From: Wayne Lin <Wayne.Lin@amd.com>
To: <amd-gfx@lists.freedesktop.org>
Cc: Harry Wentland <harry.wentland@amd.com>,
Leo Li <sunpeng.li@amd.com>,
Aurabindo Pillai <aurabindo.pillai@amd.com>,
Roman Li <roman.li@amd.com>, Wayne Lin <wayne.lin@amd.com>,
Tom Chung <chiahsuan.chung@amd.com>,
"Fangzhi Zuo" <jerry.zuo@amd.com>,
Dan Wheeler <daniel.wheeler@amd.com>, Ray Wu <Ray.Wu@amd.com>,
Ivan Lipski <ivan.lipski@amd.com>, Alex Hung <alex.hung@amd.com>,
Zheng Austin <Austin.Zheng@amd.com>,
Dillon Varone <dillon.varone@amd.com>
Subject: [PATCH 15/21] drm/amd/display: Match expected data types
Date: Wed, 28 Jan 2026 09:51:40 +0800 [thread overview]
Message-ID: <20260128015538.568712-16-Wayne.Lin@amd.com> (raw)
In-Reply-To: <20260128015538.568712-1-Wayne.Lin@amd.com>
From: Zheng Austin <Austin.Zheng@amd.com>
[Why/How]
Data types should match what is expected.
Update/cast data accordingly.
Also change ASSERT to use DML_ASSERT instead
Reviewed-by: Dillon Varone <dillon.varone@amd.com>
Signed-off-by: Zheng Austin <Austin.Zheng@amd.com>
Signed-off-by: Wayne Lin <wayne.lin@amd.com>
---
.../src/dml2_core/dml2_core_dcn4_calcs.c | 4 +--
.../dml21/src/dml2_dpmm/dml2_dpmm_dcn4.c | 34 +++++++++----------
2 files changed, 19 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
index 37699cc9e5c1..ca5ac3c0deb5 100644
--- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
+++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
@@ -7080,7 +7080,7 @@ static void calculate_excess_vactive_bandwidth_required(
static double uclk_khz_to_dram_bw_mbps(unsigned long uclk_khz, const struct dml2_dram_params *dram_config, const struct dml2_mcg_dram_bw_to_min_clk_table *dram_bw_table)
{
double bw_mbps = 0;
- int i;
+ unsigned int i;
if (!dram_config->alt_clock_bw_conversion)
bw_mbps = ((double)uclk_khz * dram_config->channel_count * dram_config->channel_width_bytes * dram_config->transactions_per_clock) / 1000.0;
@@ -7091,7 +7091,7 @@ static double uclk_khz_to_dram_bw_mbps(unsigned long uclk_khz, const struct dml2
break;
}
- ASSERT(bw_mbps > 0);
+ DML_ASSERT(bw_mbps > 0);
return bw_mbps;
}
diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.c
index 5c713f2e6eca..9d7741fd0adb 100644
--- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.c
+++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.c
@@ -17,7 +17,7 @@ static double dram_bw_kbps_to_uclk_khz(unsigned long long bandwidth_kbps, const
uclk_bytes_per_tick = dram_config->channel_count * dram_config->channel_width_bytes * dram_config->transactions_per_clock;
uclk_khz = (double)bandwidth_kbps / uclk_bytes_per_tick;
} else {
- int i;
+ unsigned int i;
/* For lpddr5 bytes per tick changes with mpstate, use table to find uclk*/
for (i = 0; i < dram_bw_table->num_entries; i++)
if (dram_bw_table->entries[i].pre_derate_dram_bw_kbps >= bandwidth_kbps) {
@@ -63,17 +63,17 @@ static void calculate_system_active_minimums(struct dml2_dpmm_map_mode_to_soc_dp
double min_uclk_latency, min_fclk_latency, min_dcfclk_latency;
const struct dml2_core_mode_support_result *mode_support_result = &in_out->display_cfg->mode_support_result;
- min_uclk_avg = dram_bw_kbps_to_uclk_khz(mode_support_result->global.active.average_bw_dram_kbps
- / ((double)in_out->soc_bb->qos_parameters.derate_table.system_active_average.dram_derate_percent_pixel / 100),
+ min_uclk_avg = dram_bw_kbps_to_uclk_khz((unsigned long long)(mode_support_result->global.active.average_bw_dram_kbps
+ / ((double)in_out->soc_bb->qos_parameters.derate_table.system_active_average.dram_derate_percent_pixel / 100)),
&in_out->soc_bb->clk_table.dram_config, &in_out->min_clk_table->dram_bw_table);
if (in_out->display_cfg->display_config.hostvm_enable)
- min_uclk_urgent = dram_bw_kbps_to_uclk_khz(mode_support_result->global.active.urgent_bw_dram_kbps
- / ((double)in_out->soc_bb->qos_parameters.derate_table.system_active_urgent.dram_derate_percent_pixel_and_vm / 100),
+ min_uclk_urgent = dram_bw_kbps_to_uclk_khz((unsigned long long)(mode_support_result->global.active.urgent_bw_dram_kbps
+ / ((double)in_out->soc_bb->qos_parameters.derate_table.system_active_urgent.dram_derate_percent_pixel_and_vm / 100)),
&in_out->soc_bb->clk_table.dram_config, &in_out->min_clk_table->dram_bw_table);
else
- min_uclk_urgent = dram_bw_kbps_to_uclk_khz(mode_support_result->global.active.urgent_bw_dram_kbps
- / ((double)in_out->soc_bb->qos_parameters.derate_table.system_active_urgent.dram_derate_percent_pixel / 100),
+ min_uclk_urgent = dram_bw_kbps_to_uclk_khz((unsigned long long)(mode_support_result->global.active.urgent_bw_dram_kbps
+ / ((double)in_out->soc_bb->qos_parameters.derate_table.system_active_urgent.dram_derate_percent_pixel / 100)),
&in_out->soc_bb->clk_table.dram_config, &in_out->min_clk_table->dram_bw_table);
min_uclk_bw = min_uclk_urgent > min_uclk_avg ? min_uclk_urgent : min_uclk_avg;
@@ -111,12 +111,12 @@ static void calculate_svp_prefetch_minimums(struct dml2_dpmm_map_mode_to_soc_dpm
const struct dml2_core_mode_support_result *mode_support_result = &in_out->display_cfg->mode_support_result;
/* assumes DF throttling is enabled */
- min_uclk_avg = dram_bw_kbps_to_uclk_khz(mode_support_result->global.svp_prefetch.average_bw_dram_kbps
- / ((double)in_out->soc_bb->qos_parameters.derate_table.dcn_mall_prefetch_average.dram_derate_percent_pixel / 100),
+ min_uclk_avg = dram_bw_kbps_to_uclk_khz((unsigned long long)(mode_support_result->global.svp_prefetch.average_bw_dram_kbps
+ / ((double)in_out->soc_bb->qos_parameters.derate_table.dcn_mall_prefetch_average.dram_derate_percent_pixel / 100)),
&in_out->soc_bb->clk_table.dram_config, &in_out->min_clk_table->dram_bw_table);
- min_uclk_urgent = dram_bw_kbps_to_uclk_khz(mode_support_result->global.svp_prefetch.urgent_bw_dram_kbps
- / ((double)in_out->soc_bb->qos_parameters.derate_table.dcn_mall_prefetch_urgent.dram_derate_percent_pixel / 100),
+ min_uclk_urgent = dram_bw_kbps_to_uclk_khz((unsigned long long)(mode_support_result->global.svp_prefetch.urgent_bw_dram_kbps
+ / ((double)in_out->soc_bb->qos_parameters.derate_table.dcn_mall_prefetch_urgent.dram_derate_percent_pixel / 100)),
&in_out->soc_bb->clk_table.dram_config, &in_out->min_clk_table->dram_bw_table);
min_uclk_bw = min_uclk_urgent > min_uclk_avg ? min_uclk_urgent : min_uclk_avg;
@@ -144,12 +144,12 @@ static void calculate_svp_prefetch_minimums(struct dml2_dpmm_map_mode_to_soc_dpm
in_out->programming->min_clocks.dcn4x.svp_prefetch.dcfclk_khz = dml_round_up(min_dcfclk_bw > min_dcfclk_latency ? min_dcfclk_bw : min_dcfclk_latency);
/* assumes DF throttling is disabled */
- min_uclk_avg = dram_bw_kbps_to_uclk_khz(mode_support_result->global.svp_prefetch.average_bw_dram_kbps
- / ((double)in_out->soc_bb->qos_parameters.derate_table.system_active_average.dram_derate_percent_pixel / 100),
+ min_uclk_avg = dram_bw_kbps_to_uclk_khz((unsigned long long)(mode_support_result->global.svp_prefetch.average_bw_dram_kbps
+ / ((double)in_out->soc_bb->qos_parameters.derate_table.system_active_average.dram_derate_percent_pixel / 100)),
&in_out->soc_bb->clk_table.dram_config, &in_out->min_clk_table->dram_bw_table);
- min_uclk_urgent = dram_bw_kbps_to_uclk_khz(mode_support_result->global.svp_prefetch.urgent_bw_dram_kbps
- / ((double)in_out->soc_bb->qos_parameters.derate_table.system_active_urgent.dram_derate_percent_pixel / 100),
+ min_uclk_urgent = dram_bw_kbps_to_uclk_khz((unsigned long long)(mode_support_result->global.svp_prefetch.urgent_bw_dram_kbps
+ / ((double)in_out->soc_bb->qos_parameters.derate_table.system_active_urgent.dram_derate_percent_pixel / 100)),
&in_out->soc_bb->clk_table.dram_config, &in_out->min_clk_table->dram_bw_table);
min_uclk_bw = min_uclk_urgent > min_uclk_avg ? min_uclk_urgent : min_uclk_avg;
@@ -185,8 +185,8 @@ static void calculate_idle_minimums(struct dml2_dpmm_map_mode_to_soc_dpm_params_
double min_uclk_latency, min_fclk_latency, min_dcfclk_latency;
const struct dml2_core_mode_support_result *mode_support_result = &in_out->display_cfg->mode_support_result;
- min_uclk_avg = dram_bw_kbps_to_uclk_khz(mode_support_result->global.active.average_bw_dram_kbps
- / ((double)in_out->soc_bb->qos_parameters.derate_table.system_idle_average.dram_derate_percent_pixel / 100),
+ min_uclk_avg = dram_bw_kbps_to_uclk_khz((unsigned long long)(mode_support_result->global.active.average_bw_dram_kbps
+ / ((double)in_out->soc_bb->qos_parameters.derate_table.system_idle_average.dram_derate_percent_pixel / 100)),
&in_out->soc_bb->clk_table.dram_config, &in_out->min_clk_table->dram_bw_table);
min_fclk_avg = (double)mode_support_result->global.active.average_bw_sdp_kbps / in_out->soc_bb->fabric_datapath_to_dcn_data_return_bytes;
--
2.43.0
next prev parent reply other threads:[~2026-01-28 2:00 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-01-28 1:51 [PATCH 00/21] DC Patches February 02, 2026 Wayne Lin
2026-01-28 1:51 ` [PATCH 01/21] drm/amd/display: Migrate DCCG register access from hwseq to dccg component Wayne Lin
2026-01-28 1:51 ` [PATCH 02/21] drm/amd/display: Add lpddr5 handling to dml2.1 Wayne Lin
2026-01-28 1:51 ` [PATCH 03/21] drm/amd/display: External panel replay fsm control Wayne Lin
2026-01-28 1:51 ` [PATCH 04/21] drm/amd/display: Make DCN35 OTG disable w/a reusable Wayne Lin
2026-01-28 1:51 ` [PATCH 05/21] drm/amd/display: Make DSC FGCG a DSC block level function Wayne Lin
2026-01-28 1:51 ` [PATCH 06/21] drm/amd/display: Make some DCN35 DCCG symbols non-static Wayne Lin
2026-01-28 1:51 ` [PATCH 07/21] drm/amd/display: Fix writeback on DCN 3.2+ Wayne Lin
2026-01-28 1:51 ` [PATCH 08/21] drm/amd/display: Fix IGT link training failure on Replay panel Wayne Lin
2026-01-28 1:51 ` [PATCH 09/21] drm/amd/display: Fix system resume lag issue Wayne Lin
2026-01-28 1:51 ` [PATCH 10/21] drm/amd/display: Add oem panel config for new features Wayne Lin
2026-01-28 1:51 ` [PATCH 11/21] drm/amd/display: Fix IGT ILR link training failure on Replay panel Wayne Lin
2026-01-28 1:51 ` [PATCH 12/21] drm/amd/display: Fix a NULL pointer dereference in dcn20_hwseq.c Wayne Lin
2026-01-28 1:51 ` [PATCH 13/21] drm/amd/display: Add Gfx Base Case For Linear Tiling Handling Wayne Lin
2026-02-16 15:16 ` Timur Kristóf
2026-01-28 1:51 ` [PATCH 14/21] drm/amd/display: Migrate DIO registers access from hwseq to dio component Wayne Lin
2026-01-28 1:51 ` Wayne Lin [this message]
2026-01-28 1:51 ` [PATCH 16/21] drm/amd/display: Add CRC 32-bit mode support for DCN3.6+ Wayne Lin
2026-01-28 1:51 ` [PATCH 17/21] drm/amd/display: Init DMUB DPIA Only for APU Wayne Lin
2026-01-28 1:51 ` [PATCH 18/21] drm/amd/display: DIO memory leak fix Wayne Lin
2026-01-28 1:51 ` [PATCH 19/21] drm/amd/display: Add Handling for gfxversion DcGfxBase Wayne Lin
2026-01-28 1:51 ` [PATCH 20/21] drm/amd/display: [FW Promotion] Release 0.1.45.0 Wayne Lin
2026-01-28 1:51 ` [PATCH 21/21] drm/amd/display: Promote DC to 3.2.368 Wayne Lin
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