From: Wayne Lin <Wayne.Lin@amd.com>
To: <amd-gfx@lists.freedesktop.org>
Cc: Harry Wentland <harry.wentland@amd.com>,
Leo Li <sunpeng.li@amd.com>,
Aurabindo Pillai <aurabindo.pillai@amd.com>,
Roman Li <roman.li@amd.com>, Wayne Lin <wayne.lin@amd.com>,
Tom Chung <chiahsuan.chung@amd.com>,
"Fangzhi Zuo" <jerry.zuo@amd.com>,
Dan Wheeler <daniel.wheeler@amd.com>, Ray Wu <Ray.Wu@amd.com>,
Ivan Lipski <ivan.lipski@amd.com>, Alex Hung <alex.hung@amd.com>,
Peichen Huang <PeiChen.Huang@amd.com>,
Robin Chen <robin.chen@amd.com>
Subject: [PATCH 03/21] drm/amd/display: External panel replay fsm control
Date: Wed, 28 Jan 2026 09:51:28 +0800 [thread overview]
Message-ID: <20260128015538.568712-4-Wayne.Lin@amd.com> (raw)
In-Reply-To: <20260128015538.568712-1-Wayne.Lin@amd.com>
From: Peichen Huang <PeiChen.Huang@amd.com>
[WHY]
To correctly control external panel replay fsm.
[HOW]
1. External panel replay is 1-A option only now.
2. Update cursor update and dirty rects commands for external
panel replay support.
3. Add external panel replay support flag in dc.
Reviewed-by: Robin Chen <robin.chen@amd.com>
Signed-off-by: Peichen Huang <PeiChen.Huang@amd.com>
Signed-off-by: Wayne Lin <wayne.lin@amd.com>
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 19 +++++--
drivers/gpu/drm/amd/display/dc/dc.h | 1 +
drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c | 15 ++++--
drivers/gpu/drm/amd/display/dc/dc_types.h | 2 +-
.../dc/link/protocols/link_dp_panel_replay.c | 52 +++++++++++++++++++
5 files changed, 80 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index cb85b7ac2697..4305691ba45e 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -3860,7 +3860,7 @@ void dc_dmub_update_dirty_rect(struct dc *dc,
if (!dc_dmub_should_send_dirty_rect_cmd(dc, stream))
return;
- if (!dc_get_edp_link_panel_inst(dc, stream->link, &panel_inst))
+ if (!dc->config.frame_update_cmd_version2 && !dc_get_edp_link_panel_inst(dc, stream->link, &panel_inst))
return;
memset(&cmd, 0x0, sizeof(cmd));
@@ -3880,7 +3880,11 @@ void dc_dmub_update_dirty_rect(struct dc *dc,
if (srf_updates[i].surface->flip_immediate)
continue;
- update_dirty_rect->cmd_version = DMUB_CMD_PSR_CONTROL_VERSION_1;
+ if (dc->config.frame_update_cmd_version2)
+ update_dirty_rect->cmd_version = DMUB_CMD_CURSOR_UPDATE_VERSION_2;
+ else
+ update_dirty_rect->cmd_version = DMUB_CMD_CURSOR_UPDATE_VERSION_1;
+
update_dirty_rect->dirty_rect_count = flip_addr->dirty_rect_count;
memcpy(update_dirty_rect->src_dirty_rects, flip_addr->dirty_rects,
sizeof(flip_addr->dirty_rects));
@@ -3894,6 +3898,7 @@ void dc_dmub_update_dirty_rect(struct dc *dc,
update_dirty_rect->panel_inst = panel_inst;
update_dirty_rect->pipe_idx = j;
+ update_dirty_rect->otg_inst = pipe_ctx->stream_res.tg->inst;
dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_NO_WAIT);
}
}
@@ -3916,7 +3921,7 @@ static void build_dmub_update_dirty_rect(
if (!dc_dmub_should_send_dirty_rect_cmd(dc, stream))
return;
- if (!dc_get_edp_link_panel_inst(dc, stream->link, &panel_inst))
+ if (!dc->config.frame_update_cmd_version2 && !dc_get_edp_link_panel_inst(dc, stream->link, &panel_inst))
return;
memset(&cmd, 0x0, sizeof(cmd));
@@ -3935,7 +3940,12 @@ static void build_dmub_update_dirty_rect(
/* Do not send in immediate flip mode */
if (srf_updates[i].surface->flip_immediate)
continue;
- update_dirty_rect->cmd_version = DMUB_CMD_PSR_CONTROL_VERSION_1;
+
+ if (dc->config.frame_update_cmd_version2)
+ update_dirty_rect->cmd_version = DMUB_CMD_CURSOR_UPDATE_VERSION_2;
+ else
+ update_dirty_rect->cmd_version = DMUB_CMD_CURSOR_UPDATE_VERSION_1;
+
update_dirty_rect->dirty_rect_count = flip_addr->dirty_rect_count;
memcpy(update_dirty_rect->src_dirty_rects, flip_addr->dirty_rects,
sizeof(flip_addr->dirty_rects));
@@ -3948,6 +3958,7 @@ static void build_dmub_update_dirty_rect(
continue;
update_dirty_rect->panel_inst = panel_inst;
update_dirty_rect->pipe_idx = j;
+ update_dirty_rect->otg_inst = pipe_ctx->stream_res.tg->inst;
dc_dmub_cmd[*dmub_cmd_count].dmub_cmd = cmd;
dc_dmub_cmd[*dmub_cmd_count].wait_type = DM_DMUB_WAIT_TYPE_NO_WAIT;
(*dmub_cmd_count)++;
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index ab19b6230945..ce2eceba2ab7 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -560,6 +560,7 @@ struct dc_config {
bool enable_dpia_pre_training;
bool unify_link_enc_assignment;
bool enable_cursor_offload;
+ bool frame_update_cmd_version2;
struct spl_sharpness_range dcn_sharpness_range;
struct spl_sharpness_range dcn_override_sharpness_range;
};
diff --git a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
index dc1b3f6c22c9..e4dd5ca70987 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
+++ b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
@@ -1034,12 +1034,19 @@ static void dc_build_cursor_update_payload0(
struct pipe_ctx *pipe_ctx, uint8_t p_idx,
struct dmub_cmd_update_cursor_payload0 *payload)
{
+ struct dc *dc = pipe_ctx->stream->ctx->dc;
struct hubp *hubp = pipe_ctx->plane_res.hubp;
unsigned int panel_inst = 0;
- if (!dc_get_edp_link_panel_inst(hubp->ctx->dc,
- pipe_ctx->stream->link, &panel_inst))
- return;
+ if (dc->config.frame_update_cmd_version2 == true) {
+ /* Don't need panel_inst for command version2 */
+ payload->cmd_version = DMUB_CMD_CURSOR_UPDATE_VERSION_2;
+ } else {
+ if (!dc_get_edp_link_panel_inst(hubp->ctx->dc,
+ pipe_ctx->stream->link, &panel_inst))
+ return;
+ payload->cmd_version = DMUB_CMD_CURSOR_UPDATE_VERSION_1;
+ }
/* Payload: Cursor Rect is built from position & attribute
* x & y are obtained from postion
@@ -1052,8 +1059,8 @@ static void dc_build_cursor_update_payload0(
payload->enable = hubp->pos.cur_ctl.bits.cur_enable;
payload->pipe_idx = p_idx;
- payload->cmd_version = DMUB_CMD_PSR_CONTROL_VERSION_1;
payload->panel_inst = panel_inst;
+ payload->otg_inst = pipe_ctx->stream_res.tg->inst;
}
static void dc_build_cursor_position_update_payload0(
diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h b/drivers/gpu/drm/amd/display/dc/dc_types.h
index 0e953059ff6d..2e38b6840c71 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_types.h
@@ -1230,7 +1230,7 @@ struct replay_settings {
uint32_t replay_desync_error_fail_count;
/* The frame skip number dal send to DMUB */
uint16_t frame_skip_number;
- /* Current Panel Replay event */
+ /* Current Panel Replay events */
uint32_t replay_events;
};
diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c
index bbd6f93f5c98..cc3b44cf7662 100644
--- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c
+++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c
@@ -35,6 +35,46 @@
#define DP_SINK_PR_ENABLE_AND_CONFIGURATION 0x37B
+static unsigned int dp_pr_calc_num_static_frames(unsigned int vsync_rate_hz)
+{
+ // at least 2 frames for static screen
+ unsigned int num_frames = 2;
+
+ // get number of frames for at least 50ms
+ if (vsync_rate_hz > 40)
+ num_frames = (vsync_rate_hz + 10) / 20;
+
+ return num_frames;
+}
+
+static void dp_pr_set_static_screen_param(struct dc_link *link)
+{
+ struct dc_static_screen_params params = {0};
+ struct dc *dc = link->ctx->dc;
+ // only support DP sst for now
+ if (!dc_is_dp_sst_signal(link->connector_signal))
+ return;
+
+ for (int i = 0; i < MAX_PIPES; i++) {
+ if (dc->current_state->res_ctx.pipe_ctx[i].stream &&
+ dc->current_state->res_ctx.pipe_ctx[i].stream->link == link) {
+ struct dc_stream_state *stream = dc->current_state->res_ctx.pipe_ctx[i].stream;
+ unsigned int vsync_rate_hz = div64_u64(div64_u64(
+ (stream->timing.pix_clk_100hz * (u64)100),
+ stream->timing.v_total),
+ stream->timing.h_total);
+
+ params.triggers.cursor_update = true;
+ params.triggers.overlay_update = true;
+ params.triggers.surface_update = true;
+ params.num_frames = dp_pr_calc_num_static_frames(vsync_rate_hz);
+
+ dc_stream_set_static_screen_params(dc, &stream, 1, ¶ms);
+ break;
+ }
+ }
+}
+
static bool dp_setup_panel_replay(struct dc_link *link, const struct dc_stream_state *stream)
{
/* To-do: Setup Replay */
@@ -159,6 +199,9 @@ bool dp_pr_get_panel_inst(const struct dc *dc,
if (!dc || !link || !inst_out)
return false;
+ if (dc->config.frame_update_cmd_version2 == false)
+ return dc_get_edp_link_panel_inst(dc, link, inst_out);
+
if (!dc_is_dp_sst_signal(link->connector_signal)) /* only supoprt DP sst (eDP included) for now */
return false;
@@ -199,6 +242,9 @@ bool dp_pr_enable(struct dc_link *link, bool enable)
if (!dp_pr_get_panel_inst(dc, link, &panel_inst))
return false;
+ if (enable && !dc_is_embedded_signal(link->connector_signal))
+ dp_pr_set_static_screen_param(link);
+
if (link->replay_settings.replay_allow_active != enable) {
//for sending PR enable commands to DMUB
memset(&cmd, 0, sizeof(cmd));
@@ -276,6 +322,12 @@ bool dp_pr_copy_settings(struct dc_link *link, struct replay_context *replay_con
pipe_ctx->stream->timing.v_border_top + pipe_ctx->stream->timing.v_border_bottom) /
pipe_ctx->stream->timing.dsc_cfg.num_slices_v;
+ if (dc_is_embedded_signal(link->connector_signal))
+ cmd.pr_copy_settings.data.main_link_activity_option = 0x03;//OPTION_1C;
+ else
+ // For external DP, use option 1-A
+ cmd.pr_copy_settings.data.main_link_activity_option = 0x01;//OPTION_1A;
+
dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);
return true;
}
--
2.43.0
next prev parent reply other threads:[~2026-01-28 1:59 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-01-28 1:51 [PATCH 00/21] DC Patches February 02, 2026 Wayne Lin
2026-01-28 1:51 ` [PATCH 01/21] drm/amd/display: Migrate DCCG register access from hwseq to dccg component Wayne Lin
2026-01-28 1:51 ` [PATCH 02/21] drm/amd/display: Add lpddr5 handling to dml2.1 Wayne Lin
2026-01-28 1:51 ` Wayne Lin [this message]
2026-01-28 1:51 ` [PATCH 04/21] drm/amd/display: Make DCN35 OTG disable w/a reusable Wayne Lin
2026-01-28 1:51 ` [PATCH 05/21] drm/amd/display: Make DSC FGCG a DSC block level function Wayne Lin
2026-01-28 1:51 ` [PATCH 06/21] drm/amd/display: Make some DCN35 DCCG symbols non-static Wayne Lin
2026-01-28 1:51 ` [PATCH 07/21] drm/amd/display: Fix writeback on DCN 3.2+ Wayne Lin
2026-01-28 1:51 ` [PATCH 08/21] drm/amd/display: Fix IGT link training failure on Replay panel Wayne Lin
2026-01-28 1:51 ` [PATCH 09/21] drm/amd/display: Fix system resume lag issue Wayne Lin
2026-01-28 1:51 ` [PATCH 10/21] drm/amd/display: Add oem panel config for new features Wayne Lin
2026-01-28 1:51 ` [PATCH 11/21] drm/amd/display: Fix IGT ILR link training failure on Replay panel Wayne Lin
2026-01-28 1:51 ` [PATCH 12/21] drm/amd/display: Fix a NULL pointer dereference in dcn20_hwseq.c Wayne Lin
2026-01-28 1:51 ` [PATCH 13/21] drm/amd/display: Add Gfx Base Case For Linear Tiling Handling Wayne Lin
2026-02-16 15:16 ` Timur Kristóf
2026-01-28 1:51 ` [PATCH 14/21] drm/amd/display: Migrate DIO registers access from hwseq to dio component Wayne Lin
2026-01-28 1:51 ` [PATCH 15/21] drm/amd/display: Match expected data types Wayne Lin
2026-01-28 1:51 ` [PATCH 16/21] drm/amd/display: Add CRC 32-bit mode support for DCN3.6+ Wayne Lin
2026-01-28 1:51 ` [PATCH 17/21] drm/amd/display: Init DMUB DPIA Only for APU Wayne Lin
2026-01-28 1:51 ` [PATCH 18/21] drm/amd/display: DIO memory leak fix Wayne Lin
2026-01-28 1:51 ` [PATCH 19/21] drm/amd/display: Add Handling for gfxversion DcGfxBase Wayne Lin
2026-01-28 1:51 ` [PATCH 20/21] drm/amd/display: [FW Promotion] Release 0.1.45.0 Wayne Lin
2026-01-28 1:51 ` [PATCH 21/21] drm/amd/display: Promote DC to 3.2.368 Wayne Lin
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