* [PATCH Review V2 1/1] drm/amdgpu: Add amdgpu_regs_pcie64 debugfs node
@ 2026-03-19 6:15 Stanley.Yang
2026-03-19 13:30 ` Lazar, Lijo
0 siblings, 1 reply; 2+ messages in thread
From: Stanley.Yang @ 2026-03-19 6:15 UTC (permalink / raw)
To: amd-gfx; +Cc: Stanley.Yang
Add amdgpu_regs_pcie64 debugfs node to
read/write 64bit PCIE registers.
Changed from V1:
Remove pm_runtime_mark_last_busy
Change-Id: I0deb7a33eb8625f37e6f2435c14338e53b809849
Signed-off-by: Stanley.Yang <Stanley.Yang@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c | 112 ++++++++++++++++++++
1 file changed, 112 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
index 63b702ec972b..3ae37eb98ef9 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
@@ -617,6 +617,110 @@ static ssize_t amdgpu_debugfs_regs_pcie_write(struct file *f, const char __user
return r;
}
+/**
+ * amdgpu_debugfs_regs_pcie64_read - Read from a 64-bit PCIE register
+ *
+ * @f: open file handle
+ * @buf: User buffer to store read data in
+ * @size: Number of bytes to read
+ * @pos: Offset to seek to
+ */
+static ssize_t amdgpu_debugfs_regs_pcie64_read(struct file *f, char __user *buf,
+ size_t size, loff_t *pos)
+{
+ struct amdgpu_device *adev = file_inode(f)->i_private;
+ ssize_t result = 0;
+ int r;
+
+ if (size & 0x7 || *pos & 0x7)
+ return -EINVAL;
+
+ r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
+ if (r < 0) {
+ pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
+ return r;
+ }
+
+ r = amdgpu_virt_enable_access_debugfs(adev);
+ if (r < 0) {
+ pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
+ return r;
+ }
+
+ while (size) {
+ uint64_t value;
+
+ value = RREG64_PCIE_EXT(*pos);
+
+ r = put_user(value, (uint64_t *)buf);
+ if (r)
+ goto out;
+
+ result += 8;
+ buf += 8;
+ *pos += 8;
+ size -= 8;
+ }
+
+ r = result;
+out:
+ pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
+ amdgpu_virt_disable_access_debugfs(adev);
+ return r;
+}
+
+/**
+ * amdgpu_debugfs_regs_pcie64_write - Write to a 64-bit PCIE register
+ *
+ * @f: open file handle
+ * @buf: User buffer to write data from
+ * @size: Number of bytes to write
+ * @pos: Offset to seek to
+ */
+static ssize_t amdgpu_debugfs_regs_pcie64_write(struct file *f, const char __user *buf,
+ size_t size, loff_t *pos)
+{
+ struct amdgpu_device *adev = file_inode(f)->i_private;
+ ssize_t result = 0;
+ int r;
+
+ if (size & 0x7 || *pos & 0x7)
+ return -EINVAL;
+
+ r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
+ if (r < 0) {
+ pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
+ return r;
+ }
+
+ r = amdgpu_virt_enable_access_debugfs(adev);
+ if (r < 0) {
+ pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
+ return r;
+ }
+
+ while (size) {
+ uint64_t value;
+
+ r = get_user(value, (uint64_t *)buf);
+ if (r)
+ goto out;
+
+ WREG64_PCIE_EXT(*pos, value);
+
+ result += 8;
+ buf += 8;
+ *pos += 8;
+ size -= 8;
+ }
+
+ r = result;
+out:
+ pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
+ amdgpu_virt_disable_access_debugfs(adev);
+ return r;
+}
+
/**
* amdgpu_debugfs_regs_didt_read - Read from a DIDT register
*
@@ -1525,6 +1629,12 @@ static const struct file_operations amdgpu_debugfs_regs_pcie_fops = {
.write = amdgpu_debugfs_regs_pcie_write,
.llseek = default_llseek
};
+static const struct file_operations amdgpu_debugfs_regs_pcie64_fops = {
+ .owner = THIS_MODULE,
+ .read = amdgpu_debugfs_regs_pcie64_read,
+ .write = amdgpu_debugfs_regs_pcie64_write,
+ .llseek = default_llseek
+};
static const struct file_operations amdgpu_debugfs_regs_smc_fops = {
.owner = THIS_MODULE,
.read = amdgpu_debugfs_regs_smc_read,
@@ -1587,6 +1697,7 @@ static const struct file_operations *debugfs_regs[] = {
&amdgpu_debugfs_gprwave_fops,
&amdgpu_debugfs_regs_didt_fops,
&amdgpu_debugfs_regs_pcie_fops,
+ &amdgpu_debugfs_regs_pcie64_fops,
&amdgpu_debugfs_regs_smc_fops,
&amdgpu_debugfs_gca_config_fops,
&amdgpu_debugfs_sensors_fops,
@@ -1604,6 +1715,7 @@ static const char * const debugfs_regs_names[] = {
"amdgpu_gprwave",
"amdgpu_regs_didt",
"amdgpu_regs_pcie",
+ "amdgpu_regs_pcie64",
"amdgpu_regs_smc",
"amdgpu_gca_config",
"amdgpu_sensors",
--
2.25.1
^ permalink raw reply related [flat|nested] 2+ messages in thread* Re: [PATCH Review V2 1/1] drm/amdgpu: Add amdgpu_regs_pcie64 debugfs node
2026-03-19 6:15 [PATCH Review V2 1/1] drm/amdgpu: Add amdgpu_regs_pcie64 debugfs node Stanley.Yang
@ 2026-03-19 13:30 ` Lazar, Lijo
0 siblings, 0 replies; 2+ messages in thread
From: Lazar, Lijo @ 2026-03-19 13:30 UTC (permalink / raw)
To: Stanley.Yang, amd-gfx
On 19-Mar-26 11:45 AM, Stanley.Yang wrote:
> Add amdgpu_regs_pcie64 debugfs node to
> read/write 64bit PCIE registers.
>
> Changed from V1:
> Remove pm_runtime_mark_last_busy
>
> Change-Id: I0deb7a33eb8625f37e6f2435c14338e53b809849
<misc> I think this is no longer used.
> Signed-off-by: Stanley.Yang <Stanley.Yang@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Thanks,
Lijo
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c | 112 ++++++++++++++++++++
> 1 file changed, 112 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
> index 63b702ec972b..3ae37eb98ef9 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
> @@ -617,6 +617,110 @@ static ssize_t amdgpu_debugfs_regs_pcie_write(struct file *f, const char __user
> return r;
> }
>
> +/**
> + * amdgpu_debugfs_regs_pcie64_read - Read from a 64-bit PCIE register
> + *
> + * @f: open file handle
> + * @buf: User buffer to store read data in
> + * @size: Number of bytes to read
> + * @pos: Offset to seek to
> + */
> +static ssize_t amdgpu_debugfs_regs_pcie64_read(struct file *f, char __user *buf,
> + size_t size, loff_t *pos)
> +{
> + struct amdgpu_device *adev = file_inode(f)->i_private;
> + ssize_t result = 0;
> + int r;
> +
> + if (size & 0x7 || *pos & 0x7)
> + return -EINVAL;
> +
> + r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
> + if (r < 0) {
> + pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
> + return r;
> + }
> +
> + r = amdgpu_virt_enable_access_debugfs(adev);
> + if (r < 0) {
> + pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
> + return r;
> + }
> +
> + while (size) {
> + uint64_t value;
> +
> + value = RREG64_PCIE_EXT(*pos);
> +
> + r = put_user(value, (uint64_t *)buf);
> + if (r)
> + goto out;
> +
> + result += 8;
> + buf += 8;
> + *pos += 8;
> + size -= 8;
> + }
> +
> + r = result;
> +out:
> + pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
> + amdgpu_virt_disable_access_debugfs(adev);
> + return r;
> +}
> +
> +/**
> + * amdgpu_debugfs_regs_pcie64_write - Write to a 64-bit PCIE register
> + *
> + * @f: open file handle
> + * @buf: User buffer to write data from
> + * @size: Number of bytes to write
> + * @pos: Offset to seek to
> + */
> +static ssize_t amdgpu_debugfs_regs_pcie64_write(struct file *f, const char __user *buf,
> + size_t size, loff_t *pos)
> +{
> + struct amdgpu_device *adev = file_inode(f)->i_private;
> + ssize_t result = 0;
> + int r;
> +
> + if (size & 0x7 || *pos & 0x7)
> + return -EINVAL;
> +
> + r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
> + if (r < 0) {
> + pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
> + return r;
> + }
> +
> + r = amdgpu_virt_enable_access_debugfs(adev);
> + if (r < 0) {
> + pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
> + return r;
> + }
> +
> + while (size) {
> + uint64_t value;
> +
> + r = get_user(value, (uint64_t *)buf);
> + if (r)
> + goto out;
> +
> + WREG64_PCIE_EXT(*pos, value);
> +
> + result += 8;
> + buf += 8;
> + *pos += 8;
> + size -= 8;
> + }
> +
> + r = result;
> +out:
> + pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
> + amdgpu_virt_disable_access_debugfs(adev);
> + return r;
> +}
> +
> /**
> * amdgpu_debugfs_regs_didt_read - Read from a DIDT register
> *
> @@ -1525,6 +1629,12 @@ static const struct file_operations amdgpu_debugfs_regs_pcie_fops = {
> .write = amdgpu_debugfs_regs_pcie_write,
> .llseek = default_llseek
> };
> +static const struct file_operations amdgpu_debugfs_regs_pcie64_fops = {
> + .owner = THIS_MODULE,
> + .read = amdgpu_debugfs_regs_pcie64_read,
> + .write = amdgpu_debugfs_regs_pcie64_write,
> + .llseek = default_llseek
> +};
> static const struct file_operations amdgpu_debugfs_regs_smc_fops = {
> .owner = THIS_MODULE,
> .read = amdgpu_debugfs_regs_smc_read,
> @@ -1587,6 +1697,7 @@ static const struct file_operations *debugfs_regs[] = {
> &amdgpu_debugfs_gprwave_fops,
> &amdgpu_debugfs_regs_didt_fops,
> &amdgpu_debugfs_regs_pcie_fops,
> + &amdgpu_debugfs_regs_pcie64_fops,
> &amdgpu_debugfs_regs_smc_fops,
> &amdgpu_debugfs_gca_config_fops,
> &amdgpu_debugfs_sensors_fops,
> @@ -1604,6 +1715,7 @@ static const char * const debugfs_regs_names[] = {
> "amdgpu_gprwave",
> "amdgpu_regs_didt",
> "amdgpu_regs_pcie",
> + "amdgpu_regs_pcie64",
> "amdgpu_regs_smc",
> "amdgpu_gca_config",
> "amdgpu_sensors",
^ permalink raw reply [flat|nested] 2+ messages in thread
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