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* [PATCH] drm/amdgpu/gfx: extract common doorbell wptr helpers to amdgpu_gfx.c
@ 2026-04-29 21:31 John B. Moore
  0 siblings, 0 replies; only message in thread
From: John B. Moore @ 2026-04-29 21:31 UTC (permalink / raw)
  To: Alexander Deucher, Christian König; +Cc: amd-gfx, John Moore

From: John Moore <jbmoore61@gmail.com>

The get_wptr and set_wptr implementations for doorbell-based compute
rings are duplicated identically across gfx_v9_0, gfx_v10_0,
gfx_v11_0, gfx_v12_0, and gfx_v12_1.  Extract them into common
helpers amdgpu_gfx_get_wptr_doorbell() and
amdgpu_gfx_set_wptr_doorbell() in amdgpu_gfx.c.

The helpers are named _doorbell rather than _compute because
there is nothing compute-specific about the implementation --
they read/write the wptr via the doorbell-mapped writeback
address.

Also replaces BUG() in the non-doorbell fallback path with
WARN_ON_ONCE(), since crashing the kernel is not an appropriate
response to a programming error.

gfx_v9_4_3 is intentionally left unconverted because it uses a
different memory access pattern (wb.wb[wptr_offs] instead of
wptr_cpu_addr).

Signed-off-by: John Moore <jbmoore61@gmail.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 39 +++++++++++++++++++++++++
 drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h |  3 ++
 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c  | 32 +++-----------------
 drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c  | 33 +++------------------
 drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c  | 33 +++------------------
 drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c  | 33 +++------------------
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c   | 32 +++-----------------
 7 files changed, 62 insertions(+), 143 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
index b8ca87669..a4ffb8156 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
@@ -2686,3 +2686,42 @@ void amdgpu_debugfs_compute_sched_mask_init(struct amdgpu_device *adev)
 #endif
 }
 
+/**
+ * amdgpu_gfx_get_wptr_doorbell - common get_wptr for rings using doorbells
+ * @ring: amdgpu_ring pointer
+ *
+ * Read the write pointer from the doorbell-mapped writeback address.
+ * This is HW-agnostic and shared across GFX generations that use
+ * doorbell-based queue management.
+ */
+u64 amdgpu_gfx_get_wptr_doorbell(struct amdgpu_ring *ring)
+{
+	/* XXX check if swapping is necessary on BE */
+	if (ring->use_doorbell)
+		return atomic64_read((atomic64_t *)ring->wptr_cpu_addr);
+
+	WARN_ON_ONCE(1);
+	return 0;
+}
+
+/**
+ * amdgpu_gfx_set_wptr_doorbell - common set_wptr for rings using doorbells
+ * @ring: amdgpu_ring pointer
+ *
+ * Write the write pointer to the doorbell-mapped writeback address and
+ * ring the doorbell.  This is HW-agnostic and shared across GFX
+ * generations that use doorbell-based queue management.
+ */
+void amdgpu_gfx_set_wptr_doorbell(struct amdgpu_ring *ring)
+{
+	struct amdgpu_device *adev = ring->adev;
+
+	/* XXX check if swapping is necessary on BE */
+	if (ring->use_doorbell) {
+		atomic64_set((atomic64_t *)ring->wptr_cpu_addr, ring->wptr);
+		WDOORBELL64(ring->doorbell_index, ring->wptr);
+	} else {
+		WARN_ON_ONCE(1);
+	}
+}
+
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
index a0cf0a3b4..64578241c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
@@ -661,6 +661,9 @@ u32 amdgpu_gfx_csb_preamble_start(u32 *buffer);
 u32 amdgpu_gfx_csb_data_parser(struct amdgpu_device *adev, u32 *buffer, u32 count);
 void amdgpu_gfx_csb_preamble_end(u32 *buffer, u32 count);
 
+u64 amdgpu_gfx_get_wptr_doorbell(struct amdgpu_ring *ring);
+void amdgpu_gfx_set_wptr_doorbell(struct amdgpu_ring *ring);
+
 void amdgpu_debugfs_gfx_sched_mask_init(struct amdgpu_device *adev);
 void amdgpu_debugfs_compute_sched_mask_init(struct amdgpu_device *adev);
 
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 58c69dcb5..070b89179 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -8591,30 +8591,6 @@ static u64 gfx_v10_0_ring_get_rptr_compute(struct amdgpu_ring *ring)
 	return *(uint32_t *)ring->rptr_cpu_addr;
 }
 
-static u64 gfx_v10_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
-{
-	u64 wptr;
-
-	/* XXX check if swapping is necessary on BE */
-	if (ring->use_doorbell)
-		wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr);
-	else
-		BUG();
-	return wptr;
-}
-
-static void gfx_v10_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
-{
-	struct amdgpu_device *adev = ring->adev;
-
-	if (ring->use_doorbell) {
-		atomic64_set((atomic64_t *)ring->wptr_cpu_addr,
-			     ring->wptr);
-		WDOORBELL64(ring->doorbell_index, ring->wptr);
-	} else {
-		BUG(); /* only DOORBELL method supported on gfx10 now */
-	}
-}
 
 static void gfx_v10_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
 {
@@ -9886,8 +9862,8 @@ static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_compute = {
 	.nop = PACKET3(PACKET3_NOP, 0x3FFF),
 	.support_64bit_ptrs = true,
 	.get_rptr = gfx_v10_0_ring_get_rptr_compute,
-	.get_wptr = gfx_v10_0_ring_get_wptr_compute,
-	.set_wptr = gfx_v10_0_ring_set_wptr_compute,
+	.get_wptr = amdgpu_gfx_get_wptr_doorbell,
+	.set_wptr = amdgpu_gfx_set_wptr_doorbell,
 	.emit_frame_size =
 		20 + /* gfx_v10_0_ring_emit_gds_switch */
 		7 + /* gfx_v10_0_ring_emit_hdp_flush */
@@ -9926,8 +9902,8 @@ static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_kiq = {
 	.nop = PACKET3(PACKET3_NOP, 0x3FFF),
 	.support_64bit_ptrs = true,
 	.get_rptr = gfx_v10_0_ring_get_rptr_compute,
-	.get_wptr = gfx_v10_0_ring_get_wptr_compute,
-	.set_wptr = gfx_v10_0_ring_set_wptr_compute,
+	.get_wptr = amdgpu_gfx_get_wptr_doorbell,
+	.set_wptr = amdgpu_gfx_set_wptr_doorbell,
 	.emit_frame_size =
 		20 + /* gfx_v10_0_ring_emit_gds_switch */
 		7 + /* gfx_v10_0_ring_emit_hdp_flush */
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
index 2c6f1e25c..8aa425b15 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
@@ -5891,31 +5891,6 @@ static u64 gfx_v11_0_ring_get_rptr_compute(struct amdgpu_ring *ring)
 	return *(uint32_t *)ring->rptr_cpu_addr;
 }
 
-static u64 gfx_v11_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
-{
-	u64 wptr;
-
-	/* XXX check if swapping is necessary on BE */
-	if (ring->use_doorbell)
-		wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr);
-	else
-		BUG();
-	return wptr;
-}
-
-static void gfx_v11_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
-{
-	struct amdgpu_device *adev = ring->adev;
-
-	/* XXX check if swapping is necessary on BE */
-	if (ring->use_doorbell) {
-		atomic64_set((atomic64_t *)ring->wptr_cpu_addr,
-			     ring->wptr);
-		WDOORBELL64(ring->doorbell_index, ring->wptr);
-	} else {
-		BUG(); /* only DOORBELL method supported on gfx11 now */
-	}
-}
 
 static void gfx_v11_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
 {
@@ -7331,8 +7306,8 @@ static const struct amdgpu_ring_funcs gfx_v11_0_ring_funcs_compute = {
 	.nop = PACKET3(PACKET3_NOP, 0x3FFF),
 	.support_64bit_ptrs = true,
 	.get_rptr = gfx_v11_0_ring_get_rptr_compute,
-	.get_wptr = gfx_v11_0_ring_get_wptr_compute,
-	.set_wptr = gfx_v11_0_ring_set_wptr_compute,
+	.get_wptr = amdgpu_gfx_get_wptr_doorbell,
+	.set_wptr = amdgpu_gfx_set_wptr_doorbell,
 	.emit_frame_size =
 		5 + /* update_spm_vmid */
 		20 + /* gfx_v11_0_ring_emit_gds_switch */
@@ -7372,8 +7347,8 @@ static const struct amdgpu_ring_funcs gfx_v11_0_ring_funcs_kiq = {
 	.nop = PACKET3(PACKET3_NOP, 0x3FFF),
 	.support_64bit_ptrs = true,
 	.get_rptr = gfx_v11_0_ring_get_rptr_compute,
-	.get_wptr = gfx_v11_0_ring_get_wptr_compute,
-	.set_wptr = gfx_v11_0_ring_set_wptr_compute,
+	.get_wptr = amdgpu_gfx_get_wptr_doorbell,
+	.set_wptr = amdgpu_gfx_set_wptr_doorbell,
 	.emit_frame_size =
 		20 + /* gfx_v11_0_ring_emit_gds_switch */
 		7 + /* gfx_v11_0_ring_emit_hdp_flush */
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
index 6baac533a..7e1ec4e3e 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
@@ -4401,31 +4401,6 @@ static u64 gfx_v12_0_ring_get_rptr_compute(struct amdgpu_ring *ring)
 	return *(uint32_t *)ring->rptr_cpu_addr;
 }
 
-static u64 gfx_v12_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
-{
-	u64 wptr;
-
-	/* XXX check if swapping is necessary on BE */
-	if (ring->use_doorbell)
-		wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr);
-	else
-		BUG();
-	return wptr;
-}
-
-static void gfx_v12_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
-{
-	struct amdgpu_device *adev = ring->adev;
-
-	/* XXX check if swapping is necessary on BE */
-	if (ring->use_doorbell) {
-		atomic64_set((atomic64_t *)ring->wptr_cpu_addr,
-			     ring->wptr);
-		WDOORBELL64(ring->doorbell_index, ring->wptr);
-	} else {
-		BUG(); /* only DOORBELL method supported on gfx12 now */
-	}
-}
 
 static void gfx_v12_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
 {
@@ -5553,8 +5528,8 @@ static const struct amdgpu_ring_funcs gfx_v12_0_ring_funcs_compute = {
 	.nop = PACKET3(PACKET3_NOP, 0x3FFF),
 	.support_64bit_ptrs = true,
 	.get_rptr = gfx_v12_0_ring_get_rptr_compute,
-	.get_wptr = gfx_v12_0_ring_get_wptr_compute,
-	.set_wptr = gfx_v12_0_ring_set_wptr_compute,
+	.get_wptr = amdgpu_gfx_get_wptr_doorbell,
+	.set_wptr = amdgpu_gfx_set_wptr_doorbell,
 	.emit_frame_size =
 		7 + /* gfx_v12_0_ring_emit_hdp_flush */
 		5 + /* hdp invalidate */
@@ -5591,8 +5566,8 @@ static const struct amdgpu_ring_funcs gfx_v12_0_ring_funcs_kiq = {
 	.nop = PACKET3(PACKET3_NOP, 0x3FFF),
 	.support_64bit_ptrs = true,
 	.get_rptr = gfx_v12_0_ring_get_rptr_compute,
-	.get_wptr = gfx_v12_0_ring_get_wptr_compute,
-	.set_wptr = gfx_v12_0_ring_set_wptr_compute,
+	.get_wptr = amdgpu_gfx_get_wptr_doorbell,
+	.set_wptr = amdgpu_gfx_set_wptr_doorbell,
 	.emit_frame_size =
 		7 + /* gfx_v12_0_ring_emit_hdp_flush */
 		5 + /*hdp invalidate */
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c b/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c
index 033f15e21..47fae6c33 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c
@@ -3368,31 +3368,6 @@ static u64 gfx_v12_1_ring_get_rptr_compute(struct amdgpu_ring *ring)
 	return *(uint32_t *)ring->rptr_cpu_addr;
 }
 
-static u64 gfx_v12_1_ring_get_wptr_compute(struct amdgpu_ring *ring)
-{
-	u64 wptr;
-
-	/* XXX check if swapping is necessary on BE */
-	if (ring->use_doorbell)
-		wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr);
-	else
-		BUG();
-	return wptr;
-}
-
-static void gfx_v12_1_ring_set_wptr_compute(struct amdgpu_ring *ring)
-{
-	struct amdgpu_device *adev = ring->adev;
-
-	/* XXX check if swapping is necessary on BE */
-	if (ring->use_doorbell) {
-		atomic64_set((atomic64_t *)ring->wptr_cpu_addr,
-			     ring->wptr);
-		WDOORBELL64(ring->doorbell_index, ring->wptr);
-	} else {
-		BUG(); /* only DOORBELL method supported on gfx12 now */
-	}
-}
 
 static void gfx_v12_1_ring_emit_ib_compute(struct amdgpu_ring *ring,
 					   struct amdgpu_job *job,
@@ -3896,8 +3871,8 @@ static const struct amdgpu_ring_funcs gfx_v12_1_ring_funcs_compute = {
 	.nop = PACKET3(PACKET3_NOP, 0x3FFF),
 	.support_64bit_ptrs = true,
 	.get_rptr = gfx_v12_1_ring_get_rptr_compute,
-	.get_wptr = gfx_v12_1_ring_get_wptr_compute,
-	.set_wptr = gfx_v12_1_ring_set_wptr_compute,
+	.get_wptr = amdgpu_gfx_get_wptr_doorbell,
+	.set_wptr = amdgpu_gfx_set_wptr_doorbell,
 	.emit_frame_size =
 		7 + /* gfx_v12_1_ring_emit_pipeline_sync */
 		SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
@@ -3926,8 +3901,8 @@ static const struct amdgpu_ring_funcs gfx_v12_1_ring_funcs_kiq = {
 	.nop = PACKET3(PACKET3_NOP, 0x3FFF),
 	.support_64bit_ptrs = true,
 	.get_rptr = gfx_v12_1_ring_get_rptr_compute,
-	.get_wptr = gfx_v12_1_ring_get_wptr_compute,
-	.set_wptr = gfx_v12_1_ring_set_wptr_compute,
+	.get_wptr = amdgpu_gfx_get_wptr_doorbell,
+	.set_wptr = amdgpu_gfx_set_wptr_doorbell,
 	.emit_frame_size =
 		7 + /* gfx_v12_1_ring_emit_pipeline_sync */
 		SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 2eb32f92a..657aff0b3 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -5634,30 +5634,6 @@ static u64 gfx_v9_0_ring_get_rptr_compute(struct amdgpu_ring *ring)
 	return *ring->rptr_cpu_addr; /* gfx9 hardware is 32bit rptr */
 }
 
-static u64 gfx_v9_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
-{
-	u64 wptr;
-
-	/* XXX check if swapping is necessary on BE */
-	if (ring->use_doorbell)
-		wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr);
-	else
-		BUG();
-	return wptr;
-}
-
-static void gfx_v9_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
-{
-	struct amdgpu_device *adev = ring->adev;
-
-	/* XXX check if swapping is necessary on BE */
-	if (ring->use_doorbell) {
-		atomic64_set((atomic64_t *)ring->wptr_cpu_addr, ring->wptr);
-		WDOORBELL64(ring->doorbell_index, ring->wptr);
-	} else{
-		BUG(); /* only DOORBELL method supported on gfx9 now */
-	}
-}
 
 static void gfx_v9_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr,
 					 u64 seq, unsigned int flags)
@@ -7614,8 +7590,8 @@ static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_compute = {
 	.nop = PACKET3(PACKET3_NOP, 0x3FFF),
 	.support_64bit_ptrs = true,
 	.get_rptr = gfx_v9_0_ring_get_rptr_compute,
-	.get_wptr = gfx_v9_0_ring_get_wptr_compute,
-	.set_wptr = gfx_v9_0_ring_set_wptr_compute,
+	.get_wptr = amdgpu_gfx_get_wptr_doorbell,
+	.set_wptr = amdgpu_gfx_set_wptr_doorbell,
 	.emit_frame_size =
 		20 + /* gfx_v9_0_ring_emit_gds_switch */
 		7 + /* gfx_v9_0_ring_emit_hdp_flush */
@@ -7656,8 +7632,8 @@ static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_kiq = {
 	.nop = PACKET3(PACKET3_NOP, 0x3FFF),
 	.support_64bit_ptrs = true,
 	.get_rptr = gfx_v9_0_ring_get_rptr_compute,
-	.get_wptr = gfx_v9_0_ring_get_wptr_compute,
-	.set_wptr = gfx_v9_0_ring_set_wptr_compute,
+	.get_wptr = amdgpu_gfx_get_wptr_doorbell,
+	.set_wptr = amdgpu_gfx_set_wptr_doorbell,
 	.emit_frame_size =
 		20 + /* gfx_v9_0_ring_emit_gds_switch */
 		7 + /* gfx_v9_0_ring_emit_hdp_flush */
-- 
2.43.0


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