From: Chenyu Chen <chen-yu.chen@amd.com>
To: <amd-gfx@lists.freedesktop.org>
Cc: Harry Wentland <harry.wentland@amd.com>,
Leo Li <sunpeng.li@amd.com>,
Aurabindo Pillai <aurabindo.pillai@amd.com>,
Roman Li <roman.li@amd.com>, Wayne Lin <wayne.lin@amd.com>,
Tom Chung <chiahsuan.chung@amd.com>,
"Fangzhi Zuo" <jerry.zuo@amd.com>,
Dan Wheeler <daniel.wheeler@amd.com>, Ray Wu <Ray.Wu@amd.com>,
Ivan Lipski <ivan.lipski@amd.com>, Alex Hung <alex.hung@amd.com>,
James Lin <PingLei.Lin@amd.com>,
Chenyu Chen <Chen-Yu.Chen@amd.com>,
Tomasz Siemek <tomasz.siemek@amd.com>,
Ilya Bakoulin <ilya.bakoulin@amd.com>,
Chenyu Chen <chen-yu.chen@amd.com>
Subject: [PATCH 01/66] drm/amd/display: Decouple cursor offload hwss executors from pipe context
Date: Tue, 8 Sep 2026 19:30:54 +0800 [thread overview]
Message-ID: <20260908113338.2433445-2-chen-yu.chen@amd.com> (raw)
In-Reply-To: <20260908113338.2433445-1-chen-yu.chen@amd.com>
From: Tomasz Siemek <tomasz.siemek@amd.com>
[Why]
Hwss executors shouldn't be coupled to complex dc structs such as
pipe_ctx.
[How]
Refactor cursor offload hardware sequencer extension to accept only
the parameters required for programming cursor offload state.
Extract these parameters in the generic HWSS layer for both immediate execution
and block-sequence construction.
Reviewed-by: Ilya Bakoulin <ilya.bakoulin@amd.com>
Signed-off-by: Tomasz Siemek <tomasz.siemek@amd.com>
Signed-off-by: Chenyu Chen <chen-yu.chen@amd.com>
---
.../drm/amd/display/dc/core/dc_hw_sequencer.c | 211 ++++++++++--------
.../gpu/drm/amd/display/dc/core/dc_stream.c | 58 ++++-
.../amd/display/dc/hwss/dcn10/dcn10_hwseq.c | 10 +-
.../amd/display/dc/hwss/dcn20/dcn20_hwseq.c | 10 +-
.../amd/display/dc/hwss/dcn35/dcn35_hwseq.c | 67 +++---
.../amd/display/dc/hwss/dcn35/dcn35_hwseq.h | 10 +-
.../amd/display/dc/hwss/dcn401/dcn401_hwseq.c | 18 +-
.../amd/display/dc/hwss/dcn401/dcn401_hwseq.h | 3 +-
.../amd/display/dc/hwss/dcn50/dcn50_hwseq.c | 10 +-
.../amd/display/dc/hwss/dcn60/dcn60_hwseq.c | 18 +-
.../amd/display/dc/hwss/dcn60/dcn60_hwseq.h | 3 +-
.../drm/amd/display/dc/hwss/hw_sequencer.h | 56 +++--
12 files changed, 274 insertions(+), 200 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
index b54466e4f42b..4b8af67ff4b5 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
@@ -1319,11 +1319,7 @@ void hwss_build_fast_sequence(struct dc *dc,
cursor_pipe_to_program = current_pipe;
if (enable_cursor_offload && dc->hwss.begin_cursor_offload_update) {
- block_sequence[*num_steps].params.begin_cursor_offload_update_params.dc = dc;
- block_sequence[*num_steps].params.begin_cursor_offload_update_params.pipe_ctx =
- current_pipe;
- block_sequence[*num_steps].func = HWSS_BEGIN_CURSOR_OFFLOAD_UPDATE;
- (*num_steps)++;
+ hwss_add_begin_cursor_offload_update(&seq_state, dc, current_pipe);
} else {
block_sequence[*num_steps].params.cursor_lock_params.dc = dc;
block_sequence[*num_steps].params.cursor_lock_params.pipe_ctx = current_pipe;
@@ -1364,22 +1360,14 @@ void hwss_build_fast_sequence(struct dc *dc,
hwss_add_set_cursor_sdr_white_level(&seq_state, current_pipe);
if (enable_cursor_offload && dc->hwss.update_cursor_offload_pipe) {
- block_sequence[*num_steps].params.update_cursor_offload_pipe_params.dc = dc;
- block_sequence[*num_steps].params.update_cursor_offload_pipe_params.pipe_ctx =
- current_pipe;
- block_sequence[*num_steps].func = HWSS_UPDATE_CURSOR_OFFLOAD_PIPE;
- (*num_steps)++;
+ hwss_add_update_cursor_offload_pipe(&seq_state, dc, current_pipe);
}
}
/* Unlock cursor attributes after all pipes have been programmed */
if (cursor_pipe_to_program) {
if (enable_cursor_offload && dc->hwss.commit_cursor_offload_update) {
- block_sequence[*num_steps].params.commit_cursor_offload_update_params.dc = dc;
- block_sequence[*num_steps].params.commit_cursor_offload_update_params.pipe_ctx =
- cursor_pipe_to_program;
- block_sequence[*num_steps].func = HWSS_COMMIT_CURSOR_OFFLOAD_UPDATE;
- (*num_steps)++;
+ hwss_add_commit_cursor_offload_update(&seq_state, dc, cursor_pipe_to_program);
} else {
block_sequence[*num_steps].params.cursor_lock_params.dc = dc;
block_sequence[*num_steps].params.cursor_lock_params.pipe_ctx = cursor_pipe_to_program;
@@ -1417,11 +1405,7 @@ void hwss_build_fast_sequence(struct dc *dc,
cursor_pipe_to_program = current_pipe;
if (enable_cursor_offload && dc->hwss.begin_cursor_offload_update) {
- block_sequence[*num_steps].params.begin_cursor_offload_update_params.dc = dc;
- block_sequence[*num_steps].params.begin_cursor_offload_update_params.pipe_ctx =
- current_pipe;
- block_sequence[*num_steps].func = HWSS_BEGIN_CURSOR_OFFLOAD_UPDATE;
- (*num_steps)++;
+ hwss_add_begin_cursor_offload_update(&seq_state, dc, current_pipe);
} else {
block_sequence[*num_steps].params.cursor_lock_params.dc = dc;
block_sequence[*num_steps].params.cursor_lock_params.pipe_ctx = current_pipe;
@@ -1437,11 +1421,7 @@ void hwss_build_fast_sequence(struct dc *dc,
(*num_steps)++;
if (enable_cursor_offload && dc->hwss.update_cursor_offload_pipe) {
- block_sequence[*num_steps].params.update_cursor_offload_pipe_params.dc = dc;
- block_sequence[*num_steps].params.update_cursor_offload_pipe_params.pipe_ctx =
- current_pipe;
- block_sequence[*num_steps].func = HWSS_UPDATE_CURSOR_OFFLOAD_PIPE;
- (*num_steps)++;
+ hwss_add_update_cursor_offload_pipe(&seq_state, dc, current_pipe);
}
if (dc->ctx->dmub_srv)
@@ -1453,11 +1433,7 @@ void hwss_build_fast_sequence(struct dc *dc,
/* Unlock cursor position after all pipes have been programmed */
if (cursor_pipe_to_program) {
if (enable_cursor_offload && dc->hwss.commit_cursor_offload_update) {
- block_sequence[*num_steps].params.commit_cursor_offload_update_params.dc = dc;
- block_sequence[*num_steps].params.commit_cursor_offload_update_params.pipe_ctx =
- cursor_pipe_to_program;
- block_sequence[*num_steps].func = HWSS_COMMIT_CURSOR_OFFLOAD_UPDATE;
- (*num_steps)++;
+ hwss_add_commit_cursor_offload_update(&seq_state, dc, cursor_pipe_to_program);
} else {
block_sequence[*num_steps].params.cursor_lock_params.dc = dc;
block_sequence[*num_steps].params.cursor_lock_params.pipe_ctx = cursor_pipe_to_program;
@@ -2127,20 +2103,20 @@ void hwss_execute_sequence(struct dc *dc,
case HUBP_MEM_PROGRAM_VIEWPORT:
hwss_hubp_mem_program_viewport(params);
break;
- case ABORT_CURSOR_OFFLOAD_UPDATE:
- hwss_abort_cursor_offload_update(params);
- break;
case HWSS_CURSOR_LOCK:
hwss_cursor_lock(params);
break;
case HWSS_BEGIN_CURSOR_OFFLOAD_UPDATE:
- hwss_begin_cursor_offload_update(params);
+ hwss_begin_cursor_offload_update(dc, params);
break;
case HWSS_COMMIT_CURSOR_OFFLOAD_UPDATE:
- hwss_commit_cursor_offload_update(params);
+ hwss_commit_cursor_offload_update(dc, params);
break;
case HWSS_UPDATE_CURSOR_OFFLOAD_PIPE:
- hwss_update_cursor_offload_pipe(params);
+ hwss_update_cursor_offload_pipe(dc, params);
+ break;
+ case ABORT_CURSOR_OFFLOAD_UPDATE:
+ hwss_abort_cursor_offload_update(dc, params);
break;
case DC_SEND_CURSOR_INFO_TO_DMU:
hwss_send_cursor_info_to_dmu(params);
@@ -4321,15 +4297,6 @@ void hwss_hubp_mem_program_viewport(union block_sequence_params *params)
hubp->funcs->mem_program_viewport(hubp, viewport, viewport_c);
}
-void hwss_abort_cursor_offload_update(union block_sequence_params *params)
-{
- struct dc *dc = params->abort_cursor_offload_update_params.dc;
- struct pipe_ctx *pipe_ctx = params->abort_cursor_offload_update_params.pipe_ctx;
-
- if (dc && dc->hwss.abort_cursor_offload_update)
- dc->hwss.abort_cursor_offload_update(dc, pipe_ctx);
-}
-
void hwss_cursor_lock(union block_sequence_params *params)
{
struct dc *dc = params->cursor_lock_params.dc;
@@ -4340,31 +4307,45 @@ void hwss_cursor_lock(union block_sequence_params *params)
dc->hwss.cursor_lock(dc, pipe_ctx, lock);
}
-void hwss_begin_cursor_offload_update(union block_sequence_params *params)
+void hwss_begin_cursor_offload_update(struct dc *dc, union block_sequence_params *params)
{
- struct dc *dc = params->begin_cursor_offload_update_params.dc;
- struct pipe_ctx *pipe_ctx = params->begin_cursor_offload_update_params.pipe_ctx;
-
- if (dc && dc->hwss.begin_cursor_offload_update)
- dc->hwss.begin_cursor_offload_update(dc, pipe_ctx);
+ if (dc->hwss.begin_cursor_offload_update)
+ dc->hwss.begin_cursor_offload_update(
+ params->begin_cursor_offload_update_params.dmub,
+ params->begin_cursor_offload_update_params.dpp,
+ params->begin_cursor_offload_update_params.hubp,
+ params->begin_cursor_offload_update_params.stream_idx);
}
-void hwss_commit_cursor_offload_update(union block_sequence_params *params)
+void hwss_commit_cursor_offload_update(struct dc *dc, union block_sequence_params *params)
{
- struct dc *dc = params->commit_cursor_offload_update_params.dc;
- struct pipe_ctx *pipe_ctx = params->commit_cursor_offload_update_params.pipe_ctx;
-
- if (dc && dc->hwss.commit_cursor_offload_update)
- dc->hwss.commit_cursor_offload_update(dc, pipe_ctx);
+ if (dc->hwss.commit_cursor_offload_update)
+ dc->hwss.commit_cursor_offload_update(
+ params->commit_cursor_offload_update_params.dmub,
+ params->commit_cursor_offload_update_params.dpp,
+ params->commit_cursor_offload_update_params.hubp,
+ params->commit_cursor_offload_update_params.stream_idx);
}
-void hwss_update_cursor_offload_pipe(union block_sequence_params *params)
+void hwss_update_cursor_offload_pipe(struct dc *dc, union block_sequence_params *params)
{
- struct dc *dc = params->update_cursor_offload_pipe_params.dc;
- struct pipe_ctx *pipe_ctx = params->update_cursor_offload_pipe_params.pipe_ctx;
+ if (dc->hwss.update_cursor_offload_pipe)
+ dc->hwss.update_cursor_offload_pipe(
+ params->update_cursor_offload_pipe_params.dmub,
+ params->update_cursor_offload_pipe_params.stream_idx,
+ params->update_cursor_offload_pipe_params.pipe_idx,
+ params->update_cursor_offload_pipe_params.dpp,
+ params->update_cursor_offload_pipe_params.hubp);
+}
- if (dc && dc->hwss.update_cursor_offload_pipe)
- dc->hwss.update_cursor_offload_pipe(dc, pipe_ctx);
+void hwss_abort_cursor_offload_update(struct dc *dc, union block_sequence_params *params)
+{
+ if (dc->hwss.abort_cursor_offload_update)
+ dc->hwss.abort_cursor_offload_update(
+ params->abort_cursor_offload_update_params.dmub,
+ params->abort_cursor_offload_update_params.dpp,
+ params->abort_cursor_offload_update_params.hubp,
+ params->abort_cursor_offload_update_params.stream_idx);
}
void hwss_send_cursor_info_to_dmu(union block_sequence_params *params)
@@ -5755,18 +5736,6 @@ void hwss_add_hubp_mem_program_viewport(struct block_sequence_state *seq_state,
}
}
-void hwss_add_abort_cursor_offload_update(struct block_sequence_state *seq_state,
- struct dc *dc,
- struct pipe_ctx *pipe_ctx)
-{
- if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
- seq_state->steps[*seq_state->num_steps].func = ABORT_CURSOR_OFFLOAD_UPDATE;
- seq_state->steps[*seq_state->num_steps].params.abort_cursor_offload_update_params.dc = dc;
- seq_state->steps[*seq_state->num_steps].params.abort_cursor_offload_update_params.pipe_ctx = pipe_ctx;
- (*seq_state->num_steps)++;
- }
-}
-
void hwss_add_set_cursor_attribute(struct block_sequence_state *seq_state,
struct dc *dc,
struct pipe_ctx *pipe_ctx)
@@ -5907,18 +5876,6 @@ void hwss_add_tg_get_frame_count(struct block_sequence_state *seq_state,
}
}
-void hwss_add_begin_cursor_offload_update(struct block_sequence_state *seq_state,
- struct dc *dc,
- struct pipe_ctx *pipe_ctx)
-{
- if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
- seq_state->steps[*seq_state->num_steps].func = HWSS_BEGIN_CURSOR_OFFLOAD_UPDATE;
- seq_state->steps[*seq_state->num_steps].params.begin_cursor_offload_update_params.dc = dc;
- seq_state->steps[*seq_state->num_steps].params.begin_cursor_offload_update_params.pipe_ctx = pipe_ctx;
- (*seq_state->num_steps)++;
- }
-}
-
void hwss_add_cursor_lock(struct block_sequence_state *seq_state,
struct dc *dc,
struct pipe_ctx *pipe_ctx,
@@ -5967,10 +5924,27 @@ void hwss_add_update_cursor_offload_pipe(struct block_sequence_state *seq_state,
struct dc *dc,
struct pipe_ctx *pipe_ctx)
{
+ const struct pipe_ctx *top_pipe;
+
+ if (!dc->hwss.update_cursor_offload_pipe)
+ return;
+
+ top_pipe = resource_get_otg_master(pipe_ctx);
+ if (!top_pipe)
+ return;
+
if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
seq_state->steps[*seq_state->num_steps].func = HWSS_UPDATE_CURSOR_OFFLOAD_PIPE;
- seq_state->steps[*seq_state->num_steps].params.update_cursor_offload_pipe_params.dc = dc;
- seq_state->steps[*seq_state->num_steps].params.update_cursor_offload_pipe_params.pipe_ctx = pipe_ctx;
+ seq_state->steps[*seq_state->num_steps].params.update_cursor_offload_pipe_params.dmub =
+ dc->ctx->dmub_srv->dmub;
+ seq_state->steps[*seq_state->num_steps].params.update_cursor_offload_pipe_params.stream_idx =
+ top_pipe->pipe_idx;
+ seq_state->steps[*seq_state->num_steps].params.update_cursor_offload_pipe_params.pipe_idx =
+ pipe_ctx->pipe_idx;
+ seq_state->steps[*seq_state->num_steps].params.update_cursor_offload_pipe_params.dpp =
+ pipe_ctx->plane_res.dpp;
+ seq_state->steps[*seq_state->num_steps].params.update_cursor_offload_pipe_params.hubp =
+ pipe_ctx->plane_res.hubp;
(*seq_state->num_steps)++;
}
}
@@ -5979,10 +5953,67 @@ void hwss_add_commit_cursor_offload_update(struct block_sequence_state *seq_stat
struct dc *dc,
struct pipe_ctx *pipe_ctx)
{
+ const struct pipe_ctx *top_pipe = resource_get_otg_master(pipe_ctx);
+
+ if (!top_pipe)
+ return;
+
if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
seq_state->steps[*seq_state->num_steps].func = HWSS_COMMIT_CURSOR_OFFLOAD_UPDATE;
- seq_state->steps[*seq_state->num_steps].params.commit_cursor_offload_update_params.dc = dc;
- seq_state->steps[*seq_state->num_steps].params.commit_cursor_offload_update_params.pipe_ctx = pipe_ctx;
+ seq_state->steps[*seq_state->num_steps].params.commit_cursor_offload_update_params.dmub =
+ dc->ctx->dmub_srv->dmub;
+ seq_state->steps[*seq_state->num_steps].params.commit_cursor_offload_update_params.stream_idx =
+ top_pipe->pipe_idx;
+ seq_state->steps[*seq_state->num_steps].params.commit_cursor_offload_update_params.dpp =
+ pipe_ctx->plane_res.dpp;
+ seq_state->steps[*seq_state->num_steps].params.commit_cursor_offload_update_params.hubp =
+ pipe_ctx->plane_res.hubp;
+ (*seq_state->num_steps)++;
+ }
+}
+
+void hwss_add_begin_cursor_offload_update(struct block_sequence_state *seq_state,
+ struct dc *dc,
+ struct pipe_ctx *pipe_ctx)
+{
+ const struct pipe_ctx *top_pipe = resource_get_otg_master(pipe_ctx);
+
+ if (!top_pipe)
+ return;
+
+ if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
+ seq_state->steps[*seq_state->num_steps].func = HWSS_BEGIN_CURSOR_OFFLOAD_UPDATE;
+ seq_state->steps[*seq_state->num_steps].params.begin_cursor_offload_update_params.dmub =
+ dc->ctx->dmub_srv->dmub;
+ seq_state->steps[*seq_state->num_steps].params.begin_cursor_offload_update_params.stream_idx =
+ top_pipe->pipe_idx;
+ seq_state->steps[*seq_state->num_steps].params.begin_cursor_offload_update_params.dpp =
+ pipe_ctx->plane_res.dpp;
+ seq_state->steps[*seq_state->num_steps].params.begin_cursor_offload_update_params.hubp =
+ pipe_ctx->plane_res.hubp;
+ (*seq_state->num_steps)++;
+ }
+}
+
+void hwss_add_abort_cursor_offload_update(struct block_sequence_state *seq_state,
+ struct dc *dc,
+ struct pipe_ctx *pipe_ctx)
+{
+ const struct pipe_ctx *top_pipe = resource_get_otg_master(pipe_ctx);
+
+ if (!top_pipe)
+ return;
+
+ if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
+ seq_state->steps[*seq_state->num_steps].func = ABORT_CURSOR_OFFLOAD_UPDATE;
+ seq_state->steps[*seq_state->num_steps].params.abort_cursor_offload_update_params.dmub =
+ dc->ctx->dmub_srv->dmub;
+ seq_state->steps[*seq_state->num_steps].params.abort_cursor_offload_update_params.stream_idx =
+ top_pipe->pipe_idx;
+ seq_state->steps[*seq_state->num_steps].params.abort_cursor_offload_update_params.dpp =
+ pipe_ctx->plane_res.dpp;
+ seq_state->steps[*seq_state->num_steps].params.abort_cursor_offload_update_params.hubp =
+ pipe_ctx->plane_res.hubp;
(*seq_state->num_steps)++;
}
}
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
index 35d4d0d5ae34..c05428f52d88 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
@@ -323,7 +323,12 @@ void program_cursor_attributes(
pipe_to_program = pipe_ctx;
if (enable_cursor_offload && dc->hwss.begin_cursor_offload_update) {
- dc->hwss.begin_cursor_offload_update(dc, pipe_ctx);
+ struct pipe_ctx *top_pipe = resource_get_otg_master(pipe_ctx);
+
+ if (top_pipe)
+ dc->hwss.begin_cursor_offload_update(dc->ctx->dmub_srv->dmub,
+ pipe_ctx->plane_res.dpp, pipe_ctx->plane_res.hubp,
+ top_pipe->pipe_idx);
} else {
dc->hwss.cursor_lock(dc, pipe_to_program, true);
if (pipe_to_program->next_odm_pipe)
@@ -335,13 +340,24 @@ void program_cursor_attributes(
update_cursor_info_to_dmu(dc, pipe_ctx);
if (dc->hwss.set_cursor_sdr_white_level)
dc->hwss.set_cursor_sdr_white_level(pipe_ctx);
- if (enable_cursor_offload && dc->hwss.update_cursor_offload_pipe)
- dc->hwss.update_cursor_offload_pipe(dc, pipe_ctx);
+ if (enable_cursor_offload && dc->hwss.update_cursor_offload_pipe) {
+ struct pipe_ctx *top_pipe = resource_get_otg_master(pipe_ctx);
+
+ if (top_pipe)
+ dc->hwss.update_cursor_offload_pipe(dc->ctx->dmub_srv->dmub,
+ top_pipe->pipe_idx, pipe_ctx->pipe_idx,
+ pipe_ctx->plane_res.dpp, pipe_ctx->plane_res.hubp);
+ }
}
if (pipe_to_program) {
if (enable_cursor_offload && dc->hwss.commit_cursor_offload_update) {
- dc->hwss.commit_cursor_offload_update(dc, pipe_to_program);
+ struct pipe_ctx *top_pipe = resource_get_otg_master(pipe_to_program);
+
+ if (top_pipe)
+ dc->hwss.commit_cursor_offload_update(dc->ctx->dmub_srv->dmub,
+ pipe_to_program->plane_res.dpp, pipe_to_program->plane_res.hubp,
+ top_pipe->pipe_idx);
} else {
dc->hwss.cursor_lock(dc, pipe_to_program, false);
if (pipe_to_program->next_odm_pipe)
@@ -484,24 +500,42 @@ void program_cursor_position(
if (!pipe_to_program) {
pipe_to_program = pipe_ctx;
- if (enable_cursor_offload && dc->hwss.begin_cursor_offload_update)
- dc->hwss.begin_cursor_offload_update(dc, pipe_ctx);
- else
+ if (enable_cursor_offload && dc->hwss.begin_cursor_offload_update) {
+ struct pipe_ctx *top_pipe = resource_get_otg_master(pipe_ctx);
+
+ if (top_pipe)
+ dc->hwss.begin_cursor_offload_update(dc->ctx->dmub_srv->dmub,
+ pipe_ctx->plane_res.dpp, pipe_ctx->plane_res.hubp,
+ top_pipe->pipe_idx);
+ } else {
dc->hwss.cursor_lock(dc, pipe_to_program, true);
+ }
}
dc->hwss.set_cursor_position(pipe_ctx);
- if (enable_cursor_offload && dc->hwss.update_cursor_offload_pipe)
- dc->hwss.update_cursor_offload_pipe(dc, pipe_ctx);
+ if (enable_cursor_offload && dc->hwss.update_cursor_offload_pipe) {
+ struct pipe_ctx *top_pipe = resource_get_otg_master(pipe_ctx);
+
+ if (top_pipe)
+ dc->hwss.update_cursor_offload_pipe(dc->ctx->dmub_srv->dmub,
+ top_pipe->pipe_idx, pipe_ctx->pipe_idx,
+ pipe_ctx->plane_res.dpp, pipe_ctx->plane_res.hubp);
+ }
update_cursor_info_to_dmu(dc, pipe_ctx);
}
if (pipe_to_program) {
- if (enable_cursor_offload && dc->hwss.commit_cursor_offload_update)
- dc->hwss.commit_cursor_offload_update(dc, pipe_to_program);
- else
+ if (enable_cursor_offload && dc->hwss.commit_cursor_offload_update) {
+ struct pipe_ctx *top_pipe = resource_get_otg_master(pipe_to_program);
+
+ if (top_pipe)
+ dc->hwss.commit_cursor_offload_update(dc->ctx->dmub_srv->dmub,
+ pipe_to_program->plane_res.dpp, pipe_to_program->plane_res.hubp,
+ top_pipe->pipe_idx);
+ } else {
dc->hwss.cursor_lock(dc, pipe_to_program, false);
+ }
}
}
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
index 1b0fc0853045..5a163711498a 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
@@ -3145,8 +3145,14 @@ static void dcn10_update_dchubp_dpp(
}
if (pipe_ctx->stream->cursor_attributes.address.quad_part != 0) {
- if (dc->hwss.abort_cursor_offload_update)
- dc->hwss.abort_cursor_offload_update(dc, pipe_ctx);
+ if (dc_dmub_srv_is_cursor_offload_enabled(dc) && dc->hwss.abort_cursor_offload_update) {
+ struct pipe_ctx *top_pipe = resource_get_otg_master(pipe_ctx);
+
+ if (top_pipe)
+ dc->hwss.abort_cursor_offload_update(dc->ctx->dmub_srv->dmub,
+ pipe_ctx->plane_res.dpp, pipe_ctx->plane_res.hubp,
+ top_pipe->pipe_idx);
+ }
dc->hwss.set_cursor_attribute(pipe_ctx);
dc->hwss.set_cursor_position(pipe_ctx);
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
index 1e60b852e61f..4e7a005d27ef 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
@@ -1834,8 +1834,14 @@ void dcn20_update_dchubp_dpp(
if ((pipe_ctx->update_flags.bits.enable || pipe_ctx->update_flags.bits.opp_changed ||
pipe_ctx->update_flags.bits.scaler || viewport_changed == true) &&
pipe_ctx->stream->cursor_attributes.address.quad_part != 0) {
- if (dc->hwss.abort_cursor_offload_update)
- dc->hwss.abort_cursor_offload_update(dc, pipe_ctx);
+ if (dc_dmub_srv_is_cursor_offload_enabled(dc) && dc->hwss.abort_cursor_offload_update) {
+ struct pipe_ctx *top_pipe = resource_get_otg_master(pipe_ctx);
+
+ if (top_pipe)
+ dc->hwss.abort_cursor_offload_update(dc->ctx->dmub_srv->dmub,
+ pipe_ctx->plane_res.dpp, pipe_ctx->plane_res.hubp,
+ top_pipe->pipe_idx);
+ }
dc->hwss.set_cursor_attribute(pipe_ctx);
dc->hwss.set_cursor_position(pipe_ctx);
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
index 6e1079377f48..16526c66c2d1 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
@@ -1642,10 +1642,9 @@ void dcn35_hardware_release(struct dc *dc)
dc->hwss.hw_block_power_up(dc, &pg_update_state);
}
-void dcn35_abort_cursor_offload_update(struct dc *dc, const struct pipe_ctx *pipe)
+void dcn35_abort_cursor_offload_update(struct dmub_srv *dmub, struct dpp *dpp, struct hubp *hubp, uint32_t stream_idx)
{
- if (!dc_dmub_srv_is_cursor_offload_enabled(dc))
- return;
+ struct dc *dc = dpp->ctx->dc;
/*
* Insert a blank update to modify the write index and set pipe_mask to 0.
@@ -1664,56 +1663,46 @@ void dcn35_abort_cursor_offload_update(struct dc *dc, const struct pipe_ctx *pip
*/
if (dc->hwss.begin_cursor_offload_update)
- dc->hwss.begin_cursor_offload_update(dc, pipe);
+ dc->hwss.begin_cursor_offload_update(dmub, dpp, hubp, stream_idx);
if (dc->hwss.commit_cursor_offload_update)
- dc->hwss.commit_cursor_offload_update(dc, pipe);
+ dc->hwss.commit_cursor_offload_update(dmub, dpp, hubp, stream_idx);
}
-void dcn35_begin_cursor_offload_update(struct dc *dc, const struct pipe_ctx *pipe)
+void dcn35_begin_cursor_offload_update(struct dmub_srv *dmub, struct dpp *dpp, struct hubp *hubp, uint32_t stream_idx)
{
- volatile struct dmub_cursor_offload_v1 *cs = dc->ctx->dmub_srv->dmub->cursor_offload_v1;
- const struct pipe_ctx *top_pipe = resource_get_otg_master(pipe);
- uint32_t stream_idx, write_idx, payload_idx;
-
- if (!top_pipe)
- return;
+ volatile struct dmub_cursor_offload_v1 *cs = dmub->cursor_offload_v1;
+ uint32_t write_idx, payload_idx;
- stream_idx = top_pipe->pipe_idx;
write_idx = cs->offload_streams[stream_idx].write_idx + 1; /* new payload (+1) */
payload_idx = write_idx % ARRAY_SIZE(cs->offload_streams[stream_idx].payloads);
cs->offload_streams[stream_idx].payloads[payload_idx].write_idx_start = write_idx;
cs->offload_streams[stream_idx].payloads[payload_idx].pipe_mask = 0;
- if (pipe->plane_res.hubp)
- pipe->plane_res.hubp->cursor_offload = true;
+ if (hubp)
+ hubp->cursor_offload = true;
- if (pipe->plane_res.dpp)
- pipe->plane_res.dpp->cursor_offload = true;
+ if (dpp)
+ dpp->cursor_offload = true;
}
-void dcn35_commit_cursor_offload_update(struct dc *dc, const struct pipe_ctx *pipe)
+void dcn35_commit_cursor_offload_update(struct dmub_srv *dmub, struct dpp *dpp, struct hubp *hubp, uint32_t stream_idx)
{
- volatile struct dmub_cursor_offload_v1 *cs = dc->ctx->dmub_srv->dmub->cursor_offload_v1;
+ volatile struct dmub_cursor_offload_v1 *cs = dmub->cursor_offload_v1;
volatile struct dmub_shared_state_cursor_offload_stream_v1 *shared_stream;
- const struct pipe_ctx *top_pipe = resource_get_otg_master(pipe);
- uint32_t stream_idx, write_idx, payload_idx;
+ uint32_t write_idx, payload_idx;
- if (pipe->plane_res.hubp)
- pipe->plane_res.hubp->cursor_offload = false;
+ if (hubp)
+ hubp->cursor_offload = false;
- if (pipe->plane_res.dpp)
- pipe->plane_res.dpp->cursor_offload = false;
+ if (dpp)
+ dpp->cursor_offload = false;
- if (!top_pipe)
- return;
-
- stream_idx = top_pipe->pipe_idx;
write_idx = cs->offload_streams[stream_idx].write_idx + 1; /* new payload (+1) */
payload_idx = write_idx % ARRAY_SIZE(cs->offload_streams[stream_idx].payloads);
- shared_stream = &dc->ctx->dmub_srv->dmub->shared_state[DMUB_SHARED_STATE_FEATURE__CURSOR_OFFLOAD_V1]
+ shared_stream = &dmub->shared_state[DMUB_SHARED_STATE_FEATURE__CURSOR_OFFLOAD_V1]
.data.cursor_offload_v1.offload_streams[stream_idx];
shared_stream->last_write_idx = write_idx;
@@ -1722,23 +1711,17 @@ void dcn35_commit_cursor_offload_update(struct dc *dc, const struct pipe_ctx *pi
cs->offload_streams[stream_idx].payloads[payload_idx].write_idx_finish = write_idx;
}
-void dcn35_update_cursor_offload_pipe(struct dc *dc, const struct pipe_ctx *pipe)
+void dcn35_update_cursor_offload_pipe(struct dmub_srv *dmub, uint32_t stream_idx,
+ uint8_t pipe_idx, const struct dpp *dpp, const struct hubp *hubp)
{
- volatile struct dmub_cursor_offload_v1 *cs = dc->ctx->dmub_srv->dmub->cursor_offload_v1;
- const struct pipe_ctx *top_pipe = resource_get_otg_master(pipe);
- const struct hubp *hubp = pipe->plane_res.hubp;
- const struct dpp *dpp = pipe->plane_res.dpp;
+ volatile struct dmub_cursor_offload_v1 *cs = dmub->cursor_offload_v1;
volatile struct dmub_cursor_offload_pipe_data_dcn30_v1 *p;
- uint32_t stream_idx, write_idx, payload_idx;
-
- if (!top_pipe || !hubp || !dpp)
- return;
+ uint32_t write_idx, payload_idx;
- stream_idx = top_pipe->pipe_idx;
write_idx = cs->offload_streams[stream_idx].write_idx + 1; /* new payload (+1) */
payload_idx = write_idx % ARRAY_SIZE(cs->offload_streams[stream_idx].payloads);
- p = &cs->offload_streams[stream_idx].payloads[payload_idx].pipe_data[pipe->pipe_idx].dcn30;
+ p = &cs->offload_streams[stream_idx].payloads[payload_idx].pipe_data[pipe_idx].dcn30;
p->CURSOR0_0_CURSOR_SURFACE_ADDRESS = hubp->att.SURFACE_ADDR;
p->CURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH = hubp->att.SURFACE_ADDR_HIGH;
@@ -1767,7 +1750,7 @@ void dcn35_update_cursor_offload_pipe(struct dc *dc, const struct pipe_ctx *pipe
p->HUBPREQ0_CURSOR_SETTINGS__CURSOR0_DST_Y_OFFSET = hubp->att.settings.bits.dst_y_offset;
p->HUBPREQ0_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST = hubp->att.settings.bits.chunk_hdl_adjust;
- cs->offload_streams[stream_idx].payloads[payload_idx].pipe_mask |= (1u << pipe->pipe_idx);
+ cs->offload_streams[stream_idx].payloads[payload_idx].pipe_mask |= (1u << pipe_idx);
}
void dcn35_notify_cursor_offload_drr_update(struct dc *dc, struct dc_state *context,
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h
index 235ebf00bd1f..fce9acb5c2fc 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h
@@ -103,10 +103,12 @@ bool dcn35_is_dp_dig_pixel_rate_div_policy(struct pipe_ctx *pipe_ctx);
void dcn35_hardware_release(struct dc *dc);
-void dcn35_abort_cursor_offload_update(struct dc *dc, const struct pipe_ctx *pipe);
-void dcn35_begin_cursor_offload_update(struct dc *dc, const struct pipe_ctx *pipe);
-void dcn35_commit_cursor_offload_update(struct dc *dc, const struct pipe_ctx *pipe);
-void dcn35_update_cursor_offload_pipe(struct dc *dc, const struct pipe_ctx *pipe);
+void dcn35_abort_cursor_offload_update(struct dmub_srv *dmub, struct dpp *dpp, struct hubp *hubp, uint32_t stream_idx);
+void dcn35_begin_cursor_offload_update(struct dmub_srv *dmub, struct dpp *dpp, struct hubp *hubp, uint32_t stream_idx);
+void dcn35_commit_cursor_offload_update(struct dmub_srv *dmub, struct dpp *dpp,
+ struct hubp *hubp, uint32_t stream_idx);
+void dcn35_update_cursor_offload_pipe(struct dmub_srv *dmub, uint32_t stream_idx,
+ uint8_t pipe_idx, const struct dpp *dpp, const struct hubp *hubp);
void dcn35_notify_cursor_offload_drr_update(struct dc *dc, struct dc_state *context,
const struct dc_stream_state *stream);
void dcn35_program_cursor_offload_now(struct dc *dc, const struct pipe_ctx *pipe);
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
index 7b089ae5c9c3..3a5dde5c8120 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
@@ -3089,23 +3089,17 @@ void dcn401_plane_atomic_power_down(struct dc *dc,
hws->funcs.dpp_root_clock_control(hws, dpp->inst, false);
}
-void dcn401_update_cursor_offload_pipe(struct dc *dc, const struct pipe_ctx *pipe)
+void dcn401_update_cursor_offload_pipe(struct dmub_srv *dmub, uint32_t stream_idx,
+ uint8_t pipe_idx, const struct dpp *dpp, const struct hubp *hubp)
{
- volatile struct dmub_cursor_offload_v1 *cs = dc->ctx->dmub_srv->dmub->cursor_offload_v1;
- const struct pipe_ctx *top_pipe = resource_get_otg_master(pipe);
- const struct hubp *hubp = pipe->plane_res.hubp;
- const struct dpp *dpp = pipe->plane_res.dpp;
+ volatile struct dmub_cursor_offload_v1 *cs = dmub->cursor_offload_v1;
volatile struct dmub_cursor_offload_pipe_data_dcn401_v1 *p;
- uint32_t stream_idx, write_idx, payload_idx;
+ uint32_t write_idx, payload_idx;
- if (!top_pipe || !hubp || !dpp)
- return;
-
- stream_idx = top_pipe->pipe_idx;
write_idx = cs->offload_streams[stream_idx].write_idx + 1; /* new payload (+1) */
payload_idx = write_idx % ARRAY_SIZE(cs->offload_streams[stream_idx].payloads);
- p = &cs->offload_streams[stream_idx].payloads[payload_idx].pipe_data[pipe->pipe_idx].dcn401;
+ p = &cs->offload_streams[stream_idx].payloads[payload_idx].pipe_data[pipe_idx].dcn401;
p->CURSOR0_0_CURSOR_SURFACE_ADDRESS = hubp->att.SURFACE_ADDR;
p->CURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH = hubp->att.SURFACE_ADDR_HIGH;
@@ -3142,7 +3136,7 @@ void dcn401_update_cursor_offload_pipe(struct dc *dc, const struct pipe_ctx *pip
p->HUBPREQ0_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST = hubp->att.settings.bits.chunk_hdl_adjust;
p->HUBP0_DCHUBP_MALL_CONFIG__USE_MALL_FOR_CURSOR = hubp->use_mall_for_cursor;
- cs->offload_streams[stream_idx].payloads[payload_idx].pipe_mask |= (1u << pipe->pipe_idx);
+ cs->offload_streams[stream_idx].payloads[payload_idx].pipe_mask |= (1u << pipe_idx);
}
void dcn401_plane_atomic_power_down_sequence(struct dc *dc,
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h
index 756b2d98a930..81e3700d728b 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h
@@ -136,7 +136,8 @@ void dcn401_blank_pixel_data_sequence(
bool blank,
struct block_sequence_state *seq_state);
void dcn401_initialize_min_clocks(struct dc *dc);
-void dcn401_update_cursor_offload_pipe(struct dc *dc, const struct pipe_ctx *pipe);
+void dcn401_update_cursor_offload_pipe(struct dmub_srv *dmub, uint32_t stream_idx,
+ uint8_t pipe_idx, const struct dpp *dpp, const struct hubp *hubp);
void dcn401_program_all_writeback_pipes_in_tree_sequence(
struct dc *dc,
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn50/dcn50_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn50/dcn50_hwseq.c
index c13d1ad8d000..8b63e75e5ee2 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn50/dcn50_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn50/dcn50_hwseq.c
@@ -201,8 +201,14 @@ void dcn50_update_dchubp_dpp(
if ((pipe_ctx->update_flags.bits.enable || pipe_ctx->update_flags.bits.opp_changed ||
pipe_ctx->update_flags.bits.scaler || viewport_changed == true) &&
pipe_ctx->stream->cursor_attributes.address.quad_part != 0) {
- if (dc->hwss.abort_cursor_offload_update)
- dc->hwss.abort_cursor_offload_update(dc, pipe_ctx);
+ if (dc_dmub_srv_is_cursor_offload_enabled(dc) && dc->hwss.abort_cursor_offload_update) {
+ struct pipe_ctx *top_pipe = resource_get_otg_master(pipe_ctx);
+
+ if (top_pipe)
+ dc->hwss.abort_cursor_offload_update(dc->ctx->dmub_srv->dmub,
+ pipe_ctx->plane_res.dpp, pipe_ctx->plane_res.hubp,
+ top_pipe->pipe_idx);
+ }
dc->hwss.set_cursor_attribute(pipe_ctx);
dc->hwss.set_cursor_position(pipe_ctx);
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn60/dcn60_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn60/dcn60_hwseq.c
index 0e6526e92544..5936f389d936 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn60/dcn60_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn60/dcn60_hwseq.c
@@ -790,23 +790,17 @@ void dcn60_set_cursor_attribute(struct pipe_ctx *pipe_ctx)
pipe_ctx->plane_res.dpp, attributes);
}
-void dcn60_update_cursor_offload_pipe(struct dc *dc, const struct pipe_ctx *pipe)
+void dcn60_update_cursor_offload_pipe(struct dmub_srv *dmub, uint32_t stream_idx,
+ uint8_t pipe_idx, const struct dpp *dpp, const struct hubp *hubp)
{
- volatile struct dmub_cursor_offload_v1 *cs = dc->ctx->dmub_srv->dmub->cursor_offload_v1;
- const struct pipe_ctx *top_pipe = resource_get_otg_master(pipe);
- const struct hubp *hubp = pipe->plane_res.hubp;
- const struct dpp *dpp = pipe->plane_res.dpp;
+ volatile struct dmub_cursor_offload_v1 *cs = dmub->cursor_offload_v1;
volatile struct dmub_cursor_offload_pipe_data_dcn60_v1 *p;
- uint32_t stream_idx, write_idx, payload_idx;
+ uint32_t write_idx, payload_idx;
- if (!top_pipe || !hubp || !dpp)
- return;
-
- stream_idx = top_pipe->pipe_idx;
write_idx = cs->offload_streams[stream_idx].write_idx + 1; /* new payload (+1) */
payload_idx = write_idx % ARRAY_SIZE(cs->offload_streams[stream_idx].payloads);
- p = &cs->offload_streams[stream_idx].payloads[payload_idx].pipe_data[pipe->pipe_idx].dcn60;
+ p = &cs->offload_streams[stream_idx].payloads[payload_idx].pipe_data[pipe_idx].dcn60;
p->CURSOR0_0_CURSOR_SURFACE_ADDRESS = hubp->att.SURFACE_ADDR;
p->CURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH = hubp->att.SURFACE_ADDR_HIGH;
@@ -843,7 +837,7 @@ void dcn60_update_cursor_offload_pipe(struct dc *dc, const struct pipe_ctx *pipe
p->HUBPREQ0_CURSOR_SETTINGS__CURSOR0_CHUNK_HDL_ADJUST = hubp->att.settings.bits.chunk_hdl_adjust;
p->HUBPREQ0_CURSOR_SETTINGS__FORCE_CURSOR_TO_DISP_PREF = hubp->att.settings.bits.force_cursor_to_disp_pref;
- cs->offload_streams[stream_idx].payloads[payload_idx].pipe_mask |= (1u << pipe->pipe_idx);
+ cs->offload_streams[stream_idx].payloads[payload_idx].pipe_mask |= (1u << pipe_idx);
}
/**
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn60/dcn60_hwseq.h b/drivers/gpu/drm/amd/display/dc/hwss/dcn60/dcn60_hwseq.h
index b57d22d310b0..3a34150096df 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn60/dcn60_hwseq.h
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn60/dcn60_hwseq.h
@@ -24,7 +24,8 @@ enum dc_status dcn60_apply_single_controller_ctx_to_hw(
void dcn60_init_hw(struct dc *dc);
void dcn60_set_cursor_attribute(struct pipe_ctx *pipe_ctx);
-void dcn60_update_cursor_offload_pipe(struct dc *dc, const struct pipe_ctx *pipe);
+void dcn60_update_cursor_offload_pipe(struct dmub_srv *dmub, uint32_t stream_idx,
+ uint8_t pipe_idx, const struct dpp *dpp, const struct hubp *hubp);
void dcn60_program_perfmon(struct dc *dc, struct dc_state *context);
bool dcn60_apply_idle_power_optimizations(struct dc *dc, bool enable);
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h
index f75e34a09dca..0133c6156897 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h
+++ b/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h
@@ -837,11 +837,6 @@ struct hubp_program_mcache_id_and_split_coordinate_params {
struct mcache_regs_struct *mcache_regs;
};
-struct abort_cursor_offload_update_params {
- struct dc *dc;
- struct pipe_ctx *pipe_ctx;
-};
-
struct cursor_lock_params {
struct dc *dc;
struct pipe_ctx *pipe_ctx;
@@ -906,18 +901,32 @@ struct phantom_hubp_post_enable_params {
};
struct begin_cursor_offload_update_params {
- struct dc *dc;
- struct pipe_ctx *pipe_ctx;
+ struct dmub_srv *dmub;
+ struct dpp *dpp;
+ struct hubp *hubp;
+ uint32_t stream_idx;
};
struct update_cursor_offload_pipe_params {
- struct dc *dc;
- struct pipe_ctx *pipe_ctx;
+ struct dmub_srv *dmub;
+ const struct dpp *dpp;
+ const struct hubp *hubp;
+ uint32_t stream_idx;
+ uint8_t pipe_idx;
};
struct commit_cursor_offload_update_params {
- struct dc *dc;
- struct pipe_ctx *pipe_ctx;
+ struct dmub_srv *dmub;
+ struct dpp *dpp;
+ struct hubp *hubp;
+ uint32_t stream_idx;
+};
+
+struct abort_cursor_offload_update_params {
+ struct dmub_srv *dmub;
+ struct dpp *dpp;
+ struct hubp *hubp;
+ uint32_t stream_idx;
};
struct stream_enc_update_hdmi_info_packets_params {
@@ -1535,10 +1544,17 @@ struct hw_sequencer_funcs {
void (*set_cursor_position)(struct pipe_ctx *pipe);
void (*set_cursor_attribute)(struct pipe_ctx *pipe);
void (*set_cursor_sdr_white_level)(struct pipe_ctx *pipe);
- void (*abort_cursor_offload_update)(struct dc *dc, const struct pipe_ctx *pipe);
- void (*begin_cursor_offload_update)(struct dc *dc, const struct pipe_ctx *pipe);
- void (*commit_cursor_offload_update)(struct dc *dc, const struct pipe_ctx *pipe);
- void (*update_cursor_offload_pipe)(struct dc *dc, const struct pipe_ctx *pipe);
+ void (*abort_cursor_offload_update)(struct dmub_srv *dmub, struct dpp *dpp,
+ struct hubp *hubp, uint32_t stream_idx);
+ void (*begin_cursor_offload_update)(struct dmub_srv *dmub, struct dpp *dpp,
+ struct hubp *hubp, uint32_t stream_idx);
+ void (*commit_cursor_offload_update)(struct dmub_srv *dmub, struct dpp *dpp,
+ struct hubp *hubp, uint32_t stream_idx);
+ void (*update_cursor_offload_pipe)(struct dmub_srv *dmub,
+ uint32_t stream_idx,
+ uint8_t pipe_idx,
+ const struct dpp *dpp,
+ const struct hubp *hubp);
void (*notify_cursor_offload_drr_update)(struct dc *dc, struct dc_state *context,
const struct dc_stream_state *stream);
void (*program_cursor_offload_now)(struct dc *dc, const struct pipe_ctx *pipe);
@@ -2126,8 +2142,6 @@ void hwss_dpp_set_scaler(union block_sequence_params *params);
void hwss_hubp_mem_program_viewport(union block_sequence_params *params);
-void hwss_abort_cursor_offload_update(union block_sequence_params *params);
-
void hwss_send_cursor_info_to_dmu(union block_sequence_params *params);
void hwss_set_cursor_attribute(union block_sequence_params *params);
@@ -2152,11 +2166,13 @@ void hwss_phantom_hubp_post_enable(union block_sequence_params *params);
void hwss_cursor_lock(union block_sequence_params *params);
-void hwss_begin_cursor_offload_update(union block_sequence_params *params);
+void hwss_begin_cursor_offload_update(struct dc *dc, union block_sequence_params *params);
+
+void hwss_commit_cursor_offload_update(struct dc *dc, union block_sequence_params *params);
-void hwss_commit_cursor_offload_update(union block_sequence_params *params);
+void hwss_update_cursor_offload_pipe(struct dc *dc, union block_sequence_params *params);
-void hwss_update_cursor_offload_pipe(union block_sequence_params *params);
+void hwss_abort_cursor_offload_update(struct dc *dc, union block_sequence_params *params);
void hwss_setup_periodic_interrupt(struct dc *dc, struct pipe_ctx *pipe_ctx);
--
2.43.0
next prev parent reply other threads:[~2026-09-08 11:34 UTC|newest]
Thread overview: 68+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-08 11:30 [PATCH 00/66] DC Patches Sep 14 2026 Chenyu Chen
2026-09-08 11:30 ` Chenyu Chen [this message]
2026-09-08 11:30 ` [PATCH 02/66] drm/amd/display: Update LLS and UPSP programming paths Chenyu Chen
2026-09-08 11:30 ` [PATCH 03/66] drm/amd/display: Refactor RMCM into a separate module Chenyu Chen
2026-09-08 11:30 ` [PATCH 04/66] drm/amd/display: Remove SDPIF_PORT_CONTROL programming for DCN31/35/42 Chenyu Chen
2026-09-08 11:30 ` [PATCH 05/66] drm/amd/display: Test sink stream creation Chenyu Chen
2026-09-08 11:30 ` [PATCH 06/66] drm/amd/display: Test connector init helper Chenyu Chen
2026-09-08 11:31 ` [PATCH 07/66] drm/amd/display: Test HDMI connector init Chenyu Chen
2026-09-08 11:31 ` [PATCH 08/66] drm/amd/display: Test FreeSync caps update Chenyu Chen
2026-09-08 11:31 ` [PATCH 09/66] drm/amd/display: Test connector init Chenyu Chen
2026-09-08 11:31 ` [PATCH 10/66] drm/amd/display: Test forced atomic commit Chenyu Chen
2026-09-08 11:31 ` [PATCH 11/66] drm/amd/display: Test DCC reject for multi-plane format Chenyu Chen
2026-09-08 11:31 ` [PATCH 12/66] drm/amd/display: Test modifier list growth failure Chenyu Chen
2026-09-08 11:31 ` [PATCH 13/66] drm/amd/display: Test pre-GFX9 plane buffer attributes Chenyu Chen
2026-09-08 11:31 ` [PATCH 14/66] drm/amd/display: Test accepted plane atomic check Chenyu Chen
2026-09-08 11:31 ` [PATCH 15/66] drm/amd/display: Test cursor update without DC stream Chenyu Chen
2026-09-08 11:31 ` [PATCH 16/66] drm/amd/display: Test panic flush DCC teardown Chenyu Chen
2026-09-08 11:31 ` [PATCH 17/66] drm/amd/display: Test optional plane property creation Chenyu Chen
2026-09-08 11:31 ` [PATCH 18/66] drm/amd/display: Add option for certain panels to disable FEC Chenyu Chen
2026-09-08 11:31 ` [PATCH 19/66] drm/amd/display: Build MST DSC helpers for KUnit Chenyu Chen
2026-09-08 11:31 ` [PATCH 20/66] drm/amd/display: Test oversized AUX transfer Chenyu Chen
2026-09-08 11:31 ` [PATCH 21/66] drm/amd/display: Test MST connector creation Chenyu Chen
2026-09-08 11:31 ` [PATCH 22/66] drm/amd/display: Test link bandwidth readback Chenyu Chen
2026-09-08 11:31 ` [PATCH 23/66] drm/amd/display: Test cascaded Panamera check Chenyu Chen
2026-09-08 11:31 ` [PATCH 24/66] drm/amd/display: Test DSC caps validation Chenyu Chen
2026-09-08 11:31 ` [PATCH 25/66] drm/amd/display: Test MST port mode support Chenyu Chen
2026-09-08 11:31 ` [PATCH 26/66] drm/amd/display: Test FRL bandwidth lookup Chenyu Chen
2026-09-08 11:31 ` [PATCH 27/66] drm/amd/display: Test DSC precompute helpers Chenyu Chen
2026-09-08 11:31 ` [PATCH 28/66] drm/amd/display: Test DSC recompute check Chenyu Chen
2026-09-08 11:31 ` [PATCH 29/66] drm/amd/display: Test DSC config computation Chenyu Chen
2026-09-08 11:31 ` [PATCH 30/66] drm/amd/display: Test per-link DSC configs Chenyu Chen
2026-09-08 11:31 ` [PATCH 31/66] drm/amd/display: Add urgent assertion counter probe Chenyu Chen
2026-09-08 11:31 ` [PATCH 32/66] drm/amd/display: Add debug option to force optional UCLK support Chenyu Chen
2026-09-08 11:31 ` [PATCH 33/66] drm/amd/display: Honor forced RGB pixel encoding Chenyu Chen
2026-09-08 11:31 ` [PATCH 34/66] drm/amd/display: Add Replay cumulative residency query Chenyu Chen
2026-09-08 11:31 ` [PATCH 35/66] drm/amd/display: Force DSC to 8bpp for MST DP tunneling over USB4 Chenyu Chen
2026-09-08 11:31 ` [PATCH 36/66] drm/amd/display: Force DSC to 8bpp for SST " Chenyu Chen
2026-09-08 11:31 ` [PATCH 37/66] drm/amd/display: Fix peak bandwidth measurement sequence Chenyu Chen
2026-09-08 11:31 ` [PATCH 38/66] drm/amd/display: Add instance field to struct mpc Chenyu Chen
2026-09-08 11:31 ` [PATCH 39/66] drm/amd/display: Enable back alt-ch Chenyu Chen
2026-09-08 11:31 ` [PATCH 40/66] drm/amd/display: Decouple HUBP_UPDATE_PLANE_ADDR from pipe_ctx Chenyu Chen
2026-09-08 11:31 ` [PATCH 41/66] drm/amd/display: Cleanup DMUB command submission interfaces Chenyu Chen
2026-09-08 11:31 ` [PATCH 42/66] drm/amd/display: Enable power gating on dcn42b Chenyu Chen
2026-09-08 11:31 ` [PATCH 43/66] drm/amd/display: Bound DSC power gating loop by num_dsc Chenyu Chen
2026-09-08 11:31 ` [PATCH 44/66] drm/amd/display: Add lock-free memory pool Chenyu Chen
2026-09-08 11:31 ` [PATCH 45/66] drm/amd/display: Rename lock_and_validation_needed to needs_dc_state_realloc Chenyu Chen
2026-09-08 11:31 ` [PATCH 46/66] drm/amd/display: Attach only plane updates that actually changed Chenyu Chen
2026-09-08 11:31 ` [PATCH 47/66] drm/amd/display: Request DMUB HW cursor offload Chenyu Chen
2026-09-08 11:31 ` [PATCH 48/66] drm/amd/display: Send stream_update to DC only when it changed Chenyu Chen
2026-09-08 11:31 ` [PATCH 49/66] drm/amd/display: Drop dead update_type param from update_planes_and_stream_adapter Chenyu Chen
2026-09-08 11:31 ` [PATCH 50/66] drm/amd/display: Flush ISM work before releasing the stream Chenyu Chen
2026-09-08 11:31 ` [PATCH 51/66] drm/amd/display: Cap DML2.1 vmin ODM combine at 2:1 for eDP Chenyu Chen
2026-09-08 11:31 ` [PATCH 52/66] drm/amd/display: Add is_odm_enabled callback to skip init_odm on active ODM pipes Chenyu Chen
2026-09-08 11:31 ` [PATCH 53/66] drm/amd/display: Program DCC as part of address update Chenyu Chen
2026-09-08 11:31 ` [PATCH 54/66] drm/amd/display: Add instance field to struct dccg Chenyu Chen
2026-09-08 11:31 ` [PATCH 55/66] drm/amd/display: Add SPDX license identifier to dcn30_dpp_cm.c Chenyu Chen
2026-09-08 11:31 ` [PATCH 56/66] drm/amd/display: Remove MALL capabilities from DCN42B Chenyu Chen
2026-09-08 11:31 ` [PATCH 57/66] drm/amd/display: Remove MALL capabilities from DCN42B bounding box Chenyu Chen
2026-09-08 11:31 ` [PATCH 58/66] drm/amd/display: Atomize IRQ register read/modify/write ops Chenyu Chen
2026-09-08 11:31 ` [PATCH 59/66] drm/amd/display: Return success status from check_mode_supported Chenyu Chen
2026-09-08 11:31 ` [PATCH 60/66] drm/amd/display: Add condition to skip MALL calculations if there is no MALL Chenyu Chen
2026-09-08 11:31 ` [PATCH 61/66] drm/amd/display: Fix HDMI FRL audio enable Chenyu Chen
2026-09-08 11:31 ` [PATCH 62/66] drm/amd/display: Cast DP DTO pixel clock math to avoid overflow and narrowing Chenyu Chen
2026-09-08 11:31 ` [PATCH 63/66] drm/amd/display: Add inbox0 HW lock helpers for DCN35 Chenyu Chen
2026-09-08 11:31 ` [PATCH 64/66] drm/amd/display: Unify fast update classification paths Chenyu Chen
2026-09-08 11:31 ` [PATCH 65/66] drm/amd/display: Use unsigned types for FRL cap check params and HPO read_state Chenyu Chen
2026-09-08 11:31 ` [PATCH 66/66] drm/amd/display: Promote DC to 3.2.398 Chenyu Chen
2026-09-14 13:02 ` [PATCH 00/66] DC Patches Sep 14 2026 Wheeler, Daniel
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