[PATCH 66/66] drm/amd/display: Promote DC to 3.2.398

[Chenyu Chen <chen-yu.chen@amd.com>]

From: Taimur Hassan <Syed.Hassan@amd.com>

This version brings along the following updates:

 - Expand amdgpu_dm KUnit coverage across connector init, sink stream
   creation, FreeSync caps, forced atomic commit, plane modifiers, cursor
   updates, panic flush, MST connector creation, AUX transfers, link
   bandwidth readback and MST DSC configuration.
 - Refactor RMCM into a separate module.
 - Decouple cursor offload hwss executors from pipe context.
 - Decouple HUBP_UPDATE_PLANE_ADDR from pipe_ctx.
 - Rename lock_and_validation_needed to needs_dc_state_realloc.
 - Drop the dead update_type param from update_planes_and_stream_adapter.
 - Attach only plane updates and stream updates that actually changed.
 - Unify fast update classification paths.
 - Request DMUB HW cursor offload.
 - Program DCC as part of address update.
 - Update LLS and UPSP programming paths.
 - Add lock-free memory pool.
 - Add instance field to struct mpc and struct dccg.
 - Cleanup DMUB command submission interfaces.
 - Add inbox0 HW lock helpers for DCN35.
 - Atomize IRQ register read/modify/write ops.
 - Add Replay cumulative residency query.
 - Add urgent assertion counter probe.
 - Add debug option to force optional UCLK support.
 - Force DSC to 8bpp for SST and MST DP tunneling over USB4.
 - Honor forced RGB pixel encoding.
 - Add option for certain panels to disable FEC.
 - Cap DML2.1 vmin ODM combine at 2:1 for eDP.
 - Add is_odm_enabled callback to skip init_odm on active ODM pipes.
 - Remove MALL capabilities from DCN42B.
 - Skip MALL calculations when there is no MALL.
 - Enable power gating on dcn42b.
 - Remove SDPIF_PORT_CONTROL programming for DCN31/35/42.
 - Enable back alt-ch.
 - Flush ISM work before releasing the stream.
 - Fix HDMI FRL audio enable.
 - Fix peak bandwidth measurement sequence.
 - Bound the DSC power gating loop by num_dsc.
 - Cast DP DTO pixel clock math to avoid overflow and narrowing.
 - Use unsigned types for FRL cap check params and HPO read_state.
 - Return success status from check_mode_supported.
 - Add SPDX license identifier to dcn30_dpp_cm.c.

Acked-by: Tom Chung <chiahsuan.chung@amd.com>
Signed-off-by: Taimur Hassan <Syed.Hassan@amd.com>
Signed-off-by: Chenyu Chen <chen-yu.chen@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index b6c71ebb7ea7..5174a0098e75 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -67,7 +67,7 @@ struct dcn_dsc_reg_state;
 struct dcn_optc_reg_state;
 struct dcn_dccg_reg_state;
 
-#define DC_VER "3.2.397"
+#define DC_VER "3.2.398"
 
 /**
  * MAX_SURFACES - representative of the upper bound of surfaces that can be piped to a single CRTC
-- 
2.43.0