[PATCH 1/3] drm/amdgpu/vm: Check PRT uAPI flag instead of PTE flag

[PATCH 1/3] drm/amdgpu/vm: Check PRT uAPI flag instead of PTE flag

[Timur Kristóf]

This fixes sparse mappings (aka. partially resident textures).

Check the correct flags.
Since a recent refactor, the code works with uAPI flags (for
mapping buffer objects), and not PTE (page table entry) flags.

Fixes: 0fdf257286d7 ("drm/amdgpu: rework how PTE flags are generated v3")
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index e803d173e25b..1a8155bdce5e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -2091,7 +2091,7 @@ int amdgpu_vm_bo_clear_mappings(struct amdgpu_device *adev,
 		struct amdgpu_bo *bo = before->bo_va->base.bo;
 
 		amdgpu_vm_it_insert(before, &vm->va);
-		if (before->flags & AMDGPU_PTE_PRT_FLAG(adev))
+		if (before->flags & AMDGPU_VM_PAGE_PRT)
 			amdgpu_vm_prt_get(adev);
 
 		if (amdgpu_vm_is_bo_always_valid(vm, bo) &&
@@ -2106,7 +2106,7 @@ int amdgpu_vm_bo_clear_mappings(struct amdgpu_device *adev,
 		struct amdgpu_bo *bo = after->bo_va->base.bo;
 
 		amdgpu_vm_it_insert(after, &vm->va);
-		if (after->flags & AMDGPU_PTE_PRT_FLAG(adev))
+		if (after->flags & AMDGPU_VM_PAGE_PRT)
 			amdgpu_vm_prt_get(adev);
 
 		if (amdgpu_vm_is_bo_always_valid(vm, bo) &&
-- 
2.51.1

[PATCH 2/3] drm/amdgpu/uapi: Clarify comment on AMDGPU_VM_PAGE_PRT

[Timur Kristóf]

In the context of the amdgpu uAPI, the PRT flag is referring only
to unmapped pages of a partially resident texture (aka. sparse
resource), but not the full resource.

Virtual addresses marked with this flag behave as follows:
- Reads return zero
- Writes are discarded

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
---
 include/uapi/drm/amdgpu_drm.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h
index 406a42be429b..f43592997b49 100644
--- a/include/uapi/drm/amdgpu_drm.h
+++ b/include/uapi/drm/amdgpu_drm.h
@@ -883,7 +883,7 @@ struct drm_amdgpu_gem_list_handles_entry {
 #define AMDGPU_VM_PAGE_WRITEABLE	(1 << 2)
 /* executable mapping, new for VI */
 #define AMDGPU_VM_PAGE_EXECUTABLE	(1 << 3)
-/* partially resident texture */
+/* unmapped page of partially resident textures */
 #define AMDGPU_VM_PAGE_PRT		(1 << 4)
 /* MTYPE flags use bit 5 to 8 */
 #define AMDGPU_VM_MTYPE_MASK		(0xf << 5)
-- 
2.51.1

Re: [PATCH 2/3] drm/amdgpu/uapi: Clarify comment on AMDGPU_VM_PAGE_PRT

[Christian König]

On 11/18/25 17:56, Timur Kristóf wrote:
> In the context of the amdgpu uAPI, the PRT flag is referring only
> to unmapped pages of a partially resident texture (aka. sparse
> resource), but not the full resource.
> 
> Virtual addresses marked with this flag behave as follows:
> - Reads return zero
> - Writes are discarded
> 
> Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>

Reviewed-by: Christian König <christian.koenig@amd.com>

> ---
>  include/uapi/drm/amdgpu_drm.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h
> index 406a42be429b..f43592997b49 100644
> --- a/include/uapi/drm/amdgpu_drm.h
> +++ b/include/uapi/drm/amdgpu_drm.h
> @@ -883,7 +883,7 @@ struct drm_amdgpu_gem_list_handles_entry {
>  #define AMDGPU_VM_PAGE_WRITEABLE	(1 << 2)
>  /* executable mapping, new for VI */
>  #define AMDGPU_VM_PAGE_EXECUTABLE	(1 << 3)
> -/* partially resident texture */
> +/* unmapped page of partially resident textures */
>  #define AMDGPU_VM_PAGE_PRT		(1 << 4)
>  /* MTYPE flags use bit 5 to 8 */
>  #define AMDGPU_VM_MTYPE_MASK		(0xf << 5)

[PATCH 3/3] Documentation/gpu: Add PRT, PTE to amdgpu glossary

[Timur Kristóf]

PRT = Partially Resident Texture (aka. sparse residency)
PTE = Page Table Entry

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
---
 Documentation/gpu/amdgpu/amdgpu-glossary.rst | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/Documentation/gpu/amdgpu/amdgpu-glossary.rst b/Documentation/gpu/amdgpu/amdgpu-glossary.rst
index 30812d9d53c6..1270e2c42ec6 100644
--- a/Documentation/gpu/amdgpu/amdgpu-glossary.rst
+++ b/Documentation/gpu/amdgpu/amdgpu-glossary.rst
@@ -149,9 +149,15 @@ we have a dedicated glossary for Display Core at
     PPLib
       PowerPlay Library - PowerPlay is the power management component.
 
+    PRT
+      Partially Resident Texture (also known as sparse residency)
+
     PSP
         Platform Security Processor
 
+    PTE
+      Page Table Entry
+
     RB
       Render Backends. Some people called it ROPs.
 
-- 
2.51.1

Re: [PATCH 3/3] Documentation/gpu: Add PRT, PTE to amdgpu glossary

[Christian König]

On 11/18/25 17:56, Timur Kristóf wrote:
> PRT = Partially Resident Texture (aka. sparse residency)
> PTE = Page Table Entry
> 
> Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
> ---
>  Documentation/gpu/amdgpu/amdgpu-glossary.rst | 6 ++++++
>  1 file changed, 6 insertions(+)
> 
> diff --git a/Documentation/gpu/amdgpu/amdgpu-glossary.rst b/Documentation/gpu/amdgpu/amdgpu-glossary.rst
> index 30812d9d53c6..1270e2c42ec6 100644
> --- a/Documentation/gpu/amdgpu/amdgpu-glossary.rst
> +++ b/Documentation/gpu/amdgpu/amdgpu-glossary.rst
> @@ -149,9 +149,15 @@ we have a dedicated glossary for Display Core at
>      PPLib
>        PowerPlay Library - PowerPlay is the power management component.
>  
> +    PRT
> +      Partially Resident Texture (also known as sparse residency)
> +
>      PSP
>          Platform Security Processor
>  
> +    PTE
> +      Page Table Entry
> +

While at it maybe also add PDE - Page Directory Entry

With that done Reviewed-by: Christian König <christian.koenig@amd.com>

Regards,
Christian.

>      RB
>        Render Backends. Some people called it ROPs.
>  

Re: [PATCH 1/3] drm/amdgpu/vm: Check PRT uAPI flag instead of PTE flag

[Christian König]

On 11/18/25 17:56, Timur Kristóf wrote:
> This fixes sparse mappings (aka. partially resident textures).
> 
> Check the correct flags.
> Since a recent refactor, the code works with uAPI flags (for
> mapping buffer objects), and not PTE (page table entry) flags.
> 
> Fixes: 0fdf257286d7 ("drm/amdgpu: rework how PTE flags are generated v3")
> Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>

Reviewed-by: Christian König <christian.koenig@amd.com>

@Alex this needs to go into 6.18, but not older kernels.

> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> index e803d173e25b..1a8155bdce5e 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> @@ -2091,7 +2091,7 @@ int amdgpu_vm_bo_clear_mappings(struct amdgpu_device *adev,
>  		struct amdgpu_bo *bo = before->bo_va->base.bo;
>  
>  		amdgpu_vm_it_insert(before, &vm->va);
> -		if (before->flags & AMDGPU_PTE_PRT_FLAG(adev))
> +		if (before->flags & AMDGPU_VM_PAGE_PRT)
>  			amdgpu_vm_prt_get(adev);
>  
>  		if (amdgpu_vm_is_bo_always_valid(vm, bo) &&
> @@ -2106,7 +2106,7 @@ int amdgpu_vm_bo_clear_mappings(struct amdgpu_device *adev,
>  		struct amdgpu_bo *bo = after->bo_va->base.bo;
>  
>  		amdgpu_vm_it_insert(after, &vm->va);
> -		if (after->flags & AMDGPU_PTE_PRT_FLAG(adev))
> +		if (after->flags & AMDGPU_VM_PAGE_PRT)
>  			amdgpu_vm_prt_get(adev);
>  
>  		if (amdgpu_vm_is_bo_always_valid(vm, bo) &&

[PATCH 1/3] drm/amdgpu/vm: Check PRT uAPI flag instead of PTE flag

[Timur Kristóf]

This fixes sparse mappings (aka. partially resident textures).

Check the correct flags.
Since a recent refactor, the code works with uAPI flags (for
mapping buffer objects), and not PTE (page table entry) flags.

Fixes: 0fdf257286d7 ("drm/amdgpu: rework how PTE flags are generated v3")
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index e803d173e25b..1a8155bdce5e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -2091,7 +2091,7 @@ int amdgpu_vm_bo_clear_mappings(struct amdgpu_device *adev,
 		struct amdgpu_bo *bo = before->bo_va->base.bo;
 
 		amdgpu_vm_it_insert(before, &vm->va);
-		if (before->flags & AMDGPU_PTE_PRT_FLAG(adev))
+		if (before->flags & AMDGPU_VM_PAGE_PRT)
 			amdgpu_vm_prt_get(adev);
 
 		if (amdgpu_vm_is_bo_always_valid(vm, bo) &&
@@ -2106,7 +2106,7 @@ int amdgpu_vm_bo_clear_mappings(struct amdgpu_device *adev,
 		struct amdgpu_bo *bo = after->bo_va->base.bo;
 
 		amdgpu_vm_it_insert(after, &vm->va);
-		if (after->flags & AMDGPU_PTE_PRT_FLAG(adev))
+		if (after->flags & AMDGPU_VM_PAGE_PRT)
 			amdgpu_vm_prt_get(adev);
 
 		if (amdgpu_vm_is_bo_always_valid(vm, bo) &&
-- 
2.51.1

[PATCH 2/3] drm/amdgpu/uapi: Clarify comment on AMDGPU_VM_PAGE_PRT

[Timur Kristóf]

In the context of the amdgpu uAPI, the PRT flag is referring only
to unmapped pages of a partially resident texture (aka. sparse
resource), but not the full resource.

Virtual addresses marked with this flag behave as follows:
- Reads return zero
- Writes are discarded

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
---
 include/uapi/drm/amdgpu_drm.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h
index 406a42be429b..f43592997b49 100644
--- a/include/uapi/drm/amdgpu_drm.h
+++ b/include/uapi/drm/amdgpu_drm.h
@@ -883,7 +883,7 @@ struct drm_amdgpu_gem_list_handles_entry {
 #define AMDGPU_VM_PAGE_WRITEABLE	(1 << 2)
 /* executable mapping, new for VI */
 #define AMDGPU_VM_PAGE_EXECUTABLE	(1 << 3)
-/* partially resident texture */
+/* unmapped page of partially resident textures */
 #define AMDGPU_VM_PAGE_PRT		(1 << 4)
 /* MTYPE flags use bit 5 to 8 */
 #define AMDGPU_VM_MTYPE_MASK		(0xf << 5)
-- 
2.51.1