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From: Felix Kuehling <felix.kuehling@amd.com>
To: amd-gfx@lists.freedesktop.org, "Sierra Guiza,
	Alejandro (Alex)" <Alex.Sierra@amd.com>
Subject: Re: [PATCH 1/4] drm/amdgpu: add stride to calculate oss ring offsets
Date: Fri, 20 Mar 2020 10:30:35 -0400	[thread overview]
Message-ID: <2ab4f027-e9c0-f60e-53ed-507bae3c7cf4@amd.com> (raw)
In-Reply-To: <20200320002245.14932-1-alex.sierra@amd.com>

On 2020-03-19 20:22, Alex Sierra wrote:
> Arcturus and vega10 share the same vega10_ih, however both
> have different register offsets at the ih ring section.
> This variable is used to help calculate ih ring register addresses
> from the osssys, that corresponds to the current asic type.
>
> Signed-off-by: Alex Sierra <alex.sierra@amd.com>
> ---
>   drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c | 4 ++++
>   drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h | 1 +
>   2 files changed, 5 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
> index 5ed4227f304b..fa384ae9a9bc 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
> @@ -279,6 +279,10 @@ int amdgpu_irq_init(struct amdgpu_device *adev)
>   				amdgpu_hotplug_work_func);
>   	}
>   
> +	if (adev->asic_type == CHIP_ARCTURUS)
> +		adev->irq.ring_stride = 1;
> +	else
> +		adev->irq.ring_stride = 0;

This can't be right. ring_stride==0 would result in all mmIH_RING(...) 
register access to map to the same physical registers. So effectively 
everything would go to ring0.

Regards,
   Felix


>   	INIT_WORK(&adev->irq.ih1_work, amdgpu_irq_handle_ih1);
>   	INIT_WORK(&adev->irq.ih2_work, amdgpu_irq_handle_ih2);
>   
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h
> index c718e94a55c9..1ec5b735cd9e 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h
> @@ -97,6 +97,7 @@ struct amdgpu_irq {
>   	struct irq_domain		*domain; /* GPU irq controller domain */
>   	unsigned			virq[AMDGPU_MAX_IRQ_SRC_ID];
>   	uint32_t                        srbm_soft_reset;
> +	unsigned			ring_stride;
>   };
>   
>   void amdgpu_irq_disable_all(struct amdgpu_device *adev);
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      parent reply	other threads:[~2020-03-20 14:30 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-03-20  0:22 [PATCH 1/4] drm/amdgpu: add stride to calculate oss ring offsets Alex Sierra
2020-03-20  0:22 ` [PATCH 2/4] drm/amdgpu: add macro to get proper ih ring register offset Alex Sierra
2020-03-20 14:30   ` Felix Kuehling
2020-03-22 19:55     ` Sierra Guiza, Alejandro (Alex)
2020-03-20  0:22 ` [PATCH 3/4] drm/amdgpu: replace rd/wr IH ring registers using mmIH_RING_REG macro Alex Sierra
2020-03-20  0:22 ` [PATCH 4/4] drm/amdgpu: reroute VMC and UMD to IH ring 1 for arcturus Alex Sierra
2020-03-20 14:06 ` [PATCH 1/4] drm/amdgpu: add stride to calculate oss ring offsets Deucher, Alexander
2020-03-20 14:20   ` Felix Kuehling
2020-03-20 14:39     ` Deucher, Alexander
2020-03-20 14:47       ` Felix Kuehling
2020-03-20 14:57         ` Deucher, Alexander
2020-03-20 18:53     ` Christian König
2020-03-20 14:30 ` Felix Kuehling [this message]

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