* [PATCH 0/3] idle optimization patches (mall)
@ 2021-01-19 20:38 Bhawanpreet Lakha
2021-01-19 20:38 ` [PATCH 1/3] drm/amd/display: Enable programing of MALL watermarks Bhawanpreet Lakha
` (2 more replies)
0 siblings, 3 replies; 5+ messages in thread
From: Bhawanpreet Lakha @ 2021-01-19 20:38 UTC (permalink / raw)
To: nicholas.kazlauskas, alexander.deucher; +Cc: Bhawanpreet Lakha, amd-gfx
There is some missing mall code, this series updates the code.
-enable watermark programming
-dynamic cursor cache
-updates to mall eligibility check
Bhawanpreet Lakha (3):
drm/amd/display: Enable programing of MALL watermarks
drm/amd/display: Dynamic cursor cache size for MALL eligibility check
drm/amd/display: Update dcn30_apply_idle_power_optimizations() code
.../display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c | 18 +-
drivers/gpu/drm/amd/display/dc/core/dc.c | 6 +-
drivers/gpu/drm/amd/display/dc/dc.h | 6 +-
.../drm/amd/display/dc/dcn30/dcn30_hwseq.c | 182 ++++++++++++++----
.../drm/amd/display/dc/dcn30/dcn30_hwseq.h | 3 +-
.../amd/display/dc/dcn302/dcn302_resource.c | 5 +-
.../gpu/drm/amd/display/dc/inc/hw_sequencer.h | 3 +-
.../gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 5 +
8 files changed, 171 insertions(+), 57 deletions(-)
--
2.25.1
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^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH 1/3] drm/amd/display: Enable programing of MALL watermarks
2021-01-19 20:38 [PATCH 0/3] idle optimization patches (mall) Bhawanpreet Lakha
@ 2021-01-19 20:38 ` Bhawanpreet Lakha
2021-01-19 20:38 ` [PATCH 2/3] drm/amd/display: Dynamic cursor cache size for MALL eligibility check Bhawanpreet Lakha
2021-01-19 20:38 ` [PATCH 3/3] drm/amd/display: Update dcn30_apply_idle_power_optimizations() code Bhawanpreet Lakha
2 siblings, 0 replies; 5+ messages in thread
From: Bhawanpreet Lakha @ 2021-01-19 20:38 UTC (permalink / raw)
To: nicholas.kazlauskas, alexander.deucher; +Cc: Bhawanpreet Lakha, amd-gfx
uncomment watermark set d
Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
---
.../display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c | 18 +++++++++---------
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c
index ab98c259ef69..c7e5a64e06af 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c
@@ -146,15 +146,15 @@ static noinline void dcn3_build_wm_range_table(struct clk_mgr_internal *clk_mgr)
clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.max_uclk = 0xFFFF;
/* Set D - MALL - SR enter and exit times adjusted for MALL */
-// clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].valid = true;
-// clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].dml_input.pstate_latency_us = pstate_latency_us;
-// clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].dml_input.sr_exit_time_us = 2;
-// clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].dml_input.sr_enter_plus_exit_time_us = 4;
-// clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.wm_type = WATERMARKS_MALL;
-// clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.min_dcfclk = 0;
-// clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.max_dcfclk = 0xFFFF;
-// clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.min_uclk = min_uclk_mhz;
-// clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.max_uclk = 0xFFFF;
+ clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].valid = true;
+ clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].dml_input.pstate_latency_us = pstate_latency_us;
+ clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].dml_input.sr_exit_time_us = 2;
+ clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].dml_input.sr_enter_plus_exit_time_us = 4;
+ clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.wm_type = WATERMARKS_MALL;
+ clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.min_dcfclk = 0;
+ clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.max_dcfclk = 0xFFFF;
+ clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.min_uclk = min_uclk_mhz;
+ clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.max_uclk = 0xFFFF;
}
void dcn3_init_clocks(struct clk_mgr *clk_mgr_base)
--
2.25.1
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^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH 2/3] drm/amd/display: Dynamic cursor cache size for MALL eligibility check
2021-01-19 20:38 [PATCH 0/3] idle optimization patches (mall) Bhawanpreet Lakha
2021-01-19 20:38 ` [PATCH 1/3] drm/amd/display: Enable programing of MALL watermarks Bhawanpreet Lakha
@ 2021-01-19 20:38 ` Bhawanpreet Lakha
2021-01-19 20:38 ` [PATCH 3/3] drm/amd/display: Update dcn30_apply_idle_power_optimizations() code Bhawanpreet Lakha
2 siblings, 0 replies; 5+ messages in thread
From: Bhawanpreet Lakha @ 2021-01-19 20:38 UTC (permalink / raw)
To: nicholas.kazlauskas, alexander.deucher
Cc: Joshua Aberback, Aric Cyr, Bhawanpreet Lakha, amd-gfx
[Why]
Currently we use the maximum possible cursor cache size when deciding if we
should attempt to enable MALL, but this prevents us from enabling the
feature for certain key use cases.
[How]
- consider cursor bpp when calculating if the cursor fits
Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Joshua Aberback <joshua.aberback@amd.com>
Reviewed-by: Aric Cyr <aric.cyr@amd.com>
---
drivers/gpu/drm/amd/display/dc/core/dc.c | 6 ++---
drivers/gpu/drm/amd/display/dc/dc.h | 4 +--
.../drm/amd/display/dc/dcn30/dcn30_hwseq.c | 25 +++++++++++++++++--
.../drm/amd/display/dc/dcn30/dcn30_hwseq.h | 3 ++-
.../amd/display/dc/dcn302/dcn302_resource.c | 1 +
.../gpu/drm/amd/display/dc/inc/hw_sequencer.h | 3 ++-
6 files changed, 33 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 89e8e3e11862..1efc67befad4 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -3156,11 +3156,11 @@ void dc_lock_memory_clock_frequency(struct dc *dc)
core_link_enable_stream(dc->current_state, &dc->current_state->res_ctx.pipe_ctx[i]);
}
-bool dc_is_plane_eligible_for_idle_optimizaitons(struct dc *dc, struct dc_plane_state *plane)
+bool dc_is_plane_eligible_for_idle_optimizations(struct dc *dc, struct dc_plane_state *plane,
+ struct dc_cursor_attributes *cursor_attr)
{
- if (dc->hwss.does_plane_fit_in_mall && dc->hwss.does_plane_fit_in_mall(dc, plane))
+ if (dc->hwss.does_plane_fit_in_mall && dc->hwss.does_plane_fit_in_mall(dc, plane, cursor_attr))
return true;
-
return false;
}
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index 28e0b6ac1f50..e21d4602e427 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -1272,8 +1272,8 @@ enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32
void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg);
#if defined(CONFIG_DRM_AMD_DC_DCN)
-bool dc_is_plane_eligible_for_idle_optimizations(struct dc *dc,
- struct dc_plane_state *plane);
+bool dc_is_plane_eligible_for_idle_optimizations(struct dc *dc, struct dc_plane_state *plane,
+ struct dc_cursor_attributes *cursor_attr);
void dc_allow_idle_optimizations(struct dc *dc, bool allow);
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
index e5cc8f8c363f..5c546b06f551 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
@@ -814,17 +814,38 @@ bool dcn30_apply_idle_power_optimizations(struct dc *dc, bool enable)
return true;
}
-bool dcn30_does_plane_fit_in_mall(struct dc *dc, struct dc_plane_state *plane)
+bool dcn30_does_plane_fit_in_mall(struct dc *dc, struct dc_plane_state *plane, struct dc_cursor_attributes *cursor_attr)
{
// add meta size?
unsigned int surface_size = plane->plane_size.surface_pitch * plane->plane_size.surface_size.height *
(plane->format >= SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616 ? 8 : 4);
unsigned int mall_size = dc->caps.mall_size_total;
+ unsigned int cursor_size = 0;
if (dc->debug.mall_size_override)
mall_size = 1024 * 1024 * dc->debug.mall_size_override;
- return (surface_size + dc->caps.cursor_cache_size) < mall_size;
+ if (cursor_attr) {
+ cursor_size = dc->caps.max_cursor_size * dc->caps.max_cursor_size;
+
+ switch (cursor_attr->color_format) {
+ case CURSOR_MODE_MONO:
+ cursor_size /= 2;
+ break;
+ case CURSOR_MODE_COLOR_1BIT_AND:
+ case CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA:
+ case CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA:
+ cursor_size *= 4;
+ break;
+
+ case CURSOR_MODE_COLOR_64BIT_FP_PRE_MULTIPLIED:
+ case CURSOR_MODE_COLOR_64BIT_FP_UN_PRE_MULTIPLIED:
+ cursor_size *= 8;
+ break;
+ }
+ }
+
+ return (surface_size + cursor_size) < mall_size;
}
void dcn30_hardware_release(struct dc *dc)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.h b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.h
index 1103f6356e90..3b7d4812e311 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.h
@@ -65,7 +65,8 @@ void dcn30_set_avmute(struct pipe_ctx *pipe_ctx, bool enable);
void dcn30_update_info_frame(struct pipe_ctx *pipe_ctx);
void dcn30_program_dmdata_engine(struct pipe_ctx *pipe_ctx);
-bool dcn30_does_plane_fit_in_mall(struct dc *dc, struct dc_plane_state *plane);
+bool dcn30_does_plane_fit_in_mall(struct dc *dc, struct dc_plane_state *plane,
+ struct dc_cursor_attributes *cursor_attr);
bool dcn30_apply_idle_power_optimizations(struct dc *dc, bool enable);
diff --git a/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c b/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c
index 22ba0be88faf..b96b32a37178 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c
@@ -1317,6 +1317,7 @@ static bool dcn302_resource_construct(
dc->caps.min_horizontal_blanking_period = 80;
dc->caps.dmdata_alloc_size = 2048;
+ dc->caps.cursor_cache_size = dc->caps.max_cursor_size * dc->caps.max_cursor_size * 8;
dc->caps.max_slave_planes = 1;
dc->caps.post_blend_color_processing = true;
dc->caps.force_dp_tps4_for_cp2520 = true;
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
index 48378beb71c0..0586ab2ffd6a 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
@@ -218,7 +218,8 @@ struct hw_sequencer_funcs {
/* Idle Optimization Related */
bool (*apply_idle_power_optimizations)(struct dc *dc, bool enable);
- bool (*does_plane_fit_in_mall)(struct dc *dc, struct dc_plane_state *plane);
+ bool (*does_plane_fit_in_mall)(struct dc *dc, struct dc_plane_state *plane,
+ struct dc_cursor_attributes *cursor_attr);
bool (*is_abm_supported)(struct dc *dc,
struct dc_state *context, struct dc_stream_state *stream);
--
2.25.1
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^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH 3/3] drm/amd/display: Update dcn30_apply_idle_power_optimizations() code
2021-01-19 20:38 [PATCH 0/3] idle optimization patches (mall) Bhawanpreet Lakha
2021-01-19 20:38 ` [PATCH 1/3] drm/amd/display: Enable programing of MALL watermarks Bhawanpreet Lakha
2021-01-19 20:38 ` [PATCH 2/3] drm/amd/display: Dynamic cursor cache size for MALL eligibility check Bhawanpreet Lakha
@ 2021-01-19 20:38 ` Bhawanpreet Lakha
2021-01-19 22:10 ` Kazlauskas, Nicholas
2 siblings, 1 reply; 5+ messages in thread
From: Bhawanpreet Lakha @ 2021-01-19 20:38 UTC (permalink / raw)
To: nicholas.kazlauskas, alexander.deucher
Cc: Joshua Aberback, Bhawanpreet Lakha, amd-gfx
Update the function for idle optimizations
-remove hardcoded size
-enable no memory-request case
-add cursor copy
-update mall eligibility check case
Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Joshua Aberback <joshua.aberback@amd.com>
---
drivers/gpu/drm/amd/display/dc/dc.h | 2 +
.../drm/amd/display/dc/dcn30/dcn30_hwseq.c | 157 +++++++++++++-----
.../amd/display/dc/dcn302/dcn302_resource.c | 4 +-
.../gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 5 +
4 files changed, 129 insertions(+), 39 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index e21d4602e427..71d46ade24e5 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -502,6 +502,8 @@ struct dc_debug_options {
#if defined(CONFIG_DRM_AMD_DC_DCN)
bool disable_idle_power_optimizations;
unsigned int mall_size_override;
+ unsigned int mall_additional_timer_percent;
+ bool mall_error_as_fatal;
#endif
bool dmub_command_table; /* for testing only */
struct dc_bw_validation_profile bw_val_profile;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
index 5c546b06f551..dff83c6a142a 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
@@ -710,8 +710,11 @@ void dcn30_program_dmdata_engine(struct pipe_ctx *pipe_ctx)
bool dcn30_apply_idle_power_optimizations(struct dc *dc, bool enable)
{
union dmub_rb_cmd cmd;
- unsigned int surface_size, refresh_hz, denom;
uint32_t tmr_delay = 0, tmr_scale = 0;
+ struct dc_cursor_attributes cursor_attr;
+ bool cursor_cache_enable = false;
+ struct dc_stream_state *stream = NULL;
+ struct dc_plane_state *plane = NULL;
if (!dc->ctx->dmub_srv)
return false;
@@ -722,72 +725,150 @@ bool dcn30_apply_idle_power_optimizations(struct dc *dc, bool enable)
/* First, check no-memory-requests case */
for (i = 0; i < dc->current_state->stream_count; i++) {
- if (dc->current_state->stream_status[i]
- .plane_count)
+ if (dc->current_state->stream_status[i].plane_count)
/* Fail eligibility on a visible stream */
break;
}
- if (dc->current_state->stream_count == 1 // single display only
- && dc->current_state->stream_status[0].plane_count == 1 // single surface only
- && dc->current_state->stream_status[0].plane_states[0]->address.page_table_base.quad_part == 0 // no VM
- // Only 8 and 16 bit formats
- && dc->current_state->stream_status[0].plane_states[0]->format <= SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F
- && dc->current_state->stream_status[0].plane_states[0]->format >= SURFACE_PIXEL_FORMAT_GRPH_ARGB8888) {
- surface_size = dc->current_state->stream_status[0].plane_states[0]->plane_size.surface_pitch *
- dc->current_state->stream_status[0].plane_states[0]->plane_size.surface_size.height *
- (dc->current_state->stream_status[0].plane_states[0]->format >= SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616 ?
- 8 : 4);
- } else {
- // TODO: remove hard code size
- surface_size = 128 * 1024 * 1024;
+ if (i == dc->current_state->stream_count) {
+ /* Enable no-memory-requests case */
+ memset(&cmd, 0, sizeof(cmd));
+ cmd.mall.header.type = DMUB_CMD__MALL;
+ cmd.mall.header.sub_type = DMUB_CMD__MALL_ACTION_NO_DF_REQ;
+ cmd.mall.header.payload_bytes = sizeof(cmd.mall) - sizeof(cmd.mall.header);
+
+ dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd);
+ dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv);
+
+ return true;
}
- // TODO: remove hard code size
- if (surface_size < 128 * 1024 * 1024) {
- refresh_hz = div_u64((unsigned long long) dc->current_state->streams[0]->timing.pix_clk_100hz *
- 100LL,
- (dc->current_state->streams[0]->timing.v_total *
- dc->current_state->streams[0]->timing.h_total));
+ stream = dc->current_state->streams[0];
+ plane = (stream ? dc->current_state->stream_status[0].plane_states[0] : NULL);
+
+ if (stream && plane) {
+ cursor_cache_enable = stream->cursor_position.enable &&
+ plane->address.grph.cursor_cache_addr.quad_part;
+ cursor_attr = stream->cursor_attributes;
+ }
+
+ /*
+ * Second, check MALL eligibility
+ *
+ * single display only, single surface only, 8 and 16 bit formats only, no VM,
+ * do not use MALL for displays that support PSR as they use D0i3.2 in DMCUB FW
+ *
+ * TODO: When we implement multi-display, PSR displays will be allowed if there is
+ * a non-PSR display present, since in that case we can't do D0i3.2
+ */
+ if (dc->current_state->stream_count == 1 &&
+ stream->link->psr_settings.psr_version == DC_PSR_VERSION_UNSUPPORTED &&
+ dc->current_state->stream_status[0].plane_count == 1 &&
+ plane->format <= SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F &&
+ plane->format >= SURFACE_PIXEL_FORMAT_GRPH_ARGB8888 &&
+ plane->address.page_table_base.quad_part == 0 &&
+ dc->hwss.does_plane_fit_in_mall &&
+ dc->hwss.does_plane_fit_in_mall(dc, plane,
+ cursor_cache_enable ? &cursor_attr : NULL)) {
+ unsigned int v_total = stream->adjust.v_total_max ?
+ stream->adjust.v_total_max : stream->timing.v_total;
+ unsigned int refresh_hz = (unsigned long long) stream->timing.pix_clk_100hz *
+ 100LL / (v_total * stream->timing.h_total);
/*
- * Delay_Us = 65.28 * (64 + MallFrameCacheTmrDly) * 2^MallFrameCacheTmrScale
- * Delay_Us / 65.28 = (64 + MallFrameCacheTmrDly) * 2^MallFrameCacheTmrScale
- * (Delay_Us / 65.28) / 2^MallFrameCacheTmrScale = 64 + MallFrameCacheTmrDly
- * MallFrameCacheTmrDly = ((Delay_Us / 65.28) / 2^MallFrameCacheTmrScale) - 64
- * = (1000000 / refresh) / 65.28 / 2^MallFrameCacheTmrScale - 64
- * = 1000000 / (refresh * 65.28 * 2^MallFrameCacheTmrScale) - 64
- * = (1000000 * 100) / (refresh * 6528 * 2^MallFrameCacheTmrScale) - 64
+ * one frame time in microsec:
+ * Delay_Us = 1000000 / refresh
+ * dynamic_delay_us = 1000000 / refresh + 2 * stutter_period
+ *
+ * one frame time modified by 'additional timer percent' (p):
+ * Delay_Us_modified = dynamic_delay_us + dynamic_delay_us * p / 100
+ * = dynamic_delay_us * (1 + p / 100)
+ * = (1000000 / refresh + 2 * stutter_period) * (100 + p) / 100
+ * = (1000000 + 2 * stutter_period * refresh) * (100 + p) / (100 * refresh)
+ *
+ * formula for timer duration based on parameters, from regspec:
+ * dynamic_delay_us = 65.28 * (64 + MallFrameCacheTmrDly) * 2^MallFrameCacheTmrScale
+ *
+ * dynamic_delay_us / 65.28 = (64 + MallFrameCacheTmrDly) * 2^MallFrameCacheTmrScale
+ * (dynamic_delay_us / 65.28) / 2^MallFrameCacheTmrScale = 64 + MallFrameCacheTmrDly
+ * MallFrameCacheTmrDly = ((dynamic_delay_us / 65.28) / 2^MallFrameCacheTmrScale) - 64
+ * = (1000000 + 2 * stutter_period * refresh) * (100 + p) / (100 * refresh) / 65.28 / 2^MallFrameCacheTmrScale - 64
+ * = (1000000 + 2 * stutter_period * refresh) * (100 + p) / (refresh * 6528 * 2^MallFrameCacheTmrScale) - 64
*
* need to round up the result of the division before the subtraction
*/
- denom = refresh_hz * 6528;
- tmr_delay = div_u64((100000000LL + denom - 1), denom) - 64LL;
+ unsigned int denom = refresh_hz * 6528;
+ unsigned int stutter_period = dc->current_state->perf_params.stutter_period_us;
+
+ tmr_delay = (((1000000LL + 2 * stutter_period * refresh_hz) *
+ (100LL + dc->debug.mall_additional_timer_percent) + denom - 1) /
+ denom) - 64LL;
/* scale should be increased until it fits into 6 bits */
while (tmr_delay & ~0x3F) {
tmr_scale++;
if (tmr_scale > 3) {
- /* The delay exceeds the range of the hystersis timer */
+ /* Delay exceeds range of hysteresis timer */
ASSERT(false);
return false;
}
denom *= 2;
- tmr_delay = div_u64((100000000LL + denom - 1), denom) - 64LL;
+ tmr_delay = (((1000000LL + 2 * stutter_period * refresh_hz) *
+ (100LL + dc->debug.mall_additional_timer_percent) + denom - 1) /
+ denom) - 64LL;
+ }
+
+ /* Copy HW cursor */
+ if (cursor_cache_enable) {
+ memset(&cmd, 0, sizeof(cmd));
+ cmd.mall.header.type = DMUB_CMD__MALL;
+ cmd.mall.header.sub_type = DMUB_CMD__MALL_ACTION_COPY_CURSOR;
+ cmd.mall.header.payload_bytes =
+ sizeof(cmd.mall) - sizeof(cmd.mall.header);
+
+ switch (cursor_attr.color_format) {
+ case CURSOR_MODE_MONO:
+ cmd.mall.cursor_bpp = 2;
+ break;
+ case CURSOR_MODE_COLOR_1BIT_AND:
+ case CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA:
+ case CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA:
+ cmd.mall.cursor_bpp = 32;
+ break;
+
+ case CURSOR_MODE_COLOR_64BIT_FP_PRE_MULTIPLIED:
+ case CURSOR_MODE_COLOR_64BIT_FP_UN_PRE_MULTIPLIED:
+ cmd.mall.cursor_bpp = 64;
+ break;
+ }
+
+ cmd.mall.cursor_copy_src.quad_part = cursor_attr.address.quad_part;
+ cmd.mall.cursor_copy_dst.quad_part =
+ plane->address.grph.cursor_cache_addr.quad_part;
+ cmd.mall.cursor_width = cursor_attr.width;
+ cmd.mall.cursor_height = cursor_attr.height;
+ cmd.mall.cursor_pitch = cursor_attr.pitch;
+
+ dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd);
+ dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv);
+ dc_dmub_srv_wait_idle(dc->ctx->dmub_srv);
+
+ /* Use copied cursor, and it's okay to not switch back */
+ cursor_attr.address.quad_part =
+ plane->address.grph.cursor_cache_addr.quad_part;
+ dc_stream_set_cursor_attributes(stream, &cursor_attr);
}
/* Enable MALL */
memset(&cmd, 0, sizeof(cmd));
cmd.mall.header.type = DMUB_CMD__MALL;
- cmd.mall.header.sub_type =
- DMUB_CMD__MALL_ACTION_ALLOW;
- cmd.mall.header.payload_bytes =
- sizeof(cmd.mall) -
- sizeof(cmd.mall.header);
+ cmd.mall.header.sub_type = DMUB_CMD__MALL_ACTION_ALLOW;
+ cmd.mall.header.payload_bytes = sizeof(cmd.mall) - sizeof(cmd.mall.header);
cmd.mall.tmr_delay = tmr_delay;
cmd.mall.tmr_scale = tmr_scale;
+ cmd.mall.debug_bits = dc->debug.mall_error_as_fatal;
dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd);
dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv);
diff --git a/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c b/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c
index b96b32a37178..b4ff73e32279 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c
@@ -1316,7 +1316,9 @@ static bool dcn302_resource_construct(
dc->caps.max_cursor_size = 256;
dc->caps.min_horizontal_blanking_period = 80;
dc->caps.dmdata_alloc_size = 2048;
-
+ dc->caps.mall_size_per_mem_channel = 4;
+ /* total size = mall per channel * num channels * 1024 * 1024 */
+ dc->caps.mall_size_total = dc->caps.mall_size_per_mem_channel * dc->ctx->dc_bios->vram_info.num_chans * 1048576;
dc->caps.cursor_cache_size = dc->caps.max_cursor_size * dc->caps.max_cursor_size * 8;
dc->caps.max_slave_planes = 1;
dc->caps.post_blend_color_processing = true;
diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
index a50bdd6c7131..98dd8b5f463c 100644
--- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
+++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
@@ -458,6 +458,10 @@ struct dmub_rb_cmd_mall {
uint16_t cursor_pitch;
uint16_t cursor_height;
uint8_t cursor_bpp;
+ uint8_t debug_bits;
+
+ uint8_t reserved1;
+ uint8_t reserved2;
};
struct dmub_cmd_digx_encoder_control_data {
@@ -624,6 +628,7 @@ enum dmub_cmd_mall_type {
DMUB_CMD__MALL_ACTION_ALLOW = 0,
DMUB_CMD__MALL_ACTION_DISALLOW = 1,
DMUB_CMD__MALL_ACTION_COPY_CURSOR = 2,
+ DMUB_CMD__MALL_ACTION_NO_DF_REQ = 3,
};
struct dmub_cmd_psr_copy_settings_data {
--
2.25.1
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^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH 3/3] drm/amd/display: Update dcn30_apply_idle_power_optimizations() code
2021-01-19 20:38 ` [PATCH 3/3] drm/amd/display: Update dcn30_apply_idle_power_optimizations() code Bhawanpreet Lakha
@ 2021-01-19 22:10 ` Kazlauskas, Nicholas
0 siblings, 0 replies; 5+ messages in thread
From: Kazlauskas, Nicholas @ 2021-01-19 22:10 UTC (permalink / raw)
To: Bhawanpreet Lakha, alexander.deucher; +Cc: Joshua Aberback, amd-gfx
On 2021-01-19 3:38 p.m., Bhawanpreet Lakha wrote:
> Update the function for idle optimizations
> -remove hardcoded size
> -enable no memory-request case
> -add cursor copy
> -update mall eligibility check case
>
> Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
> Signed-off-by: Joshua Aberback <joshua.aberback@amd.com>
Series is:
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Though you might want to update patch 1's commit message to explain a
little more detail about watermark set D.
Regards,
Nicholas Kazlauskas
> ---
> drivers/gpu/drm/amd/display/dc/dc.h | 2 +
> .../drm/amd/display/dc/dcn30/dcn30_hwseq.c | 157 +++++++++++++-----
> .../amd/display/dc/dcn302/dcn302_resource.c | 4 +-
> .../gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 5 +
> 4 files changed, 129 insertions(+), 39 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
> index e21d4602e427..71d46ade24e5 100644
> --- a/drivers/gpu/drm/amd/display/dc/dc.h
> +++ b/drivers/gpu/drm/amd/display/dc/dc.h
> @@ -502,6 +502,8 @@ struct dc_debug_options {
> #if defined(CONFIG_DRM_AMD_DC_DCN)
> bool disable_idle_power_optimizations;
> unsigned int mall_size_override;
> + unsigned int mall_additional_timer_percent;
> + bool mall_error_as_fatal;
> #endif
> bool dmub_command_table; /* for testing only */
> struct dc_bw_validation_profile bw_val_profile;
> diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
> index 5c546b06f551..dff83c6a142a 100644
> --- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
> +++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
> @@ -710,8 +710,11 @@ void dcn30_program_dmdata_engine(struct pipe_ctx *pipe_ctx)
> bool dcn30_apply_idle_power_optimizations(struct dc *dc, bool enable)
> {
> union dmub_rb_cmd cmd;
> - unsigned int surface_size, refresh_hz, denom;
> uint32_t tmr_delay = 0, tmr_scale = 0;
> + struct dc_cursor_attributes cursor_attr;
> + bool cursor_cache_enable = false;
> + struct dc_stream_state *stream = NULL;
> + struct dc_plane_state *plane = NULL;
>
> if (!dc->ctx->dmub_srv)
> return false;
> @@ -722,72 +725,150 @@ bool dcn30_apply_idle_power_optimizations(struct dc *dc, bool enable)
>
> /* First, check no-memory-requests case */
> for (i = 0; i < dc->current_state->stream_count; i++) {
> - if (dc->current_state->stream_status[i]
> - .plane_count)
> + if (dc->current_state->stream_status[i].plane_count)
> /* Fail eligibility on a visible stream */
> break;
> }
>
> - if (dc->current_state->stream_count == 1 // single display only
> - && dc->current_state->stream_status[0].plane_count == 1 // single surface only
> - && dc->current_state->stream_status[0].plane_states[0]->address.page_table_base.quad_part == 0 // no VM
> - // Only 8 and 16 bit formats
> - && dc->current_state->stream_status[0].plane_states[0]->format <= SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F
> - && dc->current_state->stream_status[0].plane_states[0]->format >= SURFACE_PIXEL_FORMAT_GRPH_ARGB8888) {
> - surface_size = dc->current_state->stream_status[0].plane_states[0]->plane_size.surface_pitch *
> - dc->current_state->stream_status[0].plane_states[0]->plane_size.surface_size.height *
> - (dc->current_state->stream_status[0].plane_states[0]->format >= SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616 ?
> - 8 : 4);
> - } else {
> - // TODO: remove hard code size
> - surface_size = 128 * 1024 * 1024;
> + if (i == dc->current_state->stream_count) {
> + /* Enable no-memory-requests case */
> + memset(&cmd, 0, sizeof(cmd));
> + cmd.mall.header.type = DMUB_CMD__MALL;
> + cmd.mall.header.sub_type = DMUB_CMD__MALL_ACTION_NO_DF_REQ;
> + cmd.mall.header.payload_bytes = sizeof(cmd.mall) - sizeof(cmd.mall.header);
> +
> + dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd);
> + dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv);
> +
> + return true;
> }
>
> - // TODO: remove hard code size
> - if (surface_size < 128 * 1024 * 1024) {
> - refresh_hz = div_u64((unsigned long long) dc->current_state->streams[0]->timing.pix_clk_100hz *
> - 100LL,
> - (dc->current_state->streams[0]->timing.v_total *
> - dc->current_state->streams[0]->timing.h_total));
> + stream = dc->current_state->streams[0];
> + plane = (stream ? dc->current_state->stream_status[0].plane_states[0] : NULL);
> +
> + if (stream && plane) {
> + cursor_cache_enable = stream->cursor_position.enable &&
> + plane->address.grph.cursor_cache_addr.quad_part;
> + cursor_attr = stream->cursor_attributes;
> + }
> +
> + /*
> + * Second, check MALL eligibility
> + *
> + * single display only, single surface only, 8 and 16 bit formats only, no VM,
> + * do not use MALL for displays that support PSR as they use D0i3.2 in DMCUB FW
> + *
> + * TODO: When we implement multi-display, PSR displays will be allowed if there is
> + * a non-PSR display present, since in that case we can't do D0i3.2
> + */
> + if (dc->current_state->stream_count == 1 &&
> + stream->link->psr_settings.psr_version == DC_PSR_VERSION_UNSUPPORTED &&
> + dc->current_state->stream_status[0].plane_count == 1 &&
> + plane->format <= SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F &&
> + plane->format >= SURFACE_PIXEL_FORMAT_GRPH_ARGB8888 &&
> + plane->address.page_table_base.quad_part == 0 &&
> + dc->hwss.does_plane_fit_in_mall &&
> + dc->hwss.does_plane_fit_in_mall(dc, plane,
> + cursor_cache_enable ? &cursor_attr : NULL)) {
> + unsigned int v_total = stream->adjust.v_total_max ?
> + stream->adjust.v_total_max : stream->timing.v_total;
> + unsigned int refresh_hz = (unsigned long long) stream->timing.pix_clk_100hz *
> + 100LL / (v_total * stream->timing.h_total);
>
> /*
> - * Delay_Us = 65.28 * (64 + MallFrameCacheTmrDly) * 2^MallFrameCacheTmrScale
> - * Delay_Us / 65.28 = (64 + MallFrameCacheTmrDly) * 2^MallFrameCacheTmrScale
> - * (Delay_Us / 65.28) / 2^MallFrameCacheTmrScale = 64 + MallFrameCacheTmrDly
> - * MallFrameCacheTmrDly = ((Delay_Us / 65.28) / 2^MallFrameCacheTmrScale) - 64
> - * = (1000000 / refresh) / 65.28 / 2^MallFrameCacheTmrScale - 64
> - * = 1000000 / (refresh * 65.28 * 2^MallFrameCacheTmrScale) - 64
> - * = (1000000 * 100) / (refresh * 6528 * 2^MallFrameCacheTmrScale) - 64
> + * one frame time in microsec:
> + * Delay_Us = 1000000 / refresh
> + * dynamic_delay_us = 1000000 / refresh + 2 * stutter_period
> + *
> + * one frame time modified by 'additional timer percent' (p):
> + * Delay_Us_modified = dynamic_delay_us + dynamic_delay_us * p / 100
> + * = dynamic_delay_us * (1 + p / 100)
> + * = (1000000 / refresh + 2 * stutter_period) * (100 + p) / 100
> + * = (1000000 + 2 * stutter_period * refresh) * (100 + p) / (100 * refresh)
> + *
> + * formula for timer duration based on parameters, from regspec:
> + * dynamic_delay_us = 65.28 * (64 + MallFrameCacheTmrDly) * 2^MallFrameCacheTmrScale
> + *
> + * dynamic_delay_us / 65.28 = (64 + MallFrameCacheTmrDly) * 2^MallFrameCacheTmrScale
> + * (dynamic_delay_us / 65.28) / 2^MallFrameCacheTmrScale = 64 + MallFrameCacheTmrDly
> + * MallFrameCacheTmrDly = ((dynamic_delay_us / 65.28) / 2^MallFrameCacheTmrScale) - 64
> + * = (1000000 + 2 * stutter_period * refresh) * (100 + p) / (100 * refresh) / 65.28 / 2^MallFrameCacheTmrScale - 64
> + * = (1000000 + 2 * stutter_period * refresh) * (100 + p) / (refresh * 6528 * 2^MallFrameCacheTmrScale) - 64
> *
> * need to round up the result of the division before the subtraction
> */
> - denom = refresh_hz * 6528;
> - tmr_delay = div_u64((100000000LL + denom - 1), denom) - 64LL;
> + unsigned int denom = refresh_hz * 6528;
> + unsigned int stutter_period = dc->current_state->perf_params.stutter_period_us;
> +
> + tmr_delay = (((1000000LL + 2 * stutter_period * refresh_hz) *
> + (100LL + dc->debug.mall_additional_timer_percent) + denom - 1) /
> + denom) - 64LL;
>
> /* scale should be increased until it fits into 6 bits */
> while (tmr_delay & ~0x3F) {
> tmr_scale++;
>
> if (tmr_scale > 3) {
> - /* The delay exceeds the range of the hystersis timer */
> + /* Delay exceeds range of hysteresis timer */
> ASSERT(false);
> return false;
> }
>
> denom *= 2;
> - tmr_delay = div_u64((100000000LL + denom - 1), denom) - 64LL;
> + tmr_delay = (((1000000LL + 2 * stutter_period * refresh_hz) *
> + (100LL + dc->debug.mall_additional_timer_percent) + denom - 1) /
> + denom) - 64LL;
> + }
> +
> + /* Copy HW cursor */
> + if (cursor_cache_enable) {
> + memset(&cmd, 0, sizeof(cmd));
> + cmd.mall.header.type = DMUB_CMD__MALL;
> + cmd.mall.header.sub_type = DMUB_CMD__MALL_ACTION_COPY_CURSOR;
> + cmd.mall.header.payload_bytes =
> + sizeof(cmd.mall) - sizeof(cmd.mall.header);
> +
> + switch (cursor_attr.color_format) {
> + case CURSOR_MODE_MONO:
> + cmd.mall.cursor_bpp = 2;
> + break;
> + case CURSOR_MODE_COLOR_1BIT_AND:
> + case CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA:
> + case CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA:
> + cmd.mall.cursor_bpp = 32;
> + break;
> +
> + case CURSOR_MODE_COLOR_64BIT_FP_PRE_MULTIPLIED:
> + case CURSOR_MODE_COLOR_64BIT_FP_UN_PRE_MULTIPLIED:
> + cmd.mall.cursor_bpp = 64;
> + break;
> + }
> +
> + cmd.mall.cursor_copy_src.quad_part = cursor_attr.address.quad_part;
> + cmd.mall.cursor_copy_dst.quad_part =
> + plane->address.grph.cursor_cache_addr.quad_part;
> + cmd.mall.cursor_width = cursor_attr.width;
> + cmd.mall.cursor_height = cursor_attr.height;
> + cmd.mall.cursor_pitch = cursor_attr.pitch;
> +
> + dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd);
> + dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv);
> + dc_dmub_srv_wait_idle(dc->ctx->dmub_srv);
> +
> + /* Use copied cursor, and it's okay to not switch back */
> + cursor_attr.address.quad_part =
> + plane->address.grph.cursor_cache_addr.quad_part;
> + dc_stream_set_cursor_attributes(stream, &cursor_attr);
> }
>
> /* Enable MALL */
> memset(&cmd, 0, sizeof(cmd));
> cmd.mall.header.type = DMUB_CMD__MALL;
> - cmd.mall.header.sub_type =
> - DMUB_CMD__MALL_ACTION_ALLOW;
> - cmd.mall.header.payload_bytes =
> - sizeof(cmd.mall) -
> - sizeof(cmd.mall.header);
> + cmd.mall.header.sub_type = DMUB_CMD__MALL_ACTION_ALLOW;
> + cmd.mall.header.payload_bytes = sizeof(cmd.mall) - sizeof(cmd.mall.header);
> cmd.mall.tmr_delay = tmr_delay;
> cmd.mall.tmr_scale = tmr_scale;
> + cmd.mall.debug_bits = dc->debug.mall_error_as_fatal;
>
> dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd);
> dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv);
> diff --git a/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c b/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c
> index b96b32a37178..b4ff73e32279 100644
> --- a/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c
> +++ b/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c
> @@ -1316,7 +1316,9 @@ static bool dcn302_resource_construct(
> dc->caps.max_cursor_size = 256;
> dc->caps.min_horizontal_blanking_period = 80;
> dc->caps.dmdata_alloc_size = 2048;
> -
> + dc->caps.mall_size_per_mem_channel = 4;
> + /* total size = mall per channel * num channels * 1024 * 1024 */
> + dc->caps.mall_size_total = dc->caps.mall_size_per_mem_channel * dc->ctx->dc_bios->vram_info.num_chans * 1048576;
> dc->caps.cursor_cache_size = dc->caps.max_cursor_size * dc->caps.max_cursor_size * 8;
> dc->caps.max_slave_planes = 1;
> dc->caps.post_blend_color_processing = true;
> diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
> index a50bdd6c7131..98dd8b5f463c 100644
> --- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
> +++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
> @@ -458,6 +458,10 @@ struct dmub_rb_cmd_mall {
> uint16_t cursor_pitch;
> uint16_t cursor_height;
> uint8_t cursor_bpp;
> + uint8_t debug_bits;
> +
> + uint8_t reserved1;
> + uint8_t reserved2;
> };
>
> struct dmub_cmd_digx_encoder_control_data {
> @@ -624,6 +628,7 @@ enum dmub_cmd_mall_type {
> DMUB_CMD__MALL_ACTION_ALLOW = 0,
> DMUB_CMD__MALL_ACTION_DISALLOW = 1,
> DMUB_CMD__MALL_ACTION_COPY_CURSOR = 2,
> + DMUB_CMD__MALL_ACTION_NO_DF_REQ = 3,
> };
>
> struct dmub_cmd_psr_copy_settings_data {
>
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^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2021-01-19 22:10 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2021-01-19 20:38 [PATCH 0/3] idle optimization patches (mall) Bhawanpreet Lakha
2021-01-19 20:38 ` [PATCH 1/3] drm/amd/display: Enable programing of MALL watermarks Bhawanpreet Lakha
2021-01-19 20:38 ` [PATCH 2/3] drm/amd/display: Dynamic cursor cache size for MALL eligibility check Bhawanpreet Lakha
2021-01-19 20:38 ` [PATCH 3/3] drm/amd/display: Update dcn30_apply_idle_power_optimizations() code Bhawanpreet Lakha
2021-01-19 22:10 ` Kazlauskas, Nicholas
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