* [PATCH] drm/amdgpu: fix MES HQD masks @ 2024-04-05 14:36 Shashank Sharma 2024-04-05 15:26 ` Joshi, Mukul 0 siblings, 1 reply; 5+ messages in thread From: Shashank Sharma @ 2024-04-05 14:36 UTC (permalink / raw) To: amd-gfx; +Cc: Shashank Sharma, Christian König, Alex Deucher, Arvind Yadav This patch fixes the existing HQD masks prepared during the MES initialization. These existing masks values were causing problems when we try to enable GFX oversubscription. Cc: Christian König <Christian.Koenig@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Shashank Sharma <shashank.sharma@amd.com> Signed-off-by: Arvind Yadav <arvind.yadav@amd.com> --- drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c | 3 --- drivers/gpu/drm/amd/amdgpu/mes_v10_1.c | 15 ++++++++++++++- drivers/gpu/drm/amd/amdgpu/mes_v11_0.c | 15 ++++++++++++++- 3 files changed, 28 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c index da48b6da0107..7db80ffda33f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c @@ -148,9 +148,6 @@ int amdgpu_mes_init(struct amdgpu_device *adev) adev->mes.compute_hqd_mask[i] = 0xc; } - for (i = 0; i < AMDGPU_MES_MAX_GFX_PIPES; i++) - adev->mes.gfx_hqd_mask[i] = i ? 0 : 0xfffffffe; - for (i = 0; i < AMDGPU_MES_MAX_SDMA_PIPES; i++) { if (amdgpu_ip_version(adev, SDMA0_HWIP, 0) < IP_VERSION(6, 0, 0)) diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c b/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c index 1e5ad1e08d2a..9217914f824d 100644 --- a/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c +++ b/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c @@ -266,6 +266,19 @@ static int mes_v10_1_query_sched_status(struct amdgpu_mes *mes) offsetof(union MESAPI__QUERY_MES_STATUS, api_status)); } +static inline uint32_t mes_v10_get_gfx_hqd_mask(int pipe_index) +{ + /* Pipe 1 can't be used for MES due to HW limitation */ + if (pipe_index == 1) + return 0; + + /* + * GFX V10 supports 2 queues, but we want to keep queue 0 + * reserved for kernel, so enable only queue 1 (1<<1) for MES. + */ + return 0x2; +} + static int mes_v10_1_set_hw_resources(struct amdgpu_mes *mes) { int i; @@ -291,7 +304,7 @@ static int mes_v10_1_set_hw_resources(struct amdgpu_mes *mes) mes->compute_hqd_mask[i]; for (i = 0; i < MAX_GFX_PIPES; i++) - mes_set_hw_res_pkt.gfx_hqd_mask[i] = mes->gfx_hqd_mask[i]; + mes_set_hw_res_pkt.gfx_hqd_mask[i] = mes_v10_get_gfx_hqd_mask(i); for (i = 0; i < MAX_SDMA_PIPES; i++) mes_set_hw_res_pkt.sdma_hqd_mask[i] = mes->sdma_hqd_mask[i]; diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c index 26d71a22395d..b7dcd936afc8 100644 --- a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c @@ -360,6 +360,19 @@ static int mes_v11_0_misc_op(struct amdgpu_mes *mes, offsetof(union MESAPI__MISC, api_status)); } +static inline uint32_t mes_v11_get_gfx_hqd_mask(int pipe_index) +{ + /* Pipe 1 can't be used for MES due to HW limitation */ + if (pipe_index == 1) + return 0; + + /* + * GFX V10 supports 2 queues, but we want to keep queue 0 + * reserved for kernel, so enable only queue 1 (1<<1) for MES. + */ + return 0x2; +} + static int mes_v11_0_set_hw_resources(struct amdgpu_mes *mes) { int i; @@ -385,7 +398,7 @@ static int mes_v11_0_set_hw_resources(struct amdgpu_mes *mes) mes->compute_hqd_mask[i]; for (i = 0; i < MAX_GFX_PIPES; i++) - mes_set_hw_res_pkt.gfx_hqd_mask[i] = mes->gfx_hqd_mask[i]; + mes_set_hw_res_pkt.gfx_hqd_mask[i] = mes_v11_get_gfx_hqd_mask(i); for (i = 0; i < MAX_SDMA_PIPES; i++) mes_set_hw_res_pkt.sdma_hqd_mask[i] = mes->sdma_hqd_mask[i]; -- 2.43.2 ^ permalink raw reply related [flat|nested] 5+ messages in thread
* RE: [PATCH] drm/amdgpu: fix MES HQD masks 2024-04-05 14:36 [PATCH] drm/amdgpu: fix MES HQD masks Shashank Sharma @ 2024-04-05 15:26 ` Joshi, Mukul 2024-04-05 15:37 ` Sharma, Shashank 0 siblings, 1 reply; 5+ messages in thread From: Joshi, Mukul @ 2024-04-05 15:26 UTC (permalink / raw) To: Sharma, Shashank, amd-gfx@lists.freedesktop.org Cc: Sharma, Shashank, Koenig, Christian, Deucher, Alexander, Yadav, Arvind [AMD Official Use Only - General] > -----Original Message----- > From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of > Shashank Sharma > Sent: Friday, April 5, 2024 10:36 AM > To: amd-gfx@lists.freedesktop.org > Cc: Sharma, Shashank <Shashank.Sharma@amd.com>; Koenig, Christian > <Christian.Koenig@amd.com>; Deucher, Alexander > <Alexander.Deucher@amd.com>; Yadav, Arvind <Arvind.Yadav@amd.com> > Subject: [PATCH] drm/amdgpu: fix MES HQD masks > > Caution: This message originated from an External Source. Use proper caution > when opening attachments, clicking links, or responding. > > > This patch fixes the existing HQD masks prepared during the MES initialization. > These existing masks values were causing problems when we try to enable GFX > oversubscription. > > Cc: Christian König <Christian.Koenig@amd.com> > Cc: Alex Deucher <alexander.deucher@amd.com> > Signed-off-by: Shashank Sharma <shashank.sharma@amd.com> > Signed-off-by: Arvind Yadav <arvind.yadav@amd.com> > --- > drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c | 3 --- > drivers/gpu/drm/amd/amdgpu/mes_v10_1.c | 15 ++++++++++++++- > drivers/gpu/drm/amd/amdgpu/mes_v11_0.c | 15 ++++++++++++++- > 3 files changed, 28 insertions(+), 5 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c > b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c > index da48b6da0107..7db80ffda33f 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c > @@ -148,9 +148,6 @@ int amdgpu_mes_init(struct amdgpu_device *adev) > adev->mes.compute_hqd_mask[i] = 0xc; > } > > - for (i = 0; i < AMDGPU_MES_MAX_GFX_PIPES; i++) > - adev->mes.gfx_hqd_mask[i] = i ? 0 : 0xfffffffe; > - > for (i = 0; i < AMDGPU_MES_MAX_SDMA_PIPES; i++) { > if (amdgpu_ip_version(adev, SDMA0_HWIP, 0) < > IP_VERSION(6, 0, 0)) diff --git > a/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c > b/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c > index 1e5ad1e08d2a..9217914f824d 100644 > --- a/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c > +++ b/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c > @@ -266,6 +266,19 @@ static int mes_v10_1_query_sched_status(struct > amdgpu_mes *mes) > offsetof(union MESAPI__QUERY_MES_STATUS, api_status)); } > > +static inline uint32_t mes_v10_get_gfx_hqd_mask(int pipe_index) { > + /* Pipe 1 can't be used for MES due to HW limitation */ > + if (pipe_index == 1) > + return 0; > + > + /* > + * GFX V10 supports 2 queues, but we want to keep queue 0 > + * reserved for kernel, so enable only queue 1 (1<<1) for MES. > + */ > + return 0x2; > +} > + > static int mes_v10_1_set_hw_resources(struct amdgpu_mes *mes) { > int i; > @@ -291,7 +304,7 @@ static int mes_v10_1_set_hw_resources(struct > amdgpu_mes *mes) > mes->compute_hqd_mask[i]; > > for (i = 0; i < MAX_GFX_PIPES; i++) > - mes_set_hw_res_pkt.gfx_hqd_mask[i] = mes->gfx_hqd_mask[i]; > + mes_set_hw_res_pkt.gfx_hqd_mask[i] = > + mes_v10_get_gfx_hqd_mask(i); > > for (i = 0; i < MAX_SDMA_PIPES; i++) > mes_set_hw_res_pkt.sdma_hqd_mask[i] = mes->sdma_hqd_mask[i]; > diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c > b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c > index 26d71a22395d..b7dcd936afc8 100644 > --- a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c > @@ -360,6 +360,19 @@ static int mes_v11_0_misc_op(struct amdgpu_mes > *mes, > offsetof(union MESAPI__MISC, api_status)); } > > +static inline uint32_t mes_v11_get_gfx_hqd_mask(int pipe_index) { > + /* Pipe 1 can't be used for MES due to HW limitation */ > + if (pipe_index == 1) > + return 0; > + > + /* > + * GFX V10 supports 2 queues, but we want to keep queue 0 > + * reserved for kernel, so enable only queue 1 (1<<1) for MES. > + */ > + return 0x2; > +} There is no difference between this function and the corresponding function written for GFX10. Why not make this a common function instead? Regards, Mukul > + > static int mes_v11_0_set_hw_resources(struct amdgpu_mes *mes) { > int i; > @@ -385,7 +398,7 @@ static int mes_v11_0_set_hw_resources(struct > amdgpu_mes *mes) > mes->compute_hqd_mask[i]; > > for (i = 0; i < MAX_GFX_PIPES; i++) > - mes_set_hw_res_pkt.gfx_hqd_mask[i] = mes->gfx_hqd_mask[i]; > + mes_set_hw_res_pkt.gfx_hqd_mask[i] = > + mes_v11_get_gfx_hqd_mask(i); > > for (i = 0; i < MAX_SDMA_PIPES; i++) > mes_set_hw_res_pkt.sdma_hqd_mask[i] = mes->sdma_hqd_mask[i]; > -- > 2.43.2 ^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH] drm/amdgpu: fix MES HQD masks 2024-04-05 15:26 ` Joshi, Mukul @ 2024-04-05 15:37 ` Sharma, Shashank 2024-04-05 16:39 ` Joshi, Mukul 0 siblings, 1 reply; 5+ messages in thread From: Sharma, Shashank @ 2024-04-05 15:37 UTC (permalink / raw) To: Joshi, Mukul, amd-gfx@lists.freedesktop.org Cc: Koenig, Christian, Deucher, Alexander, Yadav, Arvind On 05/04/2024 17:26, Joshi, Mukul wrote: > [AMD Official Use Only - General] > >> -----Original Message----- >> From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of >> Shashank Sharma >> Sent: Friday, April 5, 2024 10:36 AM >> To: amd-gfx@lists.freedesktop.org >> Cc: Sharma, Shashank <Shashank.Sharma@amd.com>; Koenig, Christian >> <Christian.Koenig@amd.com>; Deucher, Alexander >> <Alexander.Deucher@amd.com>; Yadav, Arvind <Arvind.Yadav@amd.com> >> Subject: [PATCH] drm/amdgpu: fix MES HQD masks >> >> Caution: This message originated from an External Source. Use proper caution >> when opening attachments, clicking links, or responding. >> >> >> This patch fixes the existing HQD masks prepared during the MES initialization. >> These existing masks values were causing problems when we try to enable GFX >> oversubscription. >> >> Cc: Christian König <Christian.Koenig@amd.com> >> Cc: Alex Deucher <alexander.deucher@amd.com> >> Signed-off-by: Shashank Sharma <shashank.sharma@amd.com> >> Signed-off-by: Arvind Yadav <arvind.yadav@amd.com> >> --- >> drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c | 3 --- >> drivers/gpu/drm/amd/amdgpu/mes_v10_1.c | 15 ++++++++++++++- >> drivers/gpu/drm/amd/amdgpu/mes_v11_0.c | 15 ++++++++++++++- >> 3 files changed, 28 insertions(+), 5 deletions(-) >> >> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c >> b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c >> index da48b6da0107..7db80ffda33f 100644 >> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c >> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c >> @@ -148,9 +148,6 @@ int amdgpu_mes_init(struct amdgpu_device *adev) >> adev->mes.compute_hqd_mask[i] = 0xc; >> } >> >> - for (i = 0; i < AMDGPU_MES_MAX_GFX_PIPES; i++) >> - adev->mes.gfx_hqd_mask[i] = i ? 0 : 0xfffffffe; >> - >> for (i = 0; i < AMDGPU_MES_MAX_SDMA_PIPES; i++) { >> if (amdgpu_ip_version(adev, SDMA0_HWIP, 0) < >> IP_VERSION(6, 0, 0)) diff --git >> a/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c >> b/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c >> index 1e5ad1e08d2a..9217914f824d 100644 >> --- a/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c >> +++ b/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c >> @@ -266,6 +266,19 @@ static int mes_v10_1_query_sched_status(struct >> amdgpu_mes *mes) >> offsetof(union MESAPI__QUERY_MES_STATUS, api_status)); } >> >> +static inline uint32_t mes_v10_get_gfx_hqd_mask(int pipe_index) { >> + /* Pipe 1 can't be used for MES due to HW limitation */ >> + if (pipe_index == 1) >> + return 0; >> + >> + /* >> + * GFX V10 supports 2 queues, but we want to keep queue 0 >> + * reserved for kernel, so enable only queue 1 (1<<1) for MES. >> + */ >> + return 0x2; >> +} >> + >> static int mes_v10_1_set_hw_resources(struct amdgpu_mes *mes) { >> int i; >> @@ -291,7 +304,7 @@ static int mes_v10_1_set_hw_resources(struct >> amdgpu_mes *mes) >> mes->compute_hqd_mask[i]; >> >> for (i = 0; i < MAX_GFX_PIPES; i++) >> - mes_set_hw_res_pkt.gfx_hqd_mask[i] = mes->gfx_hqd_mask[i]; >> + mes_set_hw_res_pkt.gfx_hqd_mask[i] = >> + mes_v10_get_gfx_hqd_mask(i); >> >> for (i = 0; i < MAX_SDMA_PIPES; i++) >> mes_set_hw_res_pkt.sdma_hqd_mask[i] = mes->sdma_hqd_mask[i]; >> diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c >> b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c >> index 26d71a22395d..b7dcd936afc8 100644 >> --- a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c >> +++ b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c >> @@ -360,6 +360,19 @@ static int mes_v11_0_misc_op(struct amdgpu_mes >> *mes, >> offsetof(union MESAPI__MISC, api_status)); } >> >> +static inline uint32_t mes_v11_get_gfx_hqd_mask(int pipe_index) { >> + /* Pipe 1 can't be used for MES due to HW limitation */ >> + if (pipe_index == 1) >> + return 0; >> + >> + /* >> + * GFX V10 supports 2 queues, but we want to keep queue 0 >> + * reserved for kernel, so enable only queue 1 (1<<1) for MES. >> + */ >> + return 0x2; >> +} > There is no difference between this function and the corresponding function written for GFX10. > Why not make this a common function instead? This is deliberate, to indicate that the HQD mask can be different for each GFX IP version, so as the number of pipes and queue per pipe. Also the limitation on pipe 1 will not be there for future versions. - Shashank > Regards, > Mukul > >> + >> static int mes_v11_0_set_hw_resources(struct amdgpu_mes *mes) { >> int i; >> @@ -385,7 +398,7 @@ static int mes_v11_0_set_hw_resources(struct >> amdgpu_mes *mes) >> mes->compute_hqd_mask[i]; >> >> for (i = 0; i < MAX_GFX_PIPES; i++) >> - mes_set_hw_res_pkt.gfx_hqd_mask[i] = mes->gfx_hqd_mask[i]; >> + mes_set_hw_res_pkt.gfx_hqd_mask[i] = >> + mes_v11_get_gfx_hqd_mask(i); >> >> for (i = 0; i < MAX_SDMA_PIPES; i++) >> mes_set_hw_res_pkt.sdma_hqd_mask[i] = mes->sdma_hqd_mask[i]; >> -- >> 2.43.2 ^ permalink raw reply [flat|nested] 5+ messages in thread
* RE: [PATCH] drm/amdgpu: fix MES HQD masks 2024-04-05 15:37 ` Sharma, Shashank @ 2024-04-05 16:39 ` Joshi, Mukul 2024-04-05 17:34 ` Sharma, Shashank 0 siblings, 1 reply; 5+ messages in thread From: Joshi, Mukul @ 2024-04-05 16:39 UTC (permalink / raw) To: Sharma, Shashank, amd-gfx@lists.freedesktop.org Cc: Koenig, Christian, Deucher, Alexander, Yadav, Arvind [AMD Official Use Only - General] > -----Original Message----- > From: Sharma, Shashank <Shashank.Sharma@amd.com> > Sent: Friday, April 5, 2024 11:37 AM > To: Joshi, Mukul <Mukul.Joshi@amd.com>; amd-gfx@lists.freedesktop.org > Cc: Koenig, Christian <Christian.Koenig@amd.com>; Deucher, Alexander > <Alexander.Deucher@amd.com>; Yadav, Arvind <Arvind.Yadav@amd.com> > Subject: Re: [PATCH] drm/amdgpu: fix MES HQD masks > > > On 05/04/2024 17:26, Joshi, Mukul wrote: > > [AMD Official Use Only - General] > > > >> -----Original Message----- > >> From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of > >> Shashank Sharma > >> Sent: Friday, April 5, 2024 10:36 AM > >> To: amd-gfx@lists.freedesktop.org > >> Cc: Sharma, Shashank <Shashank.Sharma@amd.com>; Koenig, Christian > >> <Christian.Koenig@amd.com>; Deucher, Alexander > >> <Alexander.Deucher@amd.com>; Yadav, Arvind <Arvind.Yadav@amd.com> > >> Subject: [PATCH] drm/amdgpu: fix MES HQD masks > >> > >> Caution: This message originated from an External Source. Use proper > >> caution when opening attachments, clicking links, or responding. > >> > >> > >> This patch fixes the existing HQD masks prepared during the MES > initialization. > >> These existing masks values were causing problems when we try to > >> enable GFX oversubscription. > >> > >> Cc: Christian König <Christian.Koenig@amd.com> > >> Cc: Alex Deucher <alexander.deucher@amd.com> > >> Signed-off-by: Shashank Sharma <shashank.sharma@amd.com> > >> Signed-off-by: Arvind Yadav <arvind.yadav@amd.com> > >> --- > >> drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c | 3 --- > >> drivers/gpu/drm/amd/amdgpu/mes_v10_1.c | 15 ++++++++++++++- > >> drivers/gpu/drm/amd/amdgpu/mes_v11_0.c | 15 ++++++++++++++- > >> 3 files changed, 28 insertions(+), 5 deletions(-) > >> > >> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c > >> b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c > >> index da48b6da0107..7db80ffda33f 100644 > >> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c > >> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c > >> @@ -148,9 +148,6 @@ int amdgpu_mes_init(struct amdgpu_device > *adev) > >> adev->mes.compute_hqd_mask[i] = 0xc; > >> } > >> > >> - for (i = 0; i < AMDGPU_MES_MAX_GFX_PIPES; i++) > >> - adev->mes.gfx_hqd_mask[i] = i ? 0 : 0xfffffffe; > >> - > >> for (i = 0; i < AMDGPU_MES_MAX_SDMA_PIPES; i++) { > >> if (amdgpu_ip_version(adev, SDMA0_HWIP, 0) < > >> IP_VERSION(6, 0, 0)) diff --git > >> a/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c > >> b/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c > >> index 1e5ad1e08d2a..9217914f824d 100644 > >> --- a/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c > >> +++ b/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c > >> @@ -266,6 +266,19 @@ static int mes_v10_1_query_sched_status(struct > >> amdgpu_mes *mes) > >> offsetof(union MESAPI__QUERY_MES_STATUS, > >> api_status)); } > >> > >> +static inline uint32_t mes_v10_get_gfx_hqd_mask(int pipe_index) { > >> + /* Pipe 1 can't be used for MES due to HW limitation */ > >> + if (pipe_index == 1) > >> + return 0; > >> + > >> + /* > >> + * GFX V10 supports 2 queues, but we want to keep queue 0 > >> + * reserved for kernel, so enable only queue 1 (1<<1) for MES. > >> + */ > >> + return 0x2; > >> +} > >> + > >> static int mes_v10_1_set_hw_resources(struct amdgpu_mes *mes) { > >> int i; > >> @@ -291,7 +304,7 @@ static int mes_v10_1_set_hw_resources(struct > >> amdgpu_mes *mes) > >> mes->compute_hqd_mask[i]; > >> > >> for (i = 0; i < MAX_GFX_PIPES; i++) > >> - mes_set_hw_res_pkt.gfx_hqd_mask[i] = mes->gfx_hqd_mask[i]; > >> + mes_set_hw_res_pkt.gfx_hqd_mask[i] = > >> + mes_v10_get_gfx_hqd_mask(i); > >> > >> for (i = 0; i < MAX_SDMA_PIPES; i++) > >> mes_set_hw_res_pkt.sdma_hqd_mask[i] = > >> mes->sdma_hqd_mask[i]; diff --git > >> a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c > >> b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c > >> index 26d71a22395d..b7dcd936afc8 100644 > >> --- a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c > >> +++ b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c > >> @@ -360,6 +360,19 @@ static int mes_v11_0_misc_op(struct > amdgpu_mes > >> *mes, > >> offsetof(union MESAPI__MISC, api_status)); > >> } > >> > >> +static inline uint32_t mes_v11_get_gfx_hqd_mask(int pipe_index) { > >> + /* Pipe 1 can't be used for MES due to HW limitation */ > >> + if (pipe_index == 1) > >> + return 0; > >> + > >> + /* > >> + * GFX V10 supports 2 queues, but we want to keep queue 0 > >> + * reserved for kernel, so enable only queue 1 (1<<1) for MES. > >> + */ > >> + return 0x2; > >> +} > > There is no difference between this function and the corresponding function > written for GFX10. > > Why not make this a common function instead? > > This is deliberate, to indicate that the HQD mask can be different for each GFX > IP version, so as the number of pipes and queue per pipe. Also the limitation > on pipe 1 will not be there for future versions. > But for now this is common for both GFX10 and GFX11. When we have a case where this changes in future, we can implement a new function specific for that GFX IP version. For now, this should be a common function. Regards, Mukul > - Shashank > > > Regards, > > Mukul > > > >> + > >> static int mes_v11_0_set_hw_resources(struct amdgpu_mes *mes) { > >> int i; > >> @@ -385,7 +398,7 @@ static int mes_v11_0_set_hw_resources(struct > >> amdgpu_mes *mes) > >> mes->compute_hqd_mask[i]; > >> > >> for (i = 0; i < MAX_GFX_PIPES; i++) > >> - mes_set_hw_res_pkt.gfx_hqd_mask[i] = mes->gfx_hqd_mask[i]; > >> + mes_set_hw_res_pkt.gfx_hqd_mask[i] = > >> + mes_v11_get_gfx_hqd_mask(i); > >> > >> for (i = 0; i < MAX_SDMA_PIPES; i++) > >> mes_set_hw_res_pkt.sdma_hqd_mask[i] = > >> mes->sdma_hqd_mask[i]; > >> -- > >> 2.43.2 ^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH] drm/amdgpu: fix MES HQD masks 2024-04-05 16:39 ` Joshi, Mukul @ 2024-04-05 17:34 ` Sharma, Shashank 0 siblings, 0 replies; 5+ messages in thread From: Sharma, Shashank @ 2024-04-05 17:34 UTC (permalink / raw) To: Joshi, Mukul, amd-gfx@lists.freedesktop.org Cc: Koenig, Christian, Deucher, Alexander, Yadav, Arvind On 05/04/2024 18:39, Joshi, Mukul wrote: > [AMD Official Use Only - General] > >> -----Original Message----- >> From: Sharma, Shashank <Shashank.Sharma@amd.com> >> Sent: Friday, April 5, 2024 11:37 AM >> To: Joshi, Mukul <Mukul.Joshi@amd.com>; amd-gfx@lists.freedesktop.org >> Cc: Koenig, Christian <Christian.Koenig@amd.com>; Deucher, Alexander >> <Alexander.Deucher@amd.com>; Yadav, Arvind <Arvind.Yadav@amd.com> >> Subject: Re: [PATCH] drm/amdgpu: fix MES HQD masks >> >> >> On 05/04/2024 17:26, Joshi, Mukul wrote: >>> [AMD Official Use Only - General] >>> >>>> -----Original Message----- >>>> From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of >>>> Shashank Sharma >>>> Sent: Friday, April 5, 2024 10:36 AM >>>> To: amd-gfx@lists.freedesktop.org >>>> Cc: Sharma, Shashank <Shashank.Sharma@amd.com>; Koenig, Christian >>>> <Christian.Koenig@amd.com>; Deucher, Alexander >>>> <Alexander.Deucher@amd.com>; Yadav, Arvind <Arvind.Yadav@amd.com> >>>> Subject: [PATCH] drm/amdgpu: fix MES HQD masks >>>> >>>> Caution: This message originated from an External Source. Use proper >>>> caution when opening attachments, clicking links, or responding. >>>> >>>> >>>> This patch fixes the existing HQD masks prepared during the MES >> initialization. >>>> These existing masks values were causing problems when we try to >>>> enable GFX oversubscription. >>>> >>>> Cc: Christian König <Christian.Koenig@amd.com> >>>> Cc: Alex Deucher <alexander.deucher@amd.com> >>>> Signed-off-by: Shashank Sharma <shashank.sharma@amd.com> >>>> Signed-off-by: Arvind Yadav <arvind.yadav@amd.com> >>>> --- >>>> drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c | 3 --- >>>> drivers/gpu/drm/amd/amdgpu/mes_v10_1.c | 15 ++++++++++++++- >>>> drivers/gpu/drm/amd/amdgpu/mes_v11_0.c | 15 ++++++++++++++- >>>> 3 files changed, 28 insertions(+), 5 deletions(-) >>>> >>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c >>>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c >>>> index da48b6da0107..7db80ffda33f 100644 >>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c >>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c >>>> @@ -148,9 +148,6 @@ int amdgpu_mes_init(struct amdgpu_device >> *adev) >>>> adev->mes.compute_hqd_mask[i] = 0xc; >>>> } >>>> >>>> - for (i = 0; i < AMDGPU_MES_MAX_GFX_PIPES; i++) >>>> - adev->mes.gfx_hqd_mask[i] = i ? 0 : 0xfffffffe; >>>> - >>>> for (i = 0; i < AMDGPU_MES_MAX_SDMA_PIPES; i++) { >>>> if (amdgpu_ip_version(adev, SDMA0_HWIP, 0) < >>>> IP_VERSION(6, 0, 0)) diff --git >>>> a/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c >>>> b/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c >>>> index 1e5ad1e08d2a..9217914f824d 100644 >>>> --- a/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c >>>> +++ b/drivers/gpu/drm/amd/amdgpu/mes_v10_1.c >>>> @@ -266,6 +266,19 @@ static int mes_v10_1_query_sched_status(struct >>>> amdgpu_mes *mes) >>>> offsetof(union MESAPI__QUERY_MES_STATUS, >>>> api_status)); } >>>> >>>> +static inline uint32_t mes_v10_get_gfx_hqd_mask(int pipe_index) { >>>> + /* Pipe 1 can't be used for MES due to HW limitation */ >>>> + if (pipe_index == 1) >>>> + return 0; >>>> + >>>> + /* >>>> + * GFX V10 supports 2 queues, but we want to keep queue 0 >>>> + * reserved for kernel, so enable only queue 1 (1<<1) for MES. >>>> + */ >>>> + return 0x2; >>>> +} >>>> + >>>> static int mes_v10_1_set_hw_resources(struct amdgpu_mes *mes) { >>>> int i; >>>> @@ -291,7 +304,7 @@ static int mes_v10_1_set_hw_resources(struct >>>> amdgpu_mes *mes) >>>> mes->compute_hqd_mask[i]; >>>> >>>> for (i = 0; i < MAX_GFX_PIPES; i++) >>>> - mes_set_hw_res_pkt.gfx_hqd_mask[i] = mes->gfx_hqd_mask[i]; >>>> + mes_set_hw_res_pkt.gfx_hqd_mask[i] = >>>> + mes_v10_get_gfx_hqd_mask(i); >>>> >>>> for (i = 0; i < MAX_SDMA_PIPES; i++) >>>> mes_set_hw_res_pkt.sdma_hqd_mask[i] = >>>> mes->sdma_hqd_mask[i]; diff --git >>>> a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c >>>> b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c >>>> index 26d71a22395d..b7dcd936afc8 100644 >>>> --- a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c >>>> +++ b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c >>>> @@ -360,6 +360,19 @@ static int mes_v11_0_misc_op(struct >> amdgpu_mes >>>> *mes, >>>> offsetof(union MESAPI__MISC, api_status)); >>>> } >>>> >>>> +static inline uint32_t mes_v11_get_gfx_hqd_mask(int pipe_index) { >>>> + /* Pipe 1 can't be used for MES due to HW limitation */ >>>> + if (pipe_index == 1) >>>> + return 0; >>>> + >>>> + /* >>>> + * GFX V10 supports 2 queues, but we want to keep queue 0 >>>> + * reserved for kernel, so enable only queue 1 (1<<1) for MES. >>>> + */ >>>> + return 0x2; >>>> +} >>> There is no difference between this function and the corresponding function >> written for GFX10. >>> Why not make this a common function instead? >> This is deliberate, to indicate that the HQD mask can be different for each GFX >> IP version, so as the number of pipes and queue per pipe. Also the limitation >> on pipe 1 will not be there for future versions. >> > But for now this is common for both GFX10 and GFX11. When we have a case where this changes in future, we can implement a new > function specific for that GFX IP version. For now, this should be a common function. > > Regards, > Mukul Mukul, This was already in a common function and this could have been fixed there, but the reason to write two function is to make the HQD mask setup IP file specific. There would be some follow up patches for the same for the SDMA IP as well. As you can see, there are multiple common/duplicate functions already existing in IP specific files (gfx/vcn/sdma) but we keep it like that to indicate that these values and setups can be IP specific. - Shashank > >> - Shashank >> >>> Regards, >>> Mukul >>> >>>> + >>>> static int mes_v11_0_set_hw_resources(struct amdgpu_mes *mes) { >>>> int i; >>>> @@ -385,7 +398,7 @@ static int mes_v11_0_set_hw_resources(struct >>>> amdgpu_mes *mes) >>>> mes->compute_hqd_mask[i]; >>>> >>>> for (i = 0; i < MAX_GFX_PIPES; i++) >>>> - mes_set_hw_res_pkt.gfx_hqd_mask[i] = mes->gfx_hqd_mask[i]; >>>> + mes_set_hw_res_pkt.gfx_hqd_mask[i] = >>>> + mes_v11_get_gfx_hqd_mask(i); >>>> >>>> for (i = 0; i < MAX_SDMA_PIPES; i++) >>>> mes_set_hw_res_pkt.sdma_hqd_mask[i] = >>>> mes->sdma_hqd_mask[i]; >>>> -- >>>> 2.43.2 ^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2024-04-05 17:34 UTC | newest] Thread overview: 5+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2024-04-05 14:36 [PATCH] drm/amdgpu: fix MES HQD masks Shashank Sharma 2024-04-05 15:26 ` Joshi, Mukul 2024-04-05 15:37 ` Sharma, Shashank 2024-04-05 16:39 ` Joshi, Mukul 2024-04-05 17:34 ` Sharma, Shashank
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