From: "Khatri, Sunil" <sukhatri@amd.com>
To: Alex Deucher <alexander.deucher@amd.com>, amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH 07/11] drm/amdgpu/gfx11: add support for disable_kq
Date: Thu, 6 Mar 2025 16:33:24 +0530 [thread overview]
Message-ID: <3f1deb74-5798-4d4d-a7dd-4556def5db25@amd.com> (raw)
In-Reply-To: <20250305204721.1213836-8-alexander.deucher@amd.com>
Reviewed-by: Sunil Khatri <sunil.khatri@amd.com>
On 3/6/2025 2:17 AM, Alex Deucher wrote:
> Plumb in support for disabling kernel queues in
> GFX11. We have to bring up a GFX queue briefly in
> order to initialize the clear state. After that
> we can disable it.
>
> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 77 +++++++++++++++++---------
> 1 file changed, 51 insertions(+), 26 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
> index 3e49c0f399e02..e18100c5faa2a 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
> @@ -1128,6 +1128,10 @@ static int gfx_v11_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id,
>
> ring->ring_obj = NULL;
> ring->use_doorbell = true;
> + if (adev->gfx.disable_kq) {
> + ring->no_scheduler = true;
> + ring->no_user_submission = true;
> + }
>
> if (!ring_id)
> ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1;
> @@ -1709,21 +1713,23 @@ static int gfx_v11_0_sw_init(struct amdgpu_ip_block *ip_block)
> }
> }
>
> - ring_id = 0;
> - /* set up the compute queues - allocate horizontally across pipes */
> - for (i = 0; i < adev->gfx.mec.num_mec; ++i) {
> - for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {
> - for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
> - if (!amdgpu_gfx_is_mec_queue_enabled(adev, 0, i,
> - k, j))
> - continue;
> + if (!adev->gfx.disable_kq) {
> + ring_id = 0;
> + /* set up the compute queues - allocate horizontally across pipes */
> + for (i = 0; i < adev->gfx.mec.num_mec; ++i) {
> + for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {
> + for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
> + if (!amdgpu_gfx_is_mec_queue_enabled(adev, 0, i,
> + k, j))
> + continue;
>
> - r = gfx_v11_0_compute_ring_init(adev, ring_id,
> - i, k, j);
> - if (r)
> - return r;
> + r = gfx_v11_0_compute_ring_init(adev, ring_id,
> + i, k, j);
> + if (r)
> + return r;
>
> - ring_id++;
> + ring_id++;
> + }
> }
> }
> }
> @@ -1823,8 +1829,10 @@ static int gfx_v11_0_sw_fini(struct amdgpu_ip_block *ip_block)
>
> for (i = 0; i < adev->gfx.num_gfx_rings; i++)
> amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
> - for (i = 0; i < adev->gfx.num_compute_rings; i++)
> - amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
> + if (!adev->gfx.disable_kq) {
> + for (i = 0; i < adev->gfx.num_compute_rings; i++)
> + amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
> + }
>
> amdgpu_gfx_mqd_sw_fini(adev, 0);
>
> @@ -4489,6 +4497,9 @@ static int gfx_v11_0_kcq_resume(struct amdgpu_device *adev)
> if (!amdgpu_async_gfx_ring)
> gfx_v11_0_cp_compute_enable(adev, true);
>
> + if (adev->gfx.disable_kq)
> + return 0;
> +
> for (i = 0; i < adev->gfx.num_compute_rings; i++) {
> ring = &adev->gfx.compute_ring[i];
>
> @@ -4561,18 +4572,29 @@ static int gfx_v11_0_cp_resume(struct amdgpu_device *adev)
> return r;
> }
>
> - for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
> - ring = &adev->gfx.gfx_ring[i];
> - r = amdgpu_ring_test_helper(ring);
> - if (r)
> - return r;
> - }
> + if (adev->gfx.disable_kq) {
> + for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
> + ring = &adev->gfx.gfx_ring[i];
> + /* we don't want to set ring->ready */
> + r = amdgpu_ring_test_ring(ring);
> + if (r)
> + return r;
> + }
> + amdgpu_gfx_disable_kgq(adev, 0);
> + } else {
> + for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
> + ring = &adev->gfx.gfx_ring[i];
> + r = amdgpu_ring_test_helper(ring);
> + if (r)
> + return r;
> + }
>
> - for (i = 0; i < adev->gfx.num_compute_rings; i++) {
> - ring = &adev->gfx.compute_ring[i];
> - r = amdgpu_ring_test_helper(ring);
> - if (r)
> - return r;
> + for (i = 0; i < adev->gfx.num_compute_rings; i++) {
> + ring = &adev->gfx.compute_ring[i];
> + r = amdgpu_ring_test_helper(ring);
> + if (r)
> + return r;
> + }
> }
>
> return 0;
> @@ -5111,6 +5133,9 @@ static int gfx_v11_0_early_init(struct amdgpu_ip_block *ip_block)
> {
> struct amdgpu_device *adev = ip_block->adev;
>
> + if (amdgpu_disable_kq == 1)
> + adev->gfx.disable_kq = true;
> +
> adev->gfx.funcs = &gfx_v11_0_gfx_funcs;
>
> adev->gfx.num_gfx_rings = GFX11_NUM_GFX_RINGS;
next prev parent reply other threads:[~2025-03-06 11:03 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-03-05 20:47 [PATCH 00/11] Add disable kernel queue support Alex Deucher
2025-03-05 20:47 ` [PATCH 01/11] drm/amdgpu: add parameter to disable kernel queues Alex Deucher
2025-03-06 7:37 ` Khatri, Sunil
2025-03-05 20:47 ` [PATCH 02/11] drm/amdgpu: add ring flag for no user submissions Alex Deucher
2025-03-06 7:48 ` Khatri, Sunil
2025-03-06 16:00 ` Alex Deucher
2025-03-05 20:47 ` [PATCH 03/11] drm/amdgpu/gfx: add generic handling for disable_kq Alex Deucher
2025-03-06 1:06 ` Felix Kuehling
2025-03-06 9:57 ` Khatri, Sunil
2025-03-05 20:47 ` [PATCH 04/11] drm/amdgpu/mes: centralize gfx_hqd mask management Alex Deucher
2025-03-06 10:20 ` Khatri, Sunil
2025-03-05 20:47 ` [PATCH 05/11] drm/amdgpu/mes: update hqd masks when disable_kq is set Alex Deucher
2025-03-06 10:21 ` Khatri, Sunil
2025-03-05 20:47 ` [PATCH 06/11] drm/amdgpu/mes: make more vmids available when disable_kq=1 Alex Deucher
2025-03-06 10:21 ` Khatri, Sunil
2025-03-05 20:47 ` [PATCH 07/11] drm/amdgpu/gfx11: add support for disable_kq Alex Deucher
2025-03-06 11:03 ` Khatri, Sunil [this message]
2025-03-05 20:47 ` [PATCH 08/11] drm/amdgpu/gfx12: " Alex Deucher
2025-03-06 11:16 ` Khatri, Sunil
2025-03-05 20:47 ` [PATCH 09/11] drm/amdgpu/sdma: add flag for tracking disable_kq Alex Deucher
2025-03-06 11:19 ` Khatri, Sunil
2025-03-05 20:47 ` [PATCH 10/11] drm/amdgpu/sdma6: add support for disable_kq Alex Deucher
2025-03-06 11:19 ` Khatri, Sunil
2025-03-05 20:47 ` [PATCH 11/11] drm/amdgpu/sdma7: " Alex Deucher
2025-03-06 11:20 ` Khatri, Sunil
-- strict thread matches above, loose matches on Subject: below --
2025-03-06 18:46 [PATCH V2 00/11] Add disable kernel queue support Alex Deucher
2025-03-06 18:46 ` [PATCH 07/11] drm/amdgpu/gfx11: add support for disable_kq Alex Deucher
2025-03-07 15:15 [PATCH V3 00/11] Add disable kernel queue support Alex Deucher
2025-03-07 15:16 ` [PATCH 07/11] drm/amdgpu/gfx11: add support for disable_kq Alex Deucher
2025-03-12 18:57 [PATCH V4 00/11] Add disable kernel queue support Alex Deucher
2025-03-12 18:57 ` [PATCH 07/11] drm/amdgpu/gfx11: add support for disable_kq Alex Deucher
2025-03-13 14:41 [PATCH V5 00/11] Add disable kernel queue support Alex Deucher
2025-03-13 14:41 ` [PATCH 07/11] drm/amdgpu/gfx11: add support for disable_kq Alex Deucher
2025-03-13 22:08 ` Rodrigo Siqueira
2025-03-14 1:50 ` Alex Deucher
2025-03-14 11:39 ` Khatri, Sunil
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=3f1deb74-5798-4d4d-a7dd-4556def5db25@amd.com \
--to=sukhatri@amd.com \
--cc=alexander.deucher@amd.com \
--cc=amd-gfx@lists.freedesktop.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox