Re: [PATCH 04/11] drm/amdgpu/mes: centralize gfx_hqd mask management

["Khatri, Sunil" <sukhatri@amd.com>]

On 3/6/2025 2:17 AM, Alex Deucher wrote:
> Move it to amdgpu_mes to align with the compute and
> sdma hqd masks. No functional change.
>
> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> ---
>   drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c | 24 ++++++++++++++++++++++++
>   drivers/gpu/drm/amd/amdgpu/mes_v11_0.c  | 16 +++-------------
>   drivers/gpu/drm/amd/amdgpu/mes_v12_0.c  | 15 +++------------
>   3 files changed, 30 insertions(+), 25 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
> index ca076306adba4..afc2ce344df52 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
> @@ -144,6 +144,30 @@ int amdgpu_mes_init(struct amdgpu_device *adev)
>   	adev->mes.vmid_mask_mmhub = 0xffffff00;
>   	adev->mes.vmid_mask_gfxhub = 0xffffff00;
>   
> +	if (adev->gfx.num_gfx_rings) {
when kernel queue is disabled then arent we having gfx.num_gfx_rings ==  
0, so this might not run at all ? Hope we taking care of that situation 
too ?
> +		for (i = 0; i < AMDGPU_MES_MAX_GFX_PIPES; i++) {
> +			/* use only 1st ME pipe */
> +			if (i >= adev->gfx.me.num_pipe_per_me)
> +				continue;

this if condition makes the outside for loop to run just once and due to 
which adev->mes.gfx_hqd_mask[1] = 0x0; is never set but based on 
previous code we need to set that to 0

as pipe 1 is disabled in hq or here we do not need to set 
adev->mes.gfx_hqd_mask at all now ?

> +			if (amdgpu_ip_version(adev, GC_HWIP, 0) >=
> +			    IP_VERSION(12, 0, 0))
> +				/*
> +				 * GFX V12 has only one GFX pipe, but 8 queues in it.
> +				 * GFX pipe 0 queue 0 is being used by Kernel queue.
> +				 * Set GFX pipe 0 queue 1-7 for MES scheduling
> +				 * mask = 1111 1110b
> +				 */
> +				adev->mes.gfx_hqd_mask[i] = 0xFE;
> +			else
> +				/*
> +				 * GFX pipe 0 queue 0 is being used by Kernel queue.
> +				 * Set GFX pipe 0 queue 1 for MES scheduling
> +				 * mask = 10b
> +				 */
> +				adev->mes.gfx_hqd_mask[i] = 0x2;
> +		}
> +	}
> +
>   	for (i = 0; i < AMDGPU_MES_MAX_COMPUTE_PIPES; i++) {
>   		/* use only 1st MEC pipes */
>   		if (i >= adev->gfx.mec.num_pipe_per_mec)
> diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
> index a569d09a1a748..39b45d8b5f049 100644
> --- a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
> @@ -669,18 +669,6 @@ static int mes_v11_0_misc_op(struct amdgpu_mes *mes,
>   			offsetof(union MESAPI__MISC, api_status));
>   }
>   
> -static void mes_v11_0_set_gfx_hqd_mask(union MESAPI_SET_HW_RESOURCES *pkt)
> -{
> -	/*
> -	 * GFX pipe 0 queue 0 is being used by Kernel queue.
> -	 * Set GFX pipe 0 queue 1 for MES scheduling
> -	 * mask = 10b
> -	 * GFX pipe 1 can't be used for MES due to HW limitation.
> -	 */
> -	pkt->gfx_hqd_mask[0] = 0x2;
> -	pkt->gfx_hqd_mask[1] = 0;
> -}
> -
>   static int mes_v11_0_set_hw_resources(struct amdgpu_mes *mes)
>   {
>   	int i;
> @@ -705,7 +693,9 @@ static int mes_v11_0_set_hw_resources(struct amdgpu_mes *mes)
>   		mes_set_hw_res_pkt.compute_hqd_mask[i] =
>   			mes->compute_hqd_mask[i];
>   
> -	mes_v11_0_set_gfx_hqd_mask(&mes_set_hw_res_pkt);
> +	for (i = 0; i < MAX_GFX_PIPES; i++)
> +		mes_set_hw_res_pkt.gfx_hqd_mask[i] =
> +			mes->gfx_hqd_mask[i];
>   
>   	for (i = 0; i < MAX_SDMA_PIPES; i++)
>   		mes_set_hw_res_pkt.sdma_hqd_mask[i] = mes->sdma_hqd_mask[i];
> diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c b/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c
> index 96336652d14c5..519f054bec60d 100644
> --- a/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c
> @@ -694,17 +694,6 @@ static int mes_v12_0_set_hw_resources_1(struct amdgpu_mes *mes, int pipe)
>   			offsetof(union MESAPI_SET_HW_RESOURCES_1, api_status));
>   }
>   
> -static void mes_v12_0_set_gfx_hqd_mask(union MESAPI_SET_HW_RESOURCES *pkt)
> -{
> -	/*
> -	 * GFX V12 has only one GFX pipe, but 8 queues in it.
> -	 * GFX pipe 0 queue 0 is being used by Kernel queue.
> -	 * Set GFX pipe 0 queue 1-7 for MES scheduling
> -	 * mask = 1111 1110b
> -	 */
> -	pkt->gfx_hqd_mask[0] = 0xFE;
> -}
> -
>   static int mes_v12_0_set_hw_resources(struct amdgpu_mes *mes, int pipe)
>   {
>   	int i;
> @@ -727,7 +716,9 @@ static int mes_v12_0_set_hw_resources(struct amdgpu_mes *mes, int pipe)
>   			mes_set_hw_res_pkt.compute_hqd_mask[i] =
>   				mes->compute_hqd_mask[i];
>   
> -		mes_v12_0_set_gfx_hqd_mask(&mes_set_hw_res_pkt);
> +		for (i = 0; i < MAX_GFX_PIPES; i++)
> +			mes_set_hw_res_pkt.gfx_hqd_mask[i] =
> +				mes->gfx_hqd_mask[i];
>   
>   		for (i = 0; i < MAX_SDMA_PIPES; i++)
>   			mes_set_hw_res_pkt.sdma_hqd_mask[i] =