* [PATCH] drm/amdgpu: attach tlb fence to the PTs update @ 2025-11-05 12:14 Prike Liang 2025-11-05 12:49 ` Christian König 0 siblings, 1 reply; 4+ messages in thread From: Prike Liang @ 2025-11-05 12:14 UTC (permalink / raw) To: amd-gfx Cc: Alexander.Deucher, Christian.Koenig, Prike Liang, Christian König Ensure the userq TLB flush is emitted only after the VM update finishes and the PT BOs have been annotated with bookkeeping fences. Suggested-by: Christian König <christian.koenig@amd.com> Signed-off-by: Prike Liang <Prike.Liang@amd.com> --- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index db66b4232de0..79d687dee877 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -1062,7 +1062,7 @@ amdgpu_vm_tlb_flush(struct amdgpu_vm_update_params *params, } /* Prepare a TLB flush fence to be attached to PTs */ - if (!params->unlocked && vm->is_compute_context) { + if (!params->unlocked) { amdgpu_vm_tlb_fence_create(params->adev, vm, fence); /* Makes sure no PD/PT is freed before the flush */ -- 2.34.1 ^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH] drm/amdgpu: attach tlb fence to the PTs update 2025-11-05 12:14 [PATCH] drm/amdgpu: attach tlb fence to the PTs update Prike Liang @ 2025-11-05 12:49 ` Christian König 2025-11-05 13:38 ` Liang, Prike 0 siblings, 1 reply; 4+ messages in thread From: Christian König @ 2025-11-05 12:49 UTC (permalink / raw) To: Prike Liang, amd-gfx; +Cc: Alexander.Deucher On 11/5/25 13:14, Prike Liang wrote: > Ensure the userq TLB flush is emitted only after > the VM update finishes and the PT BOs have been > annotated with bookkeeping fences. > > Suggested-by: Christian König <christian.koenig@amd.com> > Signed-off-by: Prike Liang <Prike.Liang@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Could be that people start to complain that this results in extra overhead, but that shouldn't be much of an issue. Regards, Christian. > --- > drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c > index db66b4232de0..79d687dee877 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c > @@ -1062,7 +1062,7 @@ amdgpu_vm_tlb_flush(struct amdgpu_vm_update_params *params, > } > > /* Prepare a TLB flush fence to be attached to PTs */ > - if (!params->unlocked && vm->is_compute_context) { > + if (!params->unlocked) { > amdgpu_vm_tlb_fence_create(params->adev, vm, fence); > > /* Makes sure no PD/PT is freed before the flush */ ^ permalink raw reply [flat|nested] 4+ messages in thread
* RE: [PATCH] drm/amdgpu: attach tlb fence to the PTs update 2025-11-05 12:49 ` Christian König @ 2025-11-05 13:38 ` Liang, Prike 2025-11-05 13:40 ` Christian König 0 siblings, 1 reply; 4+ messages in thread From: Liang, Prike @ 2025-11-05 13:38 UTC (permalink / raw) To: Koenig, Christian, amd-gfx@lists.freedesktop.org; +Cc: Deucher, Alexander [Public] Regards, Prike > -----Original Message----- > From: Koenig, Christian <Christian.Koenig@amd.com> > Sent: Wednesday, November 5, 2025 8:50 PM > To: Liang, Prike <Prike.Liang@amd.com>; amd-gfx@lists.freedesktop.org > Cc: Deucher, Alexander <Alexander.Deucher@amd.com> > Subject: Re: [PATCH] drm/amdgpu: attach tlb fence to the PTs update > > > > On 11/5/25 13:14, Prike Liang wrote: > > Ensure the userq TLB flush is emitted only after the VM update > > finishes and the PT BOs have been annotated with bookkeeping fences. > > > > Suggested-by: Christian König <christian.koenig@amd.com> > > Signed-off-by: Prike Liang <Prike.Liang@amd.com> > > Reviewed-by: Christian König <christian.koenig@amd.com> > > Could be that people start to complain that this results in extra overhead, but that > shouldn't be much of an issue. If without sorting the userq or KFD compute context, maybe overhead on legacy kernel queue case? > Regards, > Christian. > > > --- > > drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c > > b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c > > index db66b4232de0..79d687dee877 100644 > > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c > > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c > > @@ -1062,7 +1062,7 @@ amdgpu_vm_tlb_flush(struct > amdgpu_vm_update_params *params, > > } > > > > /* Prepare a TLB flush fence to be attached to PTs */ > > - if (!params->unlocked && vm->is_compute_context) { > > + if (!params->unlocked) { > > amdgpu_vm_tlb_fence_create(params->adev, vm, fence); > > > > /* Makes sure no PD/PT is freed before the flush */ ^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH] drm/amdgpu: attach tlb fence to the PTs update 2025-11-05 13:38 ` Liang, Prike @ 2025-11-05 13:40 ` Christian König 0 siblings, 0 replies; 4+ messages in thread From: Christian König @ 2025-11-05 13:40 UTC (permalink / raw) To: Liang, Prike, amd-gfx@lists.freedesktop.org; +Cc: Deucher, Alexander On 11/5/25 14:38, Liang, Prike wrote: > [Public] > > Regards, > Prike > >> -----Original Message----- >> From: Koenig, Christian <Christian.Koenig@amd.com> >> Sent: Wednesday, November 5, 2025 8:50 PM >> To: Liang, Prike <Prike.Liang@amd.com>; amd-gfx@lists.freedesktop.org >> Cc: Deucher, Alexander <Alexander.Deucher@amd.com> >> Subject: Re: [PATCH] drm/amdgpu: attach tlb fence to the PTs update >> >> >> >> On 11/5/25 13:14, Prike Liang wrote: >>> Ensure the userq TLB flush is emitted only after the VM update >>> finishes and the PT BOs have been annotated with bookkeeping fences. >>> >>> Suggested-by: Christian König <christian.koenig@amd.com> >>> Signed-off-by: Prike Liang <Prike.Liang@amd.com> >> >> Reviewed-by: Christian König <christian.koenig@amd.com> >> >> Could be that people start to complain that this results in extra overhead, but that >> shouldn't be much of an issue. > If without sorting the userq or KFD compute context, maybe overhead on legacy kernel queue case? Yes, starting a worker all the time is not that much overhead but checking all the VMIDs for the PASID is. We could make it depend on the HW generation if that really becomes a problem. Regards, Christian. > >> Regards, >> Christian. >> >>> --- >>> drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 2 +- >>> 1 file changed, 1 insertion(+), 1 deletion(-) >>> >>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c >>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c >>> index db66b4232de0..79d687dee877 100644 >>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c >>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c >>> @@ -1062,7 +1062,7 @@ amdgpu_vm_tlb_flush(struct >> amdgpu_vm_update_params *params, >>> } >>> >>> /* Prepare a TLB flush fence to be attached to PTs */ >>> - if (!params->unlocked && vm->is_compute_context) { >>> + if (!params->unlocked) { >>> amdgpu_vm_tlb_fence_create(params->adev, vm, fence); >>> >>> /* Makes sure no PD/PT is freed before the flush */ > ^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2025-11-05 13:40 UTC | newest] Thread overview: 4+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2025-11-05 12:14 [PATCH] drm/amdgpu: attach tlb fence to the PTs update Prike Liang 2025-11-05 12:49 ` Christian König 2025-11-05 13:38 ` Liang, Prike 2025-11-05 13:40 ` Christian König
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