* [PATCH v3 1/3] drm/amdgpu: UVD avoid memory allocation during IB test
@ 2021-09-11 1:34 xinhui pan
2021-09-11 1:34 ` [PATCH v3 2/3] drm/amdgpu: VCE " xinhui pan
` (2 more replies)
0 siblings, 3 replies; 6+ messages in thread
From: xinhui pan @ 2021-09-11 1:34 UTC (permalink / raw)
To: amd-gfx; +Cc: alexander.deucher, christian.koenig, xinhui pan
move BO allocation in sw_init.
Signed-off-by: xinhui pan <xinhui.pan@amd.com>
---
change from v2:
use reservation trylock for direct IB test.
change from v1:
only use pre-allocated BO for direct IB submission.
and take its reservation lock to avoid any potential race.
better safe than sorry.
---
drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c | 104 +++++++++++++++++-------
drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.h | 1 +
drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 8 +-
drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c | 8 +-
4 files changed, 79 insertions(+), 42 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
index d451c359606a..a4b3dd6b38c6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
@@ -134,6 +134,51 @@ MODULE_FIRMWARE(FIRMWARE_VEGA12);
MODULE_FIRMWARE(FIRMWARE_VEGA20);
static void amdgpu_uvd_idle_work_handler(struct work_struct *work);
+static void amdgpu_uvd_force_into_uvd_segment(struct amdgpu_bo *abo);
+
+static int amdgpu_uvd_create_msg_bo_helper(struct amdgpu_device *adev,
+ uint32_t size,
+ struct amdgpu_bo **bo_ptr)
+{
+ struct ttm_operation_ctx ctx = { true, false };
+ struct amdgpu_bo *bo = NULL;
+ void *addr;
+ int r;
+
+ r = amdgpu_bo_create_reserved(adev, size, PAGE_SIZE,
+ AMDGPU_GEM_DOMAIN_GTT,
+ &bo, NULL, &addr);
+ if (r)
+ return r;
+
+ if (adev->uvd.address_64_bit) {
+ *bo_ptr = bo;
+ return 0;
+ }
+
+ amdgpu_bo_kunmap(bo);
+ amdgpu_bo_unpin(bo);
+ amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_VRAM);
+ amdgpu_uvd_force_into_uvd_segment(bo);
+ r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
+ if (r)
+ goto err;
+ r = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_VRAM);
+ if (r)
+ goto err_pin;
+ r = amdgpu_bo_kmap(bo, &addr);
+ if (r)
+ goto err_kmap;
+ *bo_ptr = bo;
+ return 0;
+err_kmap:
+ amdgpu_bo_unpin(bo);
+err_pin:
+err:
+ amdgpu_bo_unreserve(bo);
+ amdgpu_bo_unref(&bo);
+ return r;
+}
int amdgpu_uvd_sw_init(struct amdgpu_device *adev)
{
@@ -302,6 +347,11 @@ int amdgpu_uvd_sw_init(struct amdgpu_device *adev)
if (!amdgpu_device_ip_block_version_cmp(adev, AMD_IP_BLOCK_TYPE_UVD, 5, 0))
adev->uvd.address_64_bit = true;
+ r = amdgpu_uvd_create_msg_bo_helper(adev, 128 << 10, &adev->uvd.ib_bo);
+ if (r)
+ return r;
+ amdgpu_bo_unreserve(adev->uvd.ib_bo);
+
switch (adev->asic_type) {
case CHIP_TONGA:
adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_65_10;
@@ -324,6 +374,7 @@ int amdgpu_uvd_sw_init(struct amdgpu_device *adev)
int amdgpu_uvd_sw_fini(struct amdgpu_device *adev)
{
+ void *addr = amdgpu_bo_kptr(adev->uvd.ib_bo);
int i, j;
drm_sched_entity_destroy(&adev->uvd.entity);
@@ -342,6 +393,7 @@ int amdgpu_uvd_sw_fini(struct amdgpu_device *adev)
for (i = 0; i < AMDGPU_MAX_UVD_ENC_RINGS; ++i)
amdgpu_ring_fini(&adev->uvd.inst[j].ring_enc[i]);
}
+ amdgpu_bo_free_kernel(&adev->uvd.ib_bo, NULL, &addr);
release_firmware(adev->uvd.fw);
return 0;
@@ -1080,23 +1132,10 @@ static int amdgpu_uvd_send_msg(struct amdgpu_ring *ring, struct amdgpu_bo *bo,
unsigned offset_idx = 0;
unsigned offset[3] = { UVD_BASE_SI, 0, 0 };
- amdgpu_bo_kunmap(bo);
- amdgpu_bo_unpin(bo);
-
- if (!ring->adev->uvd.address_64_bit) {
- struct ttm_operation_ctx ctx = { true, false };
-
- amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_VRAM);
- amdgpu_uvd_force_into_uvd_segment(bo);
- r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
- if (r)
- goto err;
- }
-
r = amdgpu_job_alloc_with_ib(adev, 64, direct ? AMDGPU_IB_POOL_DIRECT :
AMDGPU_IB_POOL_DELAYED, &job);
if (r)
- goto err;
+ return r;
if (adev->asic_type >= CHIP_VEGA10) {
offset_idx = 1 + ring->me;
@@ -1148,8 +1187,6 @@ static int amdgpu_uvd_send_msg(struct amdgpu_ring *ring, struct amdgpu_bo *bo,
}
amdgpu_bo_fence(bo, f, false);
- amdgpu_bo_unreserve(bo);
- amdgpu_bo_unref(&bo);
if (fence)
*fence = dma_fence_get(f);
@@ -1159,10 +1196,6 @@ static int amdgpu_uvd_send_msg(struct amdgpu_ring *ring, struct amdgpu_bo *bo,
err_free:
amdgpu_job_free(job);
-
-err:
- amdgpu_bo_unreserve(bo);
- amdgpu_bo_unref(&bo);
return r;
}
@@ -1173,16 +1206,16 @@ int amdgpu_uvd_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
struct dma_fence **fence)
{
struct amdgpu_device *adev = ring->adev;
- struct amdgpu_bo *bo = NULL;
+ struct amdgpu_bo *bo = adev->uvd.ib_bo;
uint32_t *msg;
int r, i;
- r = amdgpu_bo_create_reserved(adev, 1024, PAGE_SIZE,
- AMDGPU_GEM_DOMAIN_GTT,
- &bo, NULL, (void **)&msg);
+ /* Direct IB submission should be exclusive. */
+ r = WARN_ON_ONCE(ttm_bo_reserve(&bo->tbo, true, true, NULL));
if (r)
return r;
+ msg = amdgpu_bo_kptr(bo);
/* stitch together an UVD create msg */
msg[0] = cpu_to_le32(0x00000de4);
msg[1] = cpu_to_le32(0x00000000);
@@ -1198,23 +1231,28 @@ int amdgpu_uvd_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
for (i = 11; i < 1024; ++i)
msg[i] = cpu_to_le32(0x0);
- return amdgpu_uvd_send_msg(ring, bo, true, fence);
+ r = amdgpu_uvd_send_msg(ring, bo, true, fence);
+
+ amdgpu_bo_unreserve(bo);
+ return r;
}
int amdgpu_uvd_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
bool direct, struct dma_fence **fence)
{
struct amdgpu_device *adev = ring->adev;
- struct amdgpu_bo *bo = NULL;
+ struct amdgpu_bo *bo = adev->uvd.ib_bo;
uint32_t *msg;
int r, i;
- r = amdgpu_bo_create_reserved(adev, 1024, PAGE_SIZE,
- AMDGPU_GEM_DOMAIN_GTT,
- &bo, NULL, (void **)&msg);
+ if (direct)
+ r = WARN_ON_ONCE(ttm_bo_reserve(&bo->tbo, true, true, NULL));
+ else
+ r = amdgpu_uvd_create_msg_bo_helper(adev, 4096, &bo);
if (r)
return r;
+ msg = amdgpu_bo_kptr(bo);
/* stitch together an UVD destroy msg */
msg[0] = cpu_to_le32(0x00000de4);
msg[1] = cpu_to_le32(0x00000002);
@@ -1223,7 +1261,13 @@ int amdgpu_uvd_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
for (i = 4; i < 1024; ++i)
msg[i] = cpu_to_le32(0x0);
- return amdgpu_uvd_send_msg(ring, bo, direct, fence);
+ r = amdgpu_uvd_send_msg(ring, bo, direct, fence);
+
+ amdgpu_bo_unreserve(bo);
+ if (!direct)
+ amdgpu_bo_free_kernel(&bo, NULL, (void **)&msg);
+
+ return r;
}
static void amdgpu_uvd_idle_work_handler(struct work_struct *work)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.h
index edbb8194ee81..76ac9699885d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.h
@@ -68,6 +68,7 @@ struct amdgpu_uvd {
/* store image width to adjust nb memory state */
unsigned decode_image_width;
uint32_t keyselect;
+ struct amdgpu_bo *ib_bo;
};
int amdgpu_uvd_sw_init(struct amdgpu_device *adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
index bc571833632e..dd92d96dd5a2 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
@@ -332,12 +332,10 @@ static int uvd_v6_0_enc_get_destroy_msg(struct amdgpu_ring *ring,
static int uvd_v6_0_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout)
{
struct dma_fence *fence = NULL;
- struct amdgpu_bo *bo = NULL;
+ struct amdgpu_bo *bo = ring->adev->uvd.ib_bo;
long r;
- r = amdgpu_bo_create_reserved(ring->adev, 128 * 1024, PAGE_SIZE,
- AMDGPU_GEM_DOMAIN_VRAM,
- &bo, NULL, NULL);
+ r = WARN_ON_ONCE(ttm_bo_reserve(&bo->tbo, true, true, NULL));
if (r)
return r;
@@ -357,9 +355,7 @@ static int uvd_v6_0_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout)
error:
dma_fence_put(fence);
- amdgpu_bo_unpin(bo);
amdgpu_bo_unreserve(bo);
- amdgpu_bo_unref(&bo);
return r;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
index b6e82d75561f..271122cf2237 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
@@ -338,12 +338,10 @@ static int uvd_v7_0_enc_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handl
static int uvd_v7_0_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout)
{
struct dma_fence *fence = NULL;
- struct amdgpu_bo *bo = NULL;
+ struct amdgpu_bo *bo = ring->adev->uvd.ib_bo;
long r;
- r = amdgpu_bo_create_reserved(ring->adev, 128 * 1024, PAGE_SIZE,
- AMDGPU_GEM_DOMAIN_VRAM,
- &bo, NULL, NULL);
+ r = WARN_ON_ONCE(ttm_bo_reserve(&bo->tbo, true, true, NULL));
if (r)
return r;
@@ -363,9 +361,7 @@ static int uvd_v7_0_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout)
error:
dma_fence_put(fence);
- amdgpu_bo_unpin(bo);
amdgpu_bo_unreserve(bo);
- amdgpu_bo_unref(&bo);
return r;
}
--
2.25.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH v3 2/3] drm/amdgpu: VCE avoid memory allocation during IB test
2021-09-11 1:34 [PATCH v3 1/3] drm/amdgpu: UVD avoid memory allocation during IB test xinhui pan
@ 2021-09-11 1:34 ` xinhui pan
2021-09-11 1:34 ` [PATCH v3 3/3] drm/amdgpu: VCN " xinhui pan
2021-09-13 6:31 ` [PATCH v3 1/3] drm/amdgpu: UVD " Christian König
2 siblings, 0 replies; 6+ messages in thread
From: xinhui pan @ 2021-09-11 1:34 UTC (permalink / raw)
To: amd-gfx; +Cc: alexander.deucher, christian.koenig, xinhui pan
alloc extra msg from direct IB pool.
Signed-off-by: xinhui pan <xinhui.pan@amd.com>
---
change from v1:
let addr align up to gpu page boundary.
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c | 27 ++++++++++++-------------
1 file changed, 13 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
index e9fdf49d69e8..caa4d3420e00 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
@@ -82,7 +82,6 @@ MODULE_FIRMWARE(FIRMWARE_VEGA20);
static void amdgpu_vce_idle_work_handler(struct work_struct *work);
static int amdgpu_vce_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
- struct amdgpu_bo *bo,
struct dma_fence **fence);
static int amdgpu_vce_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
bool direct, struct dma_fence **fence);
@@ -441,12 +440,12 @@ void amdgpu_vce_free_handles(struct amdgpu_device *adev, struct drm_file *filp)
* Open up a stream for HW test
*/
static int amdgpu_vce_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
- struct amdgpu_bo *bo,
struct dma_fence **fence)
{
const unsigned ib_size_dw = 1024;
struct amdgpu_job *job;
struct amdgpu_ib *ib;
+ struct amdgpu_ib ib_msg;
struct dma_fence *f = NULL;
uint64_t addr;
int i, r;
@@ -456,9 +455,17 @@ static int amdgpu_vce_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
if (r)
return r;
- ib = &job->ibs[0];
+ memset(&ib_msg, 0, sizeof(ib_msg));
+ /* only one gpu page is needed, alloc +1 page to make addr aligned. */
+ r = amdgpu_ib_get(ring->adev, NULL, AMDGPU_GPU_PAGE_SIZE * 2,
+ AMDGPU_IB_POOL_DIRECT,
+ &ib_msg);
+ if (r)
+ goto err;
- addr = amdgpu_bo_gpu_offset(bo);
+ ib = &job->ibs[0];
+ /* let addr point to page boundary */
+ addr = AMDGPU_GPU_PAGE_ALIGN(ib_msg.gpu_addr);
/* stitch together an VCE create msg */
ib->length_dw = 0;
@@ -498,6 +505,7 @@ static int amdgpu_vce_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
ib->ptr[i] = 0x0;
r = amdgpu_job_submit_direct(job, ring, &f);
+ amdgpu_ib_free(ring->adev, &ib_msg, f);
if (r)
goto err;
@@ -1134,20 +1142,13 @@ int amdgpu_vce_ring_test_ring(struct amdgpu_ring *ring)
int amdgpu_vce_ring_test_ib(struct amdgpu_ring *ring, long timeout)
{
struct dma_fence *fence = NULL;
- struct amdgpu_bo *bo = NULL;
long r;
/* skip vce ring1/2 ib test for now, since it's not reliable */
if (ring != &ring->adev->vce.ring[0])
return 0;
- r = amdgpu_bo_create_reserved(ring->adev, 512, PAGE_SIZE,
- AMDGPU_GEM_DOMAIN_VRAM,
- &bo, NULL, NULL);
- if (r)
- return r;
-
- r = amdgpu_vce_get_create_msg(ring, 1, bo, NULL);
+ r = amdgpu_vce_get_create_msg(ring, 1, NULL);
if (r)
goto error;
@@ -1163,8 +1164,6 @@ int amdgpu_vce_ring_test_ib(struct amdgpu_ring *ring, long timeout)
error:
dma_fence_put(fence);
- amdgpu_bo_unreserve(bo);
- amdgpu_bo_free_kernel(&bo, NULL, NULL);
return r;
}
--
2.25.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH v3 3/3] drm/amdgpu: VCN avoid memory allocation during IB test
2021-09-11 1:34 [PATCH v3 1/3] drm/amdgpu: UVD avoid memory allocation during IB test xinhui pan
2021-09-11 1:34 ` [PATCH v3 2/3] drm/amdgpu: VCE " xinhui pan
@ 2021-09-11 1:34 ` xinhui pan
2021-09-13 6:31 ` [PATCH v3 1/3] drm/amdgpu: UVD " Christian König
2 siblings, 0 replies; 6+ messages in thread
From: xinhui pan @ 2021-09-11 1:34 UTC (permalink / raw)
To: amd-gfx; +Cc: alexander.deucher, christian.koenig, xinhui pan
alloc extra msg from direct IB pool.
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: xinhui pan <xinhui.pan@amd.com>
---
change from v1:
let addr align up to gpu page boundary.
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 97 +++++++++++--------------
1 file changed, 44 insertions(+), 53 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
index 561296a85b43..b60b8fe5bf67 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
@@ -541,15 +541,14 @@ int amdgpu_vcn_dec_sw_ring_test_ring(struct amdgpu_ring *ring)
}
static int amdgpu_vcn_dec_send_msg(struct amdgpu_ring *ring,
- struct amdgpu_bo *bo,
+ struct amdgpu_ib *ib_msg,
struct dma_fence **fence)
{
struct amdgpu_device *adev = ring->adev;
struct dma_fence *f = NULL;
struct amdgpu_job *job;
struct amdgpu_ib *ib;
- uint64_t addr;
- void *msg = NULL;
+ uint64_t addr = AMDGPU_GPU_PAGE_ALIGN(ib_msg->gpu_addr);
int i, r;
r = amdgpu_job_alloc_with_ib(adev, 64,
@@ -558,8 +557,6 @@ static int amdgpu_vcn_dec_send_msg(struct amdgpu_ring *ring,
goto err;
ib = &job->ibs[0];
- addr = amdgpu_bo_gpu_offset(bo);
- msg = amdgpu_bo_kptr(bo);
ib->ptr[0] = PACKET0(adev->vcn.internal.data0, 0);
ib->ptr[1] = addr;
ib->ptr[2] = PACKET0(adev->vcn.internal.data1, 0);
@@ -576,9 +573,7 @@ static int amdgpu_vcn_dec_send_msg(struct amdgpu_ring *ring,
if (r)
goto err_free;
- amdgpu_bo_fence(bo, f, false);
- amdgpu_bo_unreserve(bo);
- amdgpu_bo_free_kernel(&bo, NULL, (void **)&msg);
+ amdgpu_ib_free(adev, ib_msg, f);
if (fence)
*fence = dma_fence_get(f);
@@ -588,27 +583,26 @@ static int amdgpu_vcn_dec_send_msg(struct amdgpu_ring *ring,
err_free:
amdgpu_job_free(job);
-
err:
- amdgpu_bo_unreserve(bo);
- amdgpu_bo_free_kernel(&bo, NULL, (void **)&msg);
+ amdgpu_ib_free(adev, ib_msg, f);
return r;
}
static int amdgpu_vcn_dec_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
- struct amdgpu_bo **bo)
+ struct amdgpu_ib *ib)
{
struct amdgpu_device *adev = ring->adev;
uint32_t *msg;
int r, i;
- *bo = NULL;
- r = amdgpu_bo_create_reserved(adev, 1024, PAGE_SIZE,
- AMDGPU_GEM_DOMAIN_VRAM,
- bo, NULL, (void **)&msg);
+ memset(ib, 0, sizeof(*ib));
+ r = amdgpu_ib_get(adev, NULL, AMDGPU_GPU_PAGE_SIZE * 2,
+ AMDGPU_IB_POOL_DIRECT,
+ ib);
if (r)
return r;
+ msg = (uint32_t *)AMDGPU_GPU_PAGE_ALIGN((unsigned long)ib->ptr);
msg[0] = cpu_to_le32(0x00000028);
msg[1] = cpu_to_le32(0x00000038);
msg[2] = cpu_to_le32(0x00000001);
@@ -630,19 +624,20 @@ static int amdgpu_vcn_dec_get_create_msg(struct amdgpu_ring *ring, uint32_t hand
}
static int amdgpu_vcn_dec_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
- struct amdgpu_bo **bo)
+ struct amdgpu_ib *ib)
{
struct amdgpu_device *adev = ring->adev;
uint32_t *msg;
int r, i;
- *bo = NULL;
- r = amdgpu_bo_create_reserved(adev, 1024, PAGE_SIZE,
- AMDGPU_GEM_DOMAIN_VRAM,
- bo, NULL, (void **)&msg);
+ memset(ib, 0, sizeof(*ib));
+ r = amdgpu_ib_get(adev, NULL, AMDGPU_GPU_PAGE_SIZE * 2,
+ AMDGPU_IB_POOL_DIRECT,
+ ib);
if (r)
return r;
+ msg = (uint32_t *)AMDGPU_GPU_PAGE_ALIGN((unsigned long)ib->ptr);
msg[0] = cpu_to_le32(0x00000028);
msg[1] = cpu_to_le32(0x00000018);
msg[2] = cpu_to_le32(0x00000000);
@@ -658,21 +653,21 @@ static int amdgpu_vcn_dec_get_destroy_msg(struct amdgpu_ring *ring, uint32_t han
int amdgpu_vcn_dec_ring_test_ib(struct amdgpu_ring *ring, long timeout)
{
struct dma_fence *fence = NULL;
- struct amdgpu_bo *bo;
+ struct amdgpu_ib ib;
long r;
- r = amdgpu_vcn_dec_get_create_msg(ring, 1, &bo);
+ r = amdgpu_vcn_dec_get_create_msg(ring, 1, &ib);
if (r)
goto error;
- r = amdgpu_vcn_dec_send_msg(ring, bo, NULL);
+ r = amdgpu_vcn_dec_send_msg(ring, &ib, NULL);
if (r)
goto error;
- r = amdgpu_vcn_dec_get_destroy_msg(ring, 1, &bo);
+ r = amdgpu_vcn_dec_get_destroy_msg(ring, 1, &ib);
if (r)
goto error;
- r = amdgpu_vcn_dec_send_msg(ring, bo, &fence);
+ r = amdgpu_vcn_dec_send_msg(ring, &ib, &fence);
if (r)
goto error;
@@ -688,8 +683,8 @@ int amdgpu_vcn_dec_ring_test_ib(struct amdgpu_ring *ring, long timeout)
}
static int amdgpu_vcn_dec_sw_send_msg(struct amdgpu_ring *ring,
- struct amdgpu_bo *bo,
- struct dma_fence **fence)
+ struct amdgpu_ib *ib_msg,
+ struct dma_fence **fence)
{
struct amdgpu_vcn_decode_buffer *decode_buffer = NULL;
const unsigned int ib_size_dw = 64;
@@ -697,7 +692,7 @@ static int amdgpu_vcn_dec_sw_send_msg(struct amdgpu_ring *ring,
struct dma_fence *f = NULL;
struct amdgpu_job *job;
struct amdgpu_ib *ib;
- uint64_t addr;
+ uint64_t addr = AMDGPU_GPU_PAGE_ALIGN(ib_msg->gpu_addr);
int i, r;
r = amdgpu_job_alloc_with_ib(adev, ib_size_dw * 4,
@@ -706,7 +701,6 @@ static int amdgpu_vcn_dec_sw_send_msg(struct amdgpu_ring *ring,
goto err;
ib = &job->ibs[0];
- addr = amdgpu_bo_gpu_offset(bo);
ib->length_dw = 0;
ib->ptr[ib->length_dw++] = sizeof(struct amdgpu_vcn_decode_buffer) + 8;
@@ -726,9 +720,7 @@ static int amdgpu_vcn_dec_sw_send_msg(struct amdgpu_ring *ring,
if (r)
goto err_free;
- amdgpu_bo_fence(bo, f, false);
- amdgpu_bo_unreserve(bo);
- amdgpu_bo_unref(&bo);
+ amdgpu_ib_free(adev, ib_msg, f);
if (fence)
*fence = dma_fence_get(f);
@@ -738,31 +730,29 @@ static int amdgpu_vcn_dec_sw_send_msg(struct amdgpu_ring *ring,
err_free:
amdgpu_job_free(job);
-
err:
- amdgpu_bo_unreserve(bo);
- amdgpu_bo_unref(&bo);
+ amdgpu_ib_free(adev, ib_msg, f);
return r;
}
int amdgpu_vcn_dec_sw_ring_test_ib(struct amdgpu_ring *ring, long timeout)
{
struct dma_fence *fence = NULL;
- struct amdgpu_bo *bo;
+ struct amdgpu_ib ib;
long r;
- r = amdgpu_vcn_dec_get_create_msg(ring, 1, &bo);
+ r = amdgpu_vcn_dec_get_create_msg(ring, 1, &ib);
if (r)
goto error;
- r = amdgpu_vcn_dec_sw_send_msg(ring, bo, NULL);
+ r = amdgpu_vcn_dec_sw_send_msg(ring, &ib, NULL);
if (r)
goto error;
- r = amdgpu_vcn_dec_get_destroy_msg(ring, 1, &bo);
+ r = amdgpu_vcn_dec_get_destroy_msg(ring, 1, &ib);
if (r)
goto error;
- r = amdgpu_vcn_dec_sw_send_msg(ring, bo, &fence);
+ r = amdgpu_vcn_dec_sw_send_msg(ring, &ib, &fence);
if (r)
goto error;
@@ -809,7 +799,7 @@ int amdgpu_vcn_enc_ring_test_ring(struct amdgpu_ring *ring)
}
static int amdgpu_vcn_enc_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
- struct amdgpu_bo *bo,
+ struct amdgpu_ib *ib_msg,
struct dma_fence **fence)
{
const unsigned ib_size_dw = 16;
@@ -825,7 +815,7 @@ static int amdgpu_vcn_enc_get_create_msg(struct amdgpu_ring *ring, uint32_t hand
return r;
ib = &job->ibs[0];
- addr = amdgpu_bo_gpu_offset(bo);
+ addr = AMDGPU_GPU_PAGE_ALIGN(ib_msg->gpu_addr);
ib->length_dw = 0;
ib->ptr[ib->length_dw++] = 0x00000018;
@@ -863,7 +853,7 @@ static int amdgpu_vcn_enc_get_create_msg(struct amdgpu_ring *ring, uint32_t hand
}
static int amdgpu_vcn_enc_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
- struct amdgpu_bo *bo,
+ struct amdgpu_ib *ib_msg,
struct dma_fence **fence)
{
const unsigned ib_size_dw = 16;
@@ -879,7 +869,7 @@ static int amdgpu_vcn_enc_get_destroy_msg(struct amdgpu_ring *ring, uint32_t han
return r;
ib = &job->ibs[0];
- addr = amdgpu_bo_gpu_offset(bo);
+ addr = AMDGPU_GPU_PAGE_ALIGN(ib_msg->gpu_addr);
ib->length_dw = 0;
ib->ptr[ib->length_dw++] = 0x00000018;
@@ -918,21 +908,23 @@ static int amdgpu_vcn_enc_get_destroy_msg(struct amdgpu_ring *ring, uint32_t han
int amdgpu_vcn_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout)
{
+ struct amdgpu_device *adev = ring->adev;
struct dma_fence *fence = NULL;
- struct amdgpu_bo *bo = NULL;
+ struct amdgpu_ib ib;
long r;
- r = amdgpu_bo_create_reserved(ring->adev, 128 * 1024, PAGE_SIZE,
- AMDGPU_GEM_DOMAIN_VRAM,
- &bo, NULL, NULL);
+ memset(&ib, 0, sizeof(ib));
+ r = amdgpu_ib_get(adev, NULL, (128 << 10) + AMDGPU_GPU_PAGE_SIZE,
+ AMDGPU_IB_POOL_DIRECT,
+ &ib);
if (r)
return r;
- r = amdgpu_vcn_enc_get_create_msg(ring, 1, bo, NULL);
+ r = amdgpu_vcn_enc_get_create_msg(ring, 1, &ib, NULL);
if (r)
goto error;
- r = amdgpu_vcn_enc_get_destroy_msg(ring, 1, bo, &fence);
+ r = amdgpu_vcn_enc_get_destroy_msg(ring, 1, &ib, &fence);
if (r)
goto error;
@@ -943,9 +935,8 @@ int amdgpu_vcn_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout)
r = 0;
error:
+ amdgpu_ib_free(adev, &ib, fence);
dma_fence_put(fence);
- amdgpu_bo_unreserve(bo);
- amdgpu_bo_free_kernel(&bo, NULL, NULL);
return r;
}
--
2.25.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH v3 1/3] drm/amdgpu: UVD avoid memory allocation during IB test
2021-09-11 1:34 [PATCH v3 1/3] drm/amdgpu: UVD avoid memory allocation during IB test xinhui pan
2021-09-11 1:34 ` [PATCH v3 2/3] drm/amdgpu: VCE " xinhui pan
2021-09-11 1:34 ` [PATCH v3 3/3] drm/amdgpu: VCN " xinhui pan
@ 2021-09-13 6:31 ` Christian König
2021-09-13 6:51 ` 回复: " Pan, Xinhui
2 siblings, 1 reply; 6+ messages in thread
From: Christian König @ 2021-09-13 6:31 UTC (permalink / raw)
To: xinhui pan, amd-gfx; +Cc: alexander.deucher
Am 11.09.21 um 03:34 schrieb xinhui pan:
> move BO allocation in sw_init.
>
> Signed-off-by: xinhui pan <xinhui.pan@amd.com>
> ---
> change from v2:
> use reservation trylock for direct IB test.
> change from v1:
> only use pre-allocated BO for direct IB submission.
> and take its reservation lock to avoid any potential race.
> better safe than sorry.
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c | 104 +++++++++++++++++-------
> drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.h | 1 +
> drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 8 +-
> drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c | 8 +-
> 4 files changed, 79 insertions(+), 42 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
> index d451c359606a..a4b3dd6b38c6 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
> @@ -134,6 +134,51 @@ MODULE_FIRMWARE(FIRMWARE_VEGA12);
> MODULE_FIRMWARE(FIRMWARE_VEGA20);
>
> static void amdgpu_uvd_idle_work_handler(struct work_struct *work);
> +static void amdgpu_uvd_force_into_uvd_segment(struct amdgpu_bo *abo);
> +
> +static int amdgpu_uvd_create_msg_bo_helper(struct amdgpu_device *adev,
> + uint32_t size,
> + struct amdgpu_bo **bo_ptr)
> +{
> + struct ttm_operation_ctx ctx = { true, false };
> + struct amdgpu_bo *bo = NULL;
> + void *addr;
> + int r;
> +
> + r = amdgpu_bo_create_reserved(adev, size, PAGE_SIZE,
> + AMDGPU_GEM_DOMAIN_GTT,
> + &bo, NULL, &addr);
> + if (r)
> + return r;
> +
> + if (adev->uvd.address_64_bit) {
> + *bo_ptr = bo;
> + return 0;
> + }
> +
> + amdgpu_bo_kunmap(bo);
> + amdgpu_bo_unpin(bo);
> + amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_VRAM);
> + amdgpu_uvd_force_into_uvd_segment(bo);
> + r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
> + if (r)
> + goto err;
> + r = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_VRAM);
> + if (r)
> + goto err_pin;
> + r = amdgpu_bo_kmap(bo, &addr);
> + if (r)
> + goto err_kmap;
> + *bo_ptr = bo;
> + return 0;
> +err_kmap:
> + amdgpu_bo_unpin(bo);
> +err_pin:
> +err:
> + amdgpu_bo_unreserve(bo);
> + amdgpu_bo_unref(&bo);
> + return r;
> +}
>
> int amdgpu_uvd_sw_init(struct amdgpu_device *adev)
> {
> @@ -302,6 +347,11 @@ int amdgpu_uvd_sw_init(struct amdgpu_device *adev)
> if (!amdgpu_device_ip_block_version_cmp(adev, AMD_IP_BLOCK_TYPE_UVD, 5, 0))
> adev->uvd.address_64_bit = true;
>
> + r = amdgpu_uvd_create_msg_bo_helper(adev, 128 << 10, &adev->uvd.ib_bo);
> + if (r)
> + return r;
> + amdgpu_bo_unreserve(adev->uvd.ib_bo);
> +
> switch (adev->asic_type) {
> case CHIP_TONGA:
> adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_65_10;
> @@ -324,6 +374,7 @@ int amdgpu_uvd_sw_init(struct amdgpu_device *adev)
>
> int amdgpu_uvd_sw_fini(struct amdgpu_device *adev)
> {
> + void *addr = amdgpu_bo_kptr(adev->uvd.ib_bo);
> int i, j;
>
> drm_sched_entity_destroy(&adev->uvd.entity);
> @@ -342,6 +393,7 @@ int amdgpu_uvd_sw_fini(struct amdgpu_device *adev)
> for (i = 0; i < AMDGPU_MAX_UVD_ENC_RINGS; ++i)
> amdgpu_ring_fini(&adev->uvd.inst[j].ring_enc[i]);
> }
> + amdgpu_bo_free_kernel(&adev->uvd.ib_bo, NULL, &addr);
> release_firmware(adev->uvd.fw);
>
> return 0;
> @@ -1080,23 +1132,10 @@ static int amdgpu_uvd_send_msg(struct amdgpu_ring *ring, struct amdgpu_bo *bo,
> unsigned offset_idx = 0;
> unsigned offset[3] = { UVD_BASE_SI, 0, 0 };
>
> - amdgpu_bo_kunmap(bo);
> - amdgpu_bo_unpin(bo);
> -
> - if (!ring->adev->uvd.address_64_bit) {
> - struct ttm_operation_ctx ctx = { true, false };
> -
> - amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_VRAM);
> - amdgpu_uvd_force_into_uvd_segment(bo);
> - r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
> - if (r)
> - goto err;
> - }
> -
> r = amdgpu_job_alloc_with_ib(adev, 64, direct ? AMDGPU_IB_POOL_DIRECT :
> AMDGPU_IB_POOL_DELAYED, &job);
> if (r)
> - goto err;
> + return r;
>
> if (adev->asic_type >= CHIP_VEGA10) {
> offset_idx = 1 + ring->me;
> @@ -1148,8 +1187,6 @@ static int amdgpu_uvd_send_msg(struct amdgpu_ring *ring, struct amdgpu_bo *bo,
> }
>
> amdgpu_bo_fence(bo, f, false);
> - amdgpu_bo_unreserve(bo);
> - amdgpu_bo_unref(&bo);
>
> if (fence)
> *fence = dma_fence_get(f);
> @@ -1159,10 +1196,6 @@ static int amdgpu_uvd_send_msg(struct amdgpu_ring *ring, struct amdgpu_bo *bo,
>
> err_free:
> amdgpu_job_free(job);
> -
> -err:
> - amdgpu_bo_unreserve(bo);
> - amdgpu_bo_unref(&bo);
> return r;
> }
>
> @@ -1173,16 +1206,16 @@ int amdgpu_uvd_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
> struct dma_fence **fence)
> {
> struct amdgpu_device *adev = ring->adev;
> - struct amdgpu_bo *bo = NULL;
> + struct amdgpu_bo *bo = adev->uvd.ib_bo;
> uint32_t *msg;
> int r, i;
>
> - r = amdgpu_bo_create_reserved(adev, 1024, PAGE_SIZE,
> - AMDGPU_GEM_DOMAIN_GTT,
> - &bo, NULL, (void **)&msg);
> + /* Direct IB submission should be exclusive. */
> + r = WARN_ON_ONCE(ttm_bo_reserve(&bo->tbo, true, true, NULL));
Please just completely drop taking the reservation for direct
submission. I don't want lockdep to complain about that.
> if (r)
> return r;
>
> + msg = amdgpu_bo_kptr(bo);
> /* stitch together an UVD create msg */
> msg[0] = cpu_to_le32(0x00000de4);
> msg[1] = cpu_to_le32(0x00000000);
> @@ -1198,23 +1231,28 @@ int amdgpu_uvd_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
> for (i = 11; i < 1024; ++i)
> msg[i] = cpu_to_le32(0x0);
>
> - return amdgpu_uvd_send_msg(ring, bo, true, fence);
> + r = amdgpu_uvd_send_msg(ring, bo, true, fence);
> +
> + amdgpu_bo_unreserve(bo);
> + return r;
> }
>
> int amdgpu_uvd_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
> bool direct, struct dma_fence **fence)
> {
> struct amdgpu_device *adev = ring->adev;
> - struct amdgpu_bo *bo = NULL;
> + struct amdgpu_bo *bo = adev->uvd.ib_bo;
That won't work. To make the allocation work bo must be NULL when
amdgpu_uvd_create_msg_bo_helper() is called.
Probably best to add an "*bo = NULL" to amdgpu_uvd_create_msg_bo_helper().
Regards,
Christian.
> uint32_t *msg;
> int r, i;
>
> - r = amdgpu_bo_create_reserved(adev, 1024, PAGE_SIZE,
> - AMDGPU_GEM_DOMAIN_GTT,
> - &bo, NULL, (void **)&msg);
> + if (direct)
> + r = WARN_ON_ONCE(ttm_bo_reserve(&bo->tbo, true, true, NULL));
> + else
> + r = amdgpu_uvd_create_msg_bo_helper(adev, 4096, &bo);
> if (r)
> return r;
>
> + msg = amdgpu_bo_kptr(bo);
> /* stitch together an UVD destroy msg */
> msg[0] = cpu_to_le32(0x00000de4);
> msg[1] = cpu_to_le32(0x00000002);
> @@ -1223,7 +1261,13 @@ int amdgpu_uvd_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
> for (i = 4; i < 1024; ++i)
> msg[i] = cpu_to_le32(0x0);
>
> - return amdgpu_uvd_send_msg(ring, bo, direct, fence);
> + r = amdgpu_uvd_send_msg(ring, bo, direct, fence);
> +
> + amdgpu_bo_unreserve(bo);
> + if (!direct)
> + amdgpu_bo_free_kernel(&bo, NULL, (void **)&msg);
> +
> + return r;
> }
>
> static void amdgpu_uvd_idle_work_handler(struct work_struct *work)
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.h
> index edbb8194ee81..76ac9699885d 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.h
> @@ -68,6 +68,7 @@ struct amdgpu_uvd {
> /* store image width to adjust nb memory state */
> unsigned decode_image_width;
> uint32_t keyselect;
> + struct amdgpu_bo *ib_bo;
> };
>
> int amdgpu_uvd_sw_init(struct amdgpu_device *adev);
> diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
> index bc571833632e..dd92d96dd5a2 100644
> --- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
> @@ -332,12 +332,10 @@ static int uvd_v6_0_enc_get_destroy_msg(struct amdgpu_ring *ring,
> static int uvd_v6_0_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout)
> {
> struct dma_fence *fence = NULL;
> - struct amdgpu_bo *bo = NULL;
> + struct amdgpu_bo *bo = ring->adev->uvd.ib_bo;
> long r;
>
> - r = amdgpu_bo_create_reserved(ring->adev, 128 * 1024, PAGE_SIZE,
> - AMDGPU_GEM_DOMAIN_VRAM,
> - &bo, NULL, NULL);
> + r = WARN_ON_ONCE(ttm_bo_reserve(&bo->tbo, true, true, NULL));
> if (r)
> return r;
>
> @@ -357,9 +355,7 @@ static int uvd_v6_0_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout)
>
> error:
> dma_fence_put(fence);
> - amdgpu_bo_unpin(bo);
> amdgpu_bo_unreserve(bo);
> - amdgpu_bo_unref(&bo);
> return r;
> }
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
> index b6e82d75561f..271122cf2237 100644
> --- a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
> @@ -338,12 +338,10 @@ static int uvd_v7_0_enc_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handl
> static int uvd_v7_0_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout)
> {
> struct dma_fence *fence = NULL;
> - struct amdgpu_bo *bo = NULL;
> + struct amdgpu_bo *bo = ring->adev->uvd.ib_bo;
> long r;
>
> - r = amdgpu_bo_create_reserved(ring->adev, 128 * 1024, PAGE_SIZE,
> - AMDGPU_GEM_DOMAIN_VRAM,
> - &bo, NULL, NULL);
> + r = WARN_ON_ONCE(ttm_bo_reserve(&bo->tbo, true, true, NULL));
> if (r)
> return r;
>
> @@ -363,9 +361,7 @@ static int uvd_v7_0_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout)
>
> error:
> dma_fence_put(fence);
> - amdgpu_bo_unpin(bo);
> amdgpu_bo_unreserve(bo);
> - amdgpu_bo_unref(&bo);
> return r;
> }
>
^ permalink raw reply [flat|nested] 6+ messages in thread
* 回复: [PATCH v3 1/3] drm/amdgpu: UVD avoid memory allocation during IB test
2021-09-13 6:31 ` [PATCH v3 1/3] drm/amdgpu: UVD " Christian König
@ 2021-09-13 6:51 ` Pan, Xinhui
2021-09-13 6:52 ` Christian König
0 siblings, 1 reply; 6+ messages in thread
From: Pan, Xinhui @ 2021-09-13 6:51 UTC (permalink / raw)
To: Koenig, Christian, amd-gfx@lists.freedesktop.org; +Cc: Deucher, Alexander
[AMD Official Use Only]
1) Of cource I can drop the bo resv lock as long as we fix the race of IB test. will do it in v4
2) amdgpu_uvd_create_msg_bo_helper always use a local variable *bo = NULL passed to bo_create. and assiged it to **bo_ptr on success. Of cource, I will make code easier to understand.
________________________________________
发件人: Koenig, Christian <Christian.Koenig@amd.com>
发送时间: 2021年9月13日 14:31
收件人: Pan, Xinhui; amd-gfx@lists.freedesktop.org
抄送: Deucher, Alexander
主题: Re: [PATCH v3 1/3] drm/amdgpu: UVD avoid memory allocation during IB test
Am 11.09.21 um 03:34 schrieb xinhui pan:
> move BO allocation in sw_init.
>
> Signed-off-by: xinhui pan <xinhui.pan@amd.com>
> ---
> change from v2:
> use reservation trylock for direct IB test.
> change from v1:
> only use pre-allocated BO for direct IB submission.
> and take its reservation lock to avoid any potential race.
> better safe than sorry.
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c | 104 +++++++++++++++++-------
> drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.h | 1 +
> drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 8 +-
> drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c | 8 +-
> 4 files changed, 79 insertions(+), 42 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
> index d451c359606a..a4b3dd6b38c6 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
> @@ -134,6 +134,51 @@ MODULE_FIRMWARE(FIRMWARE_VEGA12);
> MODULE_FIRMWARE(FIRMWARE_VEGA20);
>
> static void amdgpu_uvd_idle_work_handler(struct work_struct *work);
> +static void amdgpu_uvd_force_into_uvd_segment(struct amdgpu_bo *abo);
> +
> +static int amdgpu_uvd_create_msg_bo_helper(struct amdgpu_device *adev,
> + uint32_t size,
> + struct amdgpu_bo **bo_ptr)
> +{
> + struct ttm_operation_ctx ctx = { true, false };
> + struct amdgpu_bo *bo = NULL;
> + void *addr;
> + int r;
> +
> + r = amdgpu_bo_create_reserved(adev, size, PAGE_SIZE,
> + AMDGPU_GEM_DOMAIN_GTT,
> + &bo, NULL, &addr);
> + if (r)
> + return r;
> +
> + if (adev->uvd.address_64_bit) {
> + *bo_ptr = bo;
> + return 0;
> + }
> +
> + amdgpu_bo_kunmap(bo);
> + amdgpu_bo_unpin(bo);
> + amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_VRAM);
> + amdgpu_uvd_force_into_uvd_segment(bo);
> + r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
> + if (r)
> + goto err;
> + r = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_VRAM);
> + if (r)
> + goto err_pin;
> + r = amdgpu_bo_kmap(bo, &addr);
> + if (r)
> + goto err_kmap;
> + *bo_ptr = bo;
> + return 0;
> +err_kmap:
> + amdgpu_bo_unpin(bo);
> +err_pin:
> +err:
> + amdgpu_bo_unreserve(bo);
> + amdgpu_bo_unref(&bo);
> + return r;
> +}
>
> int amdgpu_uvd_sw_init(struct amdgpu_device *adev)
> {
> @@ -302,6 +347,11 @@ int amdgpu_uvd_sw_init(struct amdgpu_device *adev)
> if (!amdgpu_device_ip_block_version_cmp(adev, AMD_IP_BLOCK_TYPE_UVD, 5, 0))
> adev->uvd.address_64_bit = true;
>
> + r = amdgpu_uvd_create_msg_bo_helper(adev, 128 << 10, &adev->uvd.ib_bo);
> + if (r)
> + return r;
> + amdgpu_bo_unreserve(adev->uvd.ib_bo);
> +
> switch (adev->asic_type) {
> case CHIP_TONGA:
> adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_65_10;
> @@ -324,6 +374,7 @@ int amdgpu_uvd_sw_init(struct amdgpu_device *adev)
>
> int amdgpu_uvd_sw_fini(struct amdgpu_device *adev)
> {
> + void *addr = amdgpu_bo_kptr(adev->uvd.ib_bo);
> int i, j;
>
> drm_sched_entity_destroy(&adev->uvd.entity);
> @@ -342,6 +393,7 @@ int amdgpu_uvd_sw_fini(struct amdgpu_device *adev)
> for (i = 0; i < AMDGPU_MAX_UVD_ENC_RINGS; ++i)
> amdgpu_ring_fini(&adev->uvd.inst[j].ring_enc[i]);
> }
> + amdgpu_bo_free_kernel(&adev->uvd.ib_bo, NULL, &addr);
> release_firmware(adev->uvd.fw);
>
> return 0;
> @@ -1080,23 +1132,10 @@ static int amdgpu_uvd_send_msg(struct amdgpu_ring *ring, struct amdgpu_bo *bo,
> unsigned offset_idx = 0;
> unsigned offset[3] = { UVD_BASE_SI, 0, 0 };
>
> - amdgpu_bo_kunmap(bo);
> - amdgpu_bo_unpin(bo);
> -
> - if (!ring->adev->uvd.address_64_bit) {
> - struct ttm_operation_ctx ctx = { true, false };
> -
> - amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_VRAM);
> - amdgpu_uvd_force_into_uvd_segment(bo);
> - r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
> - if (r)
> - goto err;
> - }
> -
> r = amdgpu_job_alloc_with_ib(adev, 64, direct ? AMDGPU_IB_POOL_DIRECT :
> AMDGPU_IB_POOL_DELAYED, &job);
> if (r)
> - goto err;
> + return r;
>
> if (adev->asic_type >= CHIP_VEGA10) {
> offset_idx = 1 + ring->me;
> @@ -1148,8 +1187,6 @@ static int amdgpu_uvd_send_msg(struct amdgpu_ring *ring, struct amdgpu_bo *bo,
> }
>
> amdgpu_bo_fence(bo, f, false);
> - amdgpu_bo_unreserve(bo);
> - amdgpu_bo_unref(&bo);
>
> if (fence)
> *fence = dma_fence_get(f);
> @@ -1159,10 +1196,6 @@ static int amdgpu_uvd_send_msg(struct amdgpu_ring *ring, struct amdgpu_bo *bo,
>
> err_free:
> amdgpu_job_free(job);
> -
> -err:
> - amdgpu_bo_unreserve(bo);
> - amdgpu_bo_unref(&bo);
> return r;
> }
>
> @@ -1173,16 +1206,16 @@ int amdgpu_uvd_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
> struct dma_fence **fence)
> {
> struct amdgpu_device *adev = ring->adev;
> - struct amdgpu_bo *bo = NULL;
> + struct amdgpu_bo *bo = adev->uvd.ib_bo;
> uint32_t *msg;
> int r, i;
>
> - r = amdgpu_bo_create_reserved(adev, 1024, PAGE_SIZE,
> - AMDGPU_GEM_DOMAIN_GTT,
> - &bo, NULL, (void **)&msg);
> + /* Direct IB submission should be exclusive. */
> + r = WARN_ON_ONCE(ttm_bo_reserve(&bo->tbo, true, true, NULL));
Please just completely drop taking the reservation for direct
submission. I don't want lockdep to complain about that.
> if (r)
> return r;
>
> + msg = amdgpu_bo_kptr(bo);
> /* stitch together an UVD create msg */
> msg[0] = cpu_to_le32(0x00000de4);
> msg[1] = cpu_to_le32(0x00000000);
> @@ -1198,23 +1231,28 @@ int amdgpu_uvd_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
> for (i = 11; i < 1024; ++i)
> msg[i] = cpu_to_le32(0x0);
>
> - return amdgpu_uvd_send_msg(ring, bo, true, fence);
> + r = amdgpu_uvd_send_msg(ring, bo, true, fence);
> +
> + amdgpu_bo_unreserve(bo);
> + return r;
> }
>
> int amdgpu_uvd_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
> bool direct, struct dma_fence **fence)
> {
> struct amdgpu_device *adev = ring->adev;
> - struct amdgpu_bo *bo = NULL;
> + struct amdgpu_bo *bo = adev->uvd.ib_bo;
That won't work. To make the allocation work bo must be NULL when
amdgpu_uvd_create_msg_bo_helper() is called.
Probably best to add an "*bo = NULL" to amdgpu_uvd_create_msg_bo_helper().
Regards,
Christian.
> uint32_t *msg;
> int r, i;
>
> - r = amdgpu_bo_create_reserved(adev, 1024, PAGE_SIZE,
> - AMDGPU_GEM_DOMAIN_GTT,
> - &bo, NULL, (void **)&msg);
> + if (direct)
> + r = WARN_ON_ONCE(ttm_bo_reserve(&bo->tbo, true, true, NULL));
> + else
> + r = amdgpu_uvd_create_msg_bo_helper(adev, 4096, &bo);
> if (r)
> return r;
>
> + msg = amdgpu_bo_kptr(bo);
> /* stitch together an UVD destroy msg */
> msg[0] = cpu_to_le32(0x00000de4);
> msg[1] = cpu_to_le32(0x00000002);
> @@ -1223,7 +1261,13 @@ int amdgpu_uvd_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
> for (i = 4; i < 1024; ++i)
> msg[i] = cpu_to_le32(0x0);
>
> - return amdgpu_uvd_send_msg(ring, bo, direct, fence);
> + r = amdgpu_uvd_send_msg(ring, bo, direct, fence);
> +
> + amdgpu_bo_unreserve(bo);
> + if (!direct)
> + amdgpu_bo_free_kernel(&bo, NULL, (void **)&msg);
> +
> + return r;
> }
>
> static void amdgpu_uvd_idle_work_handler(struct work_struct *work)
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.h
> index edbb8194ee81..76ac9699885d 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.h
> @@ -68,6 +68,7 @@ struct amdgpu_uvd {
> /* store image width to adjust nb memory state */
> unsigned decode_image_width;
> uint32_t keyselect;
> + struct amdgpu_bo *ib_bo;
> };
>
> int amdgpu_uvd_sw_init(struct amdgpu_device *adev);
> diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
> index bc571833632e..dd92d96dd5a2 100644
> --- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
> @@ -332,12 +332,10 @@ static int uvd_v6_0_enc_get_destroy_msg(struct amdgpu_ring *ring,
> static int uvd_v6_0_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout)
> {
> struct dma_fence *fence = NULL;
> - struct amdgpu_bo *bo = NULL;
> + struct amdgpu_bo *bo = ring->adev->uvd.ib_bo;
> long r;
>
> - r = amdgpu_bo_create_reserved(ring->adev, 128 * 1024, PAGE_SIZE,
> - AMDGPU_GEM_DOMAIN_VRAM,
> - &bo, NULL, NULL);
> + r = WARN_ON_ONCE(ttm_bo_reserve(&bo->tbo, true, true, NULL));
> if (r)
> return r;
>
> @@ -357,9 +355,7 @@ static int uvd_v6_0_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout)
>
> error:
> dma_fence_put(fence);
> - amdgpu_bo_unpin(bo);
> amdgpu_bo_unreserve(bo);
> - amdgpu_bo_unref(&bo);
> return r;
> }
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
> index b6e82d75561f..271122cf2237 100644
> --- a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
> @@ -338,12 +338,10 @@ static int uvd_v7_0_enc_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handl
> static int uvd_v7_0_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout)
> {
> struct dma_fence *fence = NULL;
> - struct amdgpu_bo *bo = NULL;
> + struct amdgpu_bo *bo = ring->adev->uvd.ib_bo;
> long r;
>
> - r = amdgpu_bo_create_reserved(ring->adev, 128 * 1024, PAGE_SIZE,
> - AMDGPU_GEM_DOMAIN_VRAM,
> - &bo, NULL, NULL);
> + r = WARN_ON_ONCE(ttm_bo_reserve(&bo->tbo, true, true, NULL));
> if (r)
> return r;
>
> @@ -363,9 +361,7 @@ static int uvd_v7_0_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout)
>
> error:
> dma_fence_put(fence);
> - amdgpu_bo_unpin(bo);
> amdgpu_bo_unreserve(bo);
> - amdgpu_bo_unref(&bo);
> return r;
> }
>
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: 回复: [PATCH v3 1/3] drm/amdgpu: UVD avoid memory allocation during IB test
2021-09-13 6:51 ` 回复: " Pan, Xinhui
@ 2021-09-13 6:52 ` Christian König
0 siblings, 0 replies; 6+ messages in thread
From: Christian König @ 2021-09-13 6:52 UTC (permalink / raw)
To: Pan, Xinhui, Koenig, Christian, amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander
Ah, missed the local variable in amdgpu_uvd_create_msg_bo_helper().
Please add a comment on that.
Apart from that looks good to me.
Regards,
Christian.
Am 13.09.21 um 08:51 schrieb Pan, Xinhui:
> [AMD Official Use Only]
>
> 1) Of cource I can drop the bo resv lock as long as we fix the race of IB test. will do it in v4
>
> 2) amdgpu_uvd_create_msg_bo_helper always use a local variable *bo = NULL passed to bo_create. and assiged it to **bo_ptr on success. Of cource, I will make code easier to understand.
>
> ________________________________________
> 发件人: Koenig, Christian <Christian.Koenig@amd.com>
> 发送时间: 2021年9月13日 14:31
> 收件人: Pan, Xinhui; amd-gfx@lists.freedesktop.org
> 抄送: Deucher, Alexander
> 主题: Re: [PATCH v3 1/3] drm/amdgpu: UVD avoid memory allocation during IB test
>
> Am 11.09.21 um 03:34 schrieb xinhui pan:
>> move BO allocation in sw_init.
>>
>> Signed-off-by: xinhui pan <xinhui.pan@amd.com>
>> ---
>> change from v2:
>> use reservation trylock for direct IB test.
>> change from v1:
>> only use pre-allocated BO for direct IB submission.
>> and take its reservation lock to avoid any potential race.
>> better safe than sorry.
>> ---
>> drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c | 104 +++++++++++++++++-------
>> drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.h | 1 +
>> drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 8 +-
>> drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c | 8 +-
>> 4 files changed, 79 insertions(+), 42 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
>> index d451c359606a..a4b3dd6b38c6 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
>> @@ -134,6 +134,51 @@ MODULE_FIRMWARE(FIRMWARE_VEGA12);
>> MODULE_FIRMWARE(FIRMWARE_VEGA20);
>>
>> static void amdgpu_uvd_idle_work_handler(struct work_struct *work);
>> +static void amdgpu_uvd_force_into_uvd_segment(struct amdgpu_bo *abo);
>> +
>> +static int amdgpu_uvd_create_msg_bo_helper(struct amdgpu_device *adev,
>> + uint32_t size,
>> + struct amdgpu_bo **bo_ptr)
>> +{
>> + struct ttm_operation_ctx ctx = { true, false };
>> + struct amdgpu_bo *bo = NULL;
>> + void *addr;
>> + int r;
>> +
>> + r = amdgpu_bo_create_reserved(adev, size, PAGE_SIZE,
>> + AMDGPU_GEM_DOMAIN_GTT,
>> + &bo, NULL, &addr);
>> + if (r)
>> + return r;
>> +
>> + if (adev->uvd.address_64_bit) {
>> + *bo_ptr = bo;
>> + return 0;
>> + }
>> +
>> + amdgpu_bo_kunmap(bo);
>> + amdgpu_bo_unpin(bo);
>> + amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_VRAM);
>> + amdgpu_uvd_force_into_uvd_segment(bo);
>> + r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
>> + if (r)
>> + goto err;
>> + r = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_VRAM);
>> + if (r)
>> + goto err_pin;
>> + r = amdgpu_bo_kmap(bo, &addr);
>> + if (r)
>> + goto err_kmap;
>> + *bo_ptr = bo;
>> + return 0;
>> +err_kmap:
>> + amdgpu_bo_unpin(bo);
>> +err_pin:
>> +err:
>> + amdgpu_bo_unreserve(bo);
>> + amdgpu_bo_unref(&bo);
>> + return r;
>> +}
>>
>> int amdgpu_uvd_sw_init(struct amdgpu_device *adev)
>> {
>> @@ -302,6 +347,11 @@ int amdgpu_uvd_sw_init(struct amdgpu_device *adev)
>> if (!amdgpu_device_ip_block_version_cmp(adev, AMD_IP_BLOCK_TYPE_UVD, 5, 0))
>> adev->uvd.address_64_bit = true;
>>
>> + r = amdgpu_uvd_create_msg_bo_helper(adev, 128 << 10, &adev->uvd.ib_bo);
>> + if (r)
>> + return r;
>> + amdgpu_bo_unreserve(adev->uvd.ib_bo);
>> +
>> switch (adev->asic_type) {
>> case CHIP_TONGA:
>> adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_65_10;
>> @@ -324,6 +374,7 @@ int amdgpu_uvd_sw_init(struct amdgpu_device *adev)
>>
>> int amdgpu_uvd_sw_fini(struct amdgpu_device *adev)
>> {
>> + void *addr = amdgpu_bo_kptr(adev->uvd.ib_bo);
>> int i, j;
>>
>> drm_sched_entity_destroy(&adev->uvd.entity);
>> @@ -342,6 +393,7 @@ int amdgpu_uvd_sw_fini(struct amdgpu_device *adev)
>> for (i = 0; i < AMDGPU_MAX_UVD_ENC_RINGS; ++i)
>> amdgpu_ring_fini(&adev->uvd.inst[j].ring_enc[i]);
>> }
>> + amdgpu_bo_free_kernel(&adev->uvd.ib_bo, NULL, &addr);
>> release_firmware(adev->uvd.fw);
>>
>> return 0;
>> @@ -1080,23 +1132,10 @@ static int amdgpu_uvd_send_msg(struct amdgpu_ring *ring, struct amdgpu_bo *bo,
>> unsigned offset_idx = 0;
>> unsigned offset[3] = { UVD_BASE_SI, 0, 0 };
>>
>> - amdgpu_bo_kunmap(bo);
>> - amdgpu_bo_unpin(bo);
>> -
>> - if (!ring->adev->uvd.address_64_bit) {
>> - struct ttm_operation_ctx ctx = { true, false };
>> -
>> - amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_VRAM);
>> - amdgpu_uvd_force_into_uvd_segment(bo);
>> - r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
>> - if (r)
>> - goto err;
>> - }
>> -
>> r = amdgpu_job_alloc_with_ib(adev, 64, direct ? AMDGPU_IB_POOL_DIRECT :
>> AMDGPU_IB_POOL_DELAYED, &job);
>> if (r)
>> - goto err;
>> + return r;
>>
>> if (adev->asic_type >= CHIP_VEGA10) {
>> offset_idx = 1 + ring->me;
>> @@ -1148,8 +1187,6 @@ static int amdgpu_uvd_send_msg(struct amdgpu_ring *ring, struct amdgpu_bo *bo,
>> }
>>
>> amdgpu_bo_fence(bo, f, false);
>> - amdgpu_bo_unreserve(bo);
>> - amdgpu_bo_unref(&bo);
>>
>> if (fence)
>> *fence = dma_fence_get(f);
>> @@ -1159,10 +1196,6 @@ static int amdgpu_uvd_send_msg(struct amdgpu_ring *ring, struct amdgpu_bo *bo,
>>
>> err_free:
>> amdgpu_job_free(job);
>> -
>> -err:
>> - amdgpu_bo_unreserve(bo);
>> - amdgpu_bo_unref(&bo);
>> return r;
>> }
>>
>> @@ -1173,16 +1206,16 @@ int amdgpu_uvd_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
>> struct dma_fence **fence)
>> {
>> struct amdgpu_device *adev = ring->adev;
>> - struct amdgpu_bo *bo = NULL;
>> + struct amdgpu_bo *bo = adev->uvd.ib_bo;
>> uint32_t *msg;
>> int r, i;
>>
>> - r = amdgpu_bo_create_reserved(adev, 1024, PAGE_SIZE,
>> - AMDGPU_GEM_DOMAIN_GTT,
>> - &bo, NULL, (void **)&msg);
>> + /* Direct IB submission should be exclusive. */
>> + r = WARN_ON_ONCE(ttm_bo_reserve(&bo->tbo, true, true, NULL));
> Please just completely drop taking the reservation for direct
> submission. I don't want lockdep to complain about that.
>
>> if (r)
>> return r;
>>
>> + msg = amdgpu_bo_kptr(bo);
>> /* stitch together an UVD create msg */
>> msg[0] = cpu_to_le32(0x00000de4);
>> msg[1] = cpu_to_le32(0x00000000);
>> @@ -1198,23 +1231,28 @@ int amdgpu_uvd_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
>> for (i = 11; i < 1024; ++i)
>> msg[i] = cpu_to_le32(0x0);
>>
>> - return amdgpu_uvd_send_msg(ring, bo, true, fence);
>> + r = amdgpu_uvd_send_msg(ring, bo, true, fence);
>> +
>> + amdgpu_bo_unreserve(bo);
>> + return r;
>> }
>>
>> int amdgpu_uvd_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
>> bool direct, struct dma_fence **fence)
>> {
>> struct amdgpu_device *adev = ring->adev;
>> - struct amdgpu_bo *bo = NULL;
>> + struct amdgpu_bo *bo = adev->uvd.ib_bo;
> That won't work. To make the allocation work bo must be NULL when
> amdgpu_uvd_create_msg_bo_helper() is called.
>
> Probably best to add an "*bo = NULL" to amdgpu_uvd_create_msg_bo_helper().
>
> Regards,
> Christian.
>
>> uint32_t *msg;
>> int r, i;
>>
>> - r = amdgpu_bo_create_reserved(adev, 1024, PAGE_SIZE,
>> - AMDGPU_GEM_DOMAIN_GTT,
>> - &bo, NULL, (void **)&msg);
>> + if (direct)
>> + r = WARN_ON_ONCE(ttm_bo_reserve(&bo->tbo, true, true, NULL));
>> + else
>> + r = amdgpu_uvd_create_msg_bo_helper(adev, 4096, &bo);
>> if (r)
>> return r;
>>
>> + msg = amdgpu_bo_kptr(bo);
>> /* stitch together an UVD destroy msg */
>> msg[0] = cpu_to_le32(0x00000de4);
>> msg[1] = cpu_to_le32(0x00000002);
>> @@ -1223,7 +1261,13 @@ int amdgpu_uvd_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
>> for (i = 4; i < 1024; ++i)
>> msg[i] = cpu_to_le32(0x0);
>>
>> - return amdgpu_uvd_send_msg(ring, bo, direct, fence);
>> + r = amdgpu_uvd_send_msg(ring, bo, direct, fence);
>> +
>> + amdgpu_bo_unreserve(bo);
>> + if (!direct)
>> + amdgpu_bo_free_kernel(&bo, NULL, (void **)&msg);
>> +
>> + return r;
>> }
>>
>> static void amdgpu_uvd_idle_work_handler(struct work_struct *work)
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.h
>> index edbb8194ee81..76ac9699885d 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.h
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.h
>> @@ -68,6 +68,7 @@ struct amdgpu_uvd {
>> /* store image width to adjust nb memory state */
>> unsigned decode_image_width;
>> uint32_t keyselect;
>> + struct amdgpu_bo *ib_bo;
>> };
>>
>> int amdgpu_uvd_sw_init(struct amdgpu_device *adev);
>> diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
>> index bc571833632e..dd92d96dd5a2 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
>> @@ -332,12 +332,10 @@ static int uvd_v6_0_enc_get_destroy_msg(struct amdgpu_ring *ring,
>> static int uvd_v6_0_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout)
>> {
>> struct dma_fence *fence = NULL;
>> - struct amdgpu_bo *bo = NULL;
>> + struct amdgpu_bo *bo = ring->adev->uvd.ib_bo;
>> long r;
>>
>> - r = amdgpu_bo_create_reserved(ring->adev, 128 * 1024, PAGE_SIZE,
>> - AMDGPU_GEM_DOMAIN_VRAM,
>> - &bo, NULL, NULL);
>> + r = WARN_ON_ONCE(ttm_bo_reserve(&bo->tbo, true, true, NULL));
>> if (r)
>> return r;
>>
>> @@ -357,9 +355,7 @@ static int uvd_v6_0_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout)
>>
>> error:
>> dma_fence_put(fence);
>> - amdgpu_bo_unpin(bo);
>> amdgpu_bo_unreserve(bo);
>> - amdgpu_bo_unref(&bo);
>> return r;
>> }
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
>> index b6e82d75561f..271122cf2237 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
>> @@ -338,12 +338,10 @@ static int uvd_v7_0_enc_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handl
>> static int uvd_v7_0_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout)
>> {
>> struct dma_fence *fence = NULL;
>> - struct amdgpu_bo *bo = NULL;
>> + struct amdgpu_bo *bo = ring->adev->uvd.ib_bo;
>> long r;
>>
>> - r = amdgpu_bo_create_reserved(ring->adev, 128 * 1024, PAGE_SIZE,
>> - AMDGPU_GEM_DOMAIN_VRAM,
>> - &bo, NULL, NULL);
>> + r = WARN_ON_ONCE(ttm_bo_reserve(&bo->tbo, true, true, NULL));
>> if (r)
>> return r;
>>
>> @@ -363,9 +361,7 @@ static int uvd_v7_0_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout)
>>
>> error:
>> dma_fence_put(fence);
>> - amdgpu_bo_unpin(bo);
>> amdgpu_bo_unreserve(bo);
>> - amdgpu_bo_unref(&bo);
>> return r;
>> }
>>
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2021-09-13 6:52 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz follow: Atom feed
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2021-09-11 1:34 [PATCH v3 1/3] drm/amdgpu: UVD avoid memory allocation during IB test xinhui pan
2021-09-11 1:34 ` [PATCH v3 2/3] drm/amdgpu: VCE " xinhui pan
2021-09-11 1:34 ` [PATCH v3 3/3] drm/amdgpu: VCN " xinhui pan
2021-09-13 6:31 ` [PATCH v3 1/3] drm/amdgpu: UVD " Christian König
2021-09-13 6:51 ` 回复: " Pan, Xinhui
2021-09-13 6:52 ` Christian König
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