[PATCH 1/2] Revert "drm/amd/display: disable SubVP + DRR to prevent underflow"

[PATCH 1/2] Revert "drm/amd/display: disable SubVP + DRR to prevent underflow"

[Aurabindo Pillai]

This reverts commit 541908cc2cca427fc3ae3bd4c9b82797a78e63a9.
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c    | 5 -----
 drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c | 4 ----
 drivers/gpu/drm/amd/include/amd_shared.h             | 1 -
 3 files changed, 10 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index e1565126ad2a..81206f67b993 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -1645,11 +1645,6 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
 	if (amdgpu_dc_feature_mask & DC_DISABLE_LTTPR_DP2_0)
 		init_data.flags.allow_lttpr_non_transparent_mode.bits.DP2_0 = true;
 
-	/* Disable SubVP + DRR config by default */
-	init_data.flags.disable_subvp_drr = true;
-	if (amdgpu_dc_feature_mask & DC_ENABLE_SUBVP_DRR)
-		init_data.flags.disable_subvp_drr = false;
-
 	init_data.flags.seamless_boot_edp_requested = false;
 
 	if (check_seamless_boot_capability(adev)) {
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
index b8a2518faecc..d7749260e1d9 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
@@ -880,10 +880,6 @@ static bool subvp_drr_schedulable(struct dc *dc, struct dc_state *context, struc
 	int16_t stretched_drr_us = 0;
 	int16_t drr_stretched_vblank_us = 0;
 	int16_t max_vblank_mallregion = 0;
-	const struct dc_config *config = &dc->config;
-
-	if (config->disable_subvp_drr)
-		return false;
 
 	// Find SubVP pipe
 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
diff --git a/drivers/gpu/drm/amd/include/amd_shared.h b/drivers/gpu/drm/amd/include/amd_shared.h
index e4a22c68517d..f175e65b853a 100644
--- a/drivers/gpu/drm/amd/include/amd_shared.h
+++ b/drivers/gpu/drm/amd/include/amd_shared.h
@@ -240,7 +240,6 @@ enum DC_FEATURE_MASK {
 	DC_DISABLE_LTTPR_DP2_0 = (1 << 6), //0x40, disabled by default
 	DC_PSR_ALLOW_SMU_OPT = (1 << 7), //0x80, disabled by default
 	DC_PSR_ALLOW_MULTI_DISP_OPT = (1 << 8), //0x100, disabled by default
-	DC_ENABLE_SUBVP_DRR = (1 << 9), // 0x200, disabled by default
 };
 
 enum DC_DEBUG_MASK {
-- 
2.39.2

[PATCH 2/2] drm/amd/display: Program OTG vtotal min/max selectors unconditionally

[Aurabindo Pillai]

[Why&How]

OTG_V_TOTAL_MIN/MAX_SEL bits are required to be programmed to 1 if
writes to OTG timing registers need to be honoured. This is usually
needed only when freesync is active. However, SubVP + DRR requires that
we're able to change timing even without freesync being active (but
supported). By unconditionally writing this bit to 1, we remove an
unnecessary dependency so that DMCUB can change OTG timing whenever it wants.

Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.c | 11 ++---------
 1 file changed, 2 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.c
index 2ee798965bc2..6ef56fb32131 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.c
@@ -245,16 +245,9 @@ static void optc32_set_drr(
 		}
 
 		optc->funcs->set_vtotal_min_max(optc, params->vertical_total_min - 1, params->vertical_total_max - 1);
-		optc32_setup_manual_trigger(optc);
-	} else {
-		REG_UPDATE_4(OTG_V_TOTAL_CONTROL,
-				OTG_SET_V_TOTAL_MIN_MASK, 0,
-				OTG_V_TOTAL_MIN_SEL, 0,
-				OTG_V_TOTAL_MAX_SEL, 0,
-				OTG_FORCE_LOCK_ON_EVENT, 0);
-
-		optc->funcs->set_vtotal_min_max(optc, 0, 0);
 	}
+
+	optc32_setup_manual_trigger(optc);
 }
 
 static struct timing_generator_funcs dcn32_tg_funcs = {
-- 
2.39.2

Re: [PATCH 1/2] Revert "drm/amd/display: disable SubVP + DRR to prevent underflow"

[Rodrigo Siqueira Jordao]

On 4/21/23 14:39, Aurabindo Pillai wrote:
> This reverts commit 541908cc2cca427fc3ae3bd4c9b82797a78e63a9.

Hi,

Please add an explanation of the reason why we want to revert this patch.

With that change:
Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>

Thanks
Siqueira

> ---
>   drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c    | 5 -----
>   drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c | 4 ----
>   drivers/gpu/drm/amd/include/amd_shared.h             | 1 -
>   3 files changed, 10 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> index e1565126ad2a..81206f67b993 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> @@ -1645,11 +1645,6 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
>   	if (amdgpu_dc_feature_mask & DC_DISABLE_LTTPR_DP2_0)
>   		init_data.flags.allow_lttpr_non_transparent_mode.bits.DP2_0 = true;
>   
> -	/* Disable SubVP + DRR config by default */
> -	init_data.flags.disable_subvp_drr = true;
> -	if (amdgpu_dc_feature_mask & DC_ENABLE_SUBVP_DRR)
> -		init_data.flags.disable_subvp_drr = false;
> -
>   	init_data.flags.seamless_boot_edp_requested = false;
>   
>   	if (check_seamless_boot_capability(adev)) {
> diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
> index b8a2518faecc..d7749260e1d9 100644
> --- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
> +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
> @@ -880,10 +880,6 @@ static bool subvp_drr_schedulable(struct dc *dc, struct dc_state *context, struc
>   	int16_t stretched_drr_us = 0;
>   	int16_t drr_stretched_vblank_us = 0;
>   	int16_t max_vblank_mallregion = 0;
> -	const struct dc_config *config = &dc->config;
> -
> -	if (config->disable_subvp_drr)
> -		return false;
>   
>   	// Find SubVP pipe
>   	for (i = 0; i < dc->res_pool->pipe_count; i++) {
> diff --git a/drivers/gpu/drm/amd/include/amd_shared.h b/drivers/gpu/drm/amd/include/amd_shared.h
> index e4a22c68517d..f175e65b853a 100644
> --- a/drivers/gpu/drm/amd/include/amd_shared.h
> +++ b/drivers/gpu/drm/amd/include/amd_shared.h
> @@ -240,7 +240,6 @@ enum DC_FEATURE_MASK {
>   	DC_DISABLE_LTTPR_DP2_0 = (1 << 6), //0x40, disabled by default
>   	DC_PSR_ALLOW_SMU_OPT = (1 << 7), //0x80, disabled by default
>   	DC_PSR_ALLOW_MULTI_DISP_OPT = (1 << 8), //0x100, disabled by default
> -	DC_ENABLE_SUBVP_DRR = (1 << 9), // 0x200, disabled by default
>   };
>   
>   enum DC_DEBUG_MASK {

Re: [PATCH 2/2] drm/amd/display: Program OTG vtotal min/max selectors unconditionally

[Rodrigo Siqueira Jordao]

On 4/21/23 14:39, Aurabindo Pillai wrote:
> [Why&How]

Drop the above line, with that:

Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>

> 
> OTG_V_TOTAL_MIN/MAX_SEL bits are required to be programmed to 1 if
> writes to OTG timing registers need to be honoured. This is usually
> needed only when freesync is active. However, SubVP + DRR requires that
> we're able to change timing even without freesync being active (but
> supported). By unconditionally writing this bit to 1, we remove an
> unnecessary dependency so that DMCUB can change OTG timing whenever it wants.
> 
> Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
> ---
>   drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.c | 11 ++---------
>   1 file changed, 2 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.c
> index 2ee798965bc2..6ef56fb32131 100644
> --- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.c
> +++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.c
> @@ -245,16 +245,9 @@ static void optc32_set_drr(
>   		}
>   
>   		optc->funcs->set_vtotal_min_max(optc, params->vertical_total_min - 1, params->vertical_total_max - 1);
> -		optc32_setup_manual_trigger(optc);
> -	} else {
> -		REG_UPDATE_4(OTG_V_TOTAL_CONTROL,
> -				OTG_SET_V_TOTAL_MIN_MASK, 0,
> -				OTG_V_TOTAL_MIN_SEL, 0,
> -				OTG_V_TOTAL_MAX_SEL, 0,
> -				OTG_FORCE_LOCK_ON_EVENT, 0);
> -
> -		optc->funcs->set_vtotal_min_max(optc, 0, 0);
>   	}
> +
> +	optc32_setup_manual_trigger(optc);
>   }
>   
>   static struct timing_generator_funcs dcn32_tg_funcs = {