From: Steven Price <steven.price@arm.com>
To: Boris Brezillon <boris.brezillon@collabora.com>
Cc: dri-devel@lists.freedesktop.org,
"Maarten Lankhorst" <maarten.lankhorst@linux.intel.com>,
"Maxime Ripard" <mripard@kernel.org>,
"Thomas Zimmermann" <tzimmermann@suse.de>,
"David Airlie" <airlied@gmail.com>,
"Simona Vetter" <simona@ffwll.ch>,
"Faith Ekstrand" <faith.ekstrand@collabora.com>,
"Thierry Reding" <thierry.reding@gmail.com>,
"Mikko Perttunen" <mperttunen@nvidia.com>,
"Melissa Wen" <mwen@igalia.com>,
"Maíra Canal" <mcanal@igalia.com>,
"Lucas De Marchi" <lucas.demarchi@intel.com>,
"Thomas Hellström" <thomas.hellstrom@linux.intel.com>,
"Rodrigo Vivi" <rodrigo.vivi@intel.com>,
"Frank Binns" <frank.binns@imgtec.com>,
"Matt Coster" <matt.coster@imgtec.com>,
"Rob Clark" <robin.clark@oss.qualcomm.com>,
"Dmitry Baryshkov" <lumag@kernel.org>,
"Abhinav Kumar" <abhinav.kumar@linux.dev>,
"Jessica Zhang" <jessica.zhang@oss.qualcomm.com>,
"Sean Paul" <sean@poorly.run>,
"Marijn Suijten" <marijn.suijten@somainline.org>,
"Alex Deucher" <alexander.deucher@amd.com>,
"Christian König" <christian.koenig@amd.com>,
amd-gfx@lists.freedesktop.org, kernel@collabora.com
Subject: Re: [PATCH v5 12/16] drm/panfrost: Expose the selected coherency protocol to the UMD
Date: Fri, 14 Nov 2025 16:19:53 +0000 [thread overview]
Message-ID: <6f1dbbbc-5eea-448a-9c12-a7f24294fe54@arm.com> (raw)
In-Reply-To: <20251030140525.366636-13-boris.brezillon@collabora.com>
On 30/10/2025 14:05, Boris Brezillon wrote:
> Will be needed if we want to skip CPU cache maintenance operations when
> the GPU can snoop CPU caches.
>
> v2:
> - New commit
>
> v3:
> - Fix the coherency values (enum instead of bitmask)
>
> v4:
> - Fix init/test on coherency_features
>
> v5:
> - No changes
>
> Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Steven Price <steven.price@arm.com>
> ---
> drivers/gpu/drm/panfrost/panfrost_device.h | 1 +
> drivers/gpu/drm/panfrost/panfrost_drv.c | 1 +
> drivers/gpu/drm/panfrost/panfrost_gpu.c | 26 +++++++++++++++++++---
> drivers/gpu/drm/panfrost/panfrost_regs.h | 10 +++++++--
> include/uapi/drm/panfrost_drm.h | 7 ++++++
> 5 files changed, 40 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/panfrost/panfrost_device.h b/drivers/gpu/drm/panfrost/panfrost_device.h
> index e61c4329fd07..0f3992412205 100644
> --- a/drivers/gpu/drm/panfrost/panfrost_device.h
> +++ b/drivers/gpu/drm/panfrost/panfrost_device.h
> @@ -79,6 +79,7 @@ struct panfrost_features {
> u32 thread_max_workgroup_sz;
> u32 thread_max_barrier_sz;
> u32 coherency_features;
> + u32 selected_coherency;
> u32 afbc_features;
> u32 texture_features[4];
> u32 js_features[16];
> diff --git a/drivers/gpu/drm/panfrost/panfrost_drv.c b/drivers/gpu/drm/panfrost/panfrost_drv.c
> index e3cdc0c95a56..6c08a4907eea 100644
> --- a/drivers/gpu/drm/panfrost/panfrost_drv.c
> +++ b/drivers/gpu/drm/panfrost/panfrost_drv.c
> @@ -94,6 +94,7 @@ static int panfrost_ioctl_get_param(struct drm_device *ddev, void *data, struct
> PANFROST_FEATURE_ARRAY(JS_FEATURES, js_features, 15);
> PANFROST_FEATURE(NR_CORE_GROUPS, nr_core_groups);
> PANFROST_FEATURE(THREAD_TLS_ALLOC, thread_tls_alloc);
> + PANFROST_FEATURE(SELECTED_COHERENCY, selected_coherency);
>
> case DRM_PANFROST_PARAM_SYSTEM_TIMESTAMP:
> ret = panfrost_ioctl_query_timestamp(pfdev, ¶m->value);
> diff --git a/drivers/gpu/drm/panfrost/panfrost_gpu.c b/drivers/gpu/drm/panfrost/panfrost_gpu.c
> index 8d049a07d393..59e3f25b2dc2 100644
> --- a/drivers/gpu/drm/panfrost/panfrost_gpu.c
> +++ b/drivers/gpu/drm/panfrost/panfrost_gpu.c
> @@ -157,8 +157,8 @@ static void panfrost_gpu_init_quirks(struct panfrost_device *pfdev)
> pfdev->features.revision >= 0x2000)
> quirks |= JM_MAX_JOB_THROTTLE_LIMIT << JM_JOB_THROTTLE_LIMIT_SHIFT;
> else if (panfrost_model_eq(pfdev, 0x6000) &&
> - pfdev->features.coherency_features == COHERENCY_ACE)
> - quirks |= (COHERENCY_ACE_LITE | COHERENCY_ACE) <<
> + pfdev->features.coherency_features == BIT(COHERENCY_ACE))
> + quirks |= (BIT(COHERENCY_ACE_LITE) | BIT(COHERENCY_ACE)) <<
> JM_FORCE_COHERENCY_FEATURES_SHIFT;
Interestingly it appears kbase had a bug here with BIT() confusion[1]! I
did give this a run on my HiKey960 and didn't immediately notice any
issues. So hopefully we're fine.
Thanks,
Steve
[1]
https://android.googlesource.com/kernel/google-modules/gpu/+/refs/heads/android-gs-raviole-5.10-android13/mali_kbase/backend/gpu/mali_kbase_pm_driver.c#2630
>
> if (panfrost_has_hw_feature(pfdev, HW_FEATURE_IDVS_GROUP_SIZE))
> @@ -261,7 +261,27 @@ static int panfrost_gpu_init_features(struct panfrost_device *pfdev)
> pfdev->features.max_threads = gpu_read(pfdev, GPU_THREAD_MAX_THREADS);
> pfdev->features.thread_max_workgroup_sz = gpu_read(pfdev, GPU_THREAD_MAX_WORKGROUP_SIZE);
> pfdev->features.thread_max_barrier_sz = gpu_read(pfdev, GPU_THREAD_MAX_BARRIER_SIZE);
> - pfdev->features.coherency_features = gpu_read(pfdev, GPU_COHERENCY_FEATURES);
> +
> + if (panfrost_has_hw_feature(pfdev, HW_FEATURE_COHERENCY_REG))
> + pfdev->features.coherency_features = gpu_read(pfdev, GPU_COHERENCY_FEATURES);
> + else
> + pfdev->features.coherency_features = BIT(COHERENCY_ACE_LITE);
> +
> + BUILD_BUG_ON(COHERENCY_ACE_LITE != DRM_PANFROST_GPU_COHERENCY_ACE_LITE);
> + BUILD_BUG_ON(COHERENCY_ACE != DRM_PANFROST_GPU_COHERENCY_ACE);
> + BUILD_BUG_ON(COHERENCY_NONE != DRM_PANFROST_GPU_COHERENCY_NONE);
> +
> + if (!pfdev->coherent) {
> + pfdev->features.selected_coherency = COHERENCY_NONE;
> + } else if (pfdev->features.coherency_features & BIT(COHERENCY_ACE)) {
> + pfdev->features.selected_coherency = COHERENCY_ACE;
> + } else if (pfdev->features.coherency_features & BIT(COHERENCY_ACE_LITE)) {
> + pfdev->features.selected_coherency = COHERENCY_ACE_LITE;
> + } else {
> + drm_WARN(&pfdev->base, true, "No known coherency protocol supported");
> + pfdev->features.selected_coherency = COHERENCY_NONE;
> + }
> +
> pfdev->features.afbc_features = gpu_read(pfdev, GPU_AFBC_FEATURES);
> for (i = 0; i < 4; i++)
> pfdev->features.texture_features[i] = gpu_read(pfdev, GPU_TEXTURE_FEATURES(i));
> diff --git a/drivers/gpu/drm/panfrost/panfrost_regs.h b/drivers/gpu/drm/panfrost/panfrost_regs.h
> index 2b8f1617b836..ee15f6bf6e6f 100644
> --- a/drivers/gpu/drm/panfrost/panfrost_regs.h
> +++ b/drivers/gpu/drm/panfrost/panfrost_regs.h
> @@ -102,9 +102,15 @@
> #define GPU_L2_PRESENT_LO 0x120 /* (RO) Level 2 cache present bitmap, low word */
> #define GPU_L2_PRESENT_HI 0x124 /* (RO) Level 2 cache present bitmap, high word */
>
> +/* GPU_COHERENCY_FEATURES is a bitmask of BIT(COHERENCY_xxx) values encoding the
> + * set of supported coherency protocols. GPU_COHERENCY_ENABLE is passed a
> + * COHERENCY_xxx value.
> + */
> #define GPU_COHERENCY_FEATURES 0x300 /* (RO) Coherency features present */
> -#define COHERENCY_ACE_LITE BIT(0)
> -#define COHERENCY_ACE BIT(1)
> +#define GPU_COHERENCY_ENABLE 0x304 /* (RW) Coherency protocol selection */
> +#define COHERENCY_ACE_LITE 0
> +#define COHERENCY_ACE 1
> +#define COHERENCY_NONE 31
>
> #define GPU_STACK_PRESENT_LO 0xE00 /* (RO) Core stack present bitmap, low word */
> #define GPU_STACK_PRESENT_HI 0xE04 /* (RO) Core stack present bitmap, high word */
> diff --git a/include/uapi/drm/panfrost_drm.h b/include/uapi/drm/panfrost_drm.h
> index e8b47c9f6976..9bd8fa401400 100644
> --- a/include/uapi/drm/panfrost_drm.h
> +++ b/include/uapi/drm/panfrost_drm.h
> @@ -188,6 +188,13 @@ enum drm_panfrost_param {
> DRM_PANFROST_PARAM_SYSTEM_TIMESTAMP,
> DRM_PANFROST_PARAM_SYSTEM_TIMESTAMP_FREQUENCY,
> DRM_PANFROST_PARAM_ALLOWED_JM_CTX_PRIORITIES,
> + DRM_PANFROST_PARAM_SELECTED_COHERENCY,
> +};
> +
> +enum drm_panfrost_gpu_coherency {
> + DRM_PANFROST_GPU_COHERENCY_ACE_LITE = 0,
> + DRM_PANFROST_GPU_COHERENCY_ACE = 1,
> + DRM_PANFROST_GPU_COHERENCY_NONE = 31,
> };
>
> struct drm_panfrost_get_param {
next prev parent reply other threads:[~2025-11-14 16:20 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-30 14:05 [PATCH v5 00/16] drm/panfrost, panthor: Cached maps and explicit flushing Boris Brezillon
2025-10-30 14:05 ` [PATCH v5 01/16] drm/prime: Simplify life of drivers needing custom dma_buf_ops Boris Brezillon
2025-10-30 14:25 ` Christian König
2025-10-30 14:35 ` Boris Brezillon
2025-10-30 14:05 ` [PATCH v5 02/16] drm/shmem: Provide a generic {begin, end}_cpu_access() implementation Boris Brezillon
2025-10-30 14:31 ` [PATCH v5 02/16] drm/shmem: Provide a generic {begin,end}_cpu_access() implementation Christian König
2025-11-04 8:08 ` Boris Brezillon
2025-11-03 20:34 ` [PATCH v5 02/16] drm/shmem: Provide a generic {begin, end}_cpu_access() implementation Akash Goel
2025-11-04 7:42 ` Boris Brezillon
2025-10-30 14:05 ` [PATCH v5 03/16] drm/shmem: Add a drm_gem_shmem_sync() helper Boris Brezillon
2025-11-14 15:02 ` Steven Price
2025-10-30 14:05 ` [PATCH v5 04/16] drm/panthor: Provide a custom dma_buf implementation Boris Brezillon
2025-11-14 15:02 ` Steven Price
2025-10-30 14:05 ` [PATCH v5 05/16] drm/panthor: Fix panthor_gpu_coherency_set() Boris Brezillon
2025-10-30 14:05 ` [PATCH v5 06/16] drm/panthor: Expose the selected coherency protocol to the UMD Boris Brezillon
2025-10-30 14:05 ` [PATCH v5 07/16] drm/panthor: Add a PANTHOR_BO_SYNC ioctl Boris Brezillon
2025-10-31 7:25 ` Marcin Ślusarz
2025-11-03 20:42 ` Akash Goel
2025-11-04 7:41 ` Boris Brezillon
2025-10-30 14:05 ` [PATCH v5 08/16] drm/panthor: Add an ioctl to query BO flags Boris Brezillon
2025-10-30 14:05 ` [PATCH v5 09/16] drm/panthor: Add flag to map GEM object Write-Back Cacheable Boris Brezillon
2025-11-03 16:43 ` Akash Goel
2025-11-03 17:13 ` Boris Brezillon
2025-10-30 14:05 ` [PATCH v5 10/16] drm/panthor: Bump the driver version to 1.6 Boris Brezillon
2025-10-30 14:05 ` [PATCH v5 11/16] drm/panfrost: Provide a custom dma_buf implementation Boris Brezillon
2025-11-14 16:17 ` Steven Price
2025-10-30 14:05 ` [PATCH v5 12/16] drm/panfrost: Expose the selected coherency protocol to the UMD Boris Brezillon
2025-11-14 16:19 ` Steven Price [this message]
2025-10-30 14:05 ` [PATCH v5 13/16] drm/panfrost: Add a PANFROST_SYNC_BO ioctl Boris Brezillon
2025-10-31 7:08 ` Marcin Ślusarz
2025-10-31 8:49 ` Boris Brezillon
2025-10-30 14:05 ` [PATCH v5 14/16] drm/panfrost: Add an ioctl to query BO flags Boris Brezillon
2025-10-30 14:05 ` [PATCH v5 15/16] drm/panfrost: Add flag to map GEM object Write-Back Cacheable Boris Brezillon
2025-11-14 16:22 ` Steven Price
2025-10-30 14:05 ` [PATCH v5 16/16] drm/panfrost: Bump the driver version to 1.6 Boris Brezillon
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