From: Shashank Sharma <shashank.sharma@amd.com>
To: Alex Deucher <alexdeucher@gmail.com>
Cc: Alex Deucher <alexander.deucher@amd.com>,
arvind.yadav@amd.com, Christian Koenig <christian.koenig@amd.com>,
amd-gfx@lists.freedesktop.org, arunpravin.paneerselvam@amd.com
Subject: Re: [RFC 6/7] drm/amdgpu: Map userqueue into HW
Date: Tue, 3 Jan 2023 10:38:42 +0100 [thread overview]
Message-ID: <86a5e0fc-16c8-2c30-6849-67e6ae46b8f9@amd.com> (raw)
In-Reply-To: <CADnq5_MSrURbaNCN9+cjPAqoFoOPtLBXZPcP7hM_UFWJKKDyFw@mail.gmail.com>
On 29/12/2022 18:51, Alex Deucher wrote:
> On Fri, Dec 23, 2022 at 2:37 PM Shashank Sharma <shashank.sharma@amd.com> wrote:
>> This patch add the function to map/unmap the usermode queue into the HW,
>> using the prepared MQD and other objects. After this mapping, the queue
>> will be ready to accept the workload.
> This should also be a callback into IP specific code. It will be
> different for each IP type and version.
>
> Alex
Noted, so far we have two IP specific functions, .init_mqd() and .map()
- Shashank
>> Cc: Alex Deucher <alexander.deucher@amd.com>
>> Cc: Christian Koenig <christian.koenig@amd.com>
>>
>> Signed-off-by: Shashank Sharma <shashank.sharma@amd.com>
>> ---
>> drivers/gpu/drm/amd/amdgpu/amdgpu_userqueue.c | 71 +++++++++++++++++++
>> 1 file changed, 71 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userqueue.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_userqueue.c
>> index 2a854a5e2f70..b164e24247ca 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userqueue.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userqueue.c
>> @@ -50,6 +50,67 @@ amdgpu_userqueue_remove_index(struct amdgpu_device *adev, struct amdgpu_usermode
>> ida_simple_remove(&uqg->ida, queue->queue_id);
>> }
>>
>> +static int amdgpu_userqueue_map(struct amdgpu_device *adev,
>> + struct amdgpu_usermode_queue *queue)
>> +{
>> + int r;
>> + struct mes_add_queue_input queue_input;
>> +
>> + memset(&queue_input, 0x0, sizeof(struct mes_add_queue_input));
>> +
>> + queue_input.process_va_start = 0;
>> + queue_input.process_va_end = adev->vm_manager.max_pfn - 1;
>> + queue_input.process_quantum = 100000; /* 10ms */
>> + queue_input.gang_quantum = 10000; /* 1ms */
>> + queue_input.paging = false;
>> +
>> + queue_input.gang_context_addr = queue->gang_ctx.gpu_addr;
>> + queue_input.process_context_addr = queue->proc_ctx.gpu_addr;
>> + queue_input.inprocess_gang_priority = AMDGPU_MES_PRIORITY_LEVEL_NORMAL;
>> + queue_input.gang_global_priority_level = AMDGPU_MES_PRIORITY_LEVEL_NORMAL;
>> +
>> + queue_input.process_id = queue->pasid;
>> + queue_input.queue_type = queue->queue_type;
>> + queue_input.mqd_addr = queue->mqd_gpu_addr;
>> + queue_input.wptr_addr = queue->wptr_gpu_addr;
>> + queue_input.queue_size = queue->queue_size >> 2;
>> + queue_input.doorbell_offset = queue->doorbell_index;
>> + queue_input.page_table_base_addr = queue->vm->pd_phys_addr;
>> +
>> + amdgpu_mes_lock(&adev->mes);
>> + r = adev->mes.funcs->add_hw_queue(&adev->mes, &queue_input);
>> + amdgpu_mes_unlock(&adev->mes);
>> + if (r) {
>> + DRM_ERROR("Failed to map queue in HW, err (%d)\n", r);
>> + return r;
>> + }
>> +
>> + DRM_DEBUG_DRIVER("Queue %d mapped successfully\n", queue->queue_id);
>> + return 0;
>> +}
>> +
>> +static void amdgpu_userqueue_unmap(struct amdgpu_device *adev,
>> + struct amdgpu_usermode_queue *queue)
>> +{
>> + int r;
>> + struct mes_remove_queue_input queue_input;
>> +
>> + memset(&queue_input, 0x0, sizeof(struct mes_remove_queue_input));
>> + queue_input.doorbell_offset = queue->doorbell_index;
>> + queue_input.gang_context_addr = queue->gang_ctx.gpu_addr;
>> +
>> + amdgpu_mes_lock(&adev->mes);
>> + r = adev->mes.funcs->remove_hw_queue(&adev->mes, &queue_input);
>> + amdgpu_mes_unlock(&adev->mes);
>> +
>> + if (r) {
>> + DRM_ERROR("Failed to unmap usermode queue %d\n", queue->queue_id);
>> + return;
>> + }
>> +
>> + DRM_DEBUG_DRIVER("Usermode queue %d unmapped\n", queue->queue_id);
>> +}
>> +
>> static int
>> amdgpu_userqueue_get_doorbell(struct amdgpu_device *adev,
>> struct amdgpu_usermode_queue *queue)
>> @@ -338,12 +399,21 @@ int amdgpu_userqueue_create(struct amdgpu_device *adev, struct drm_file *filp,
>> goto free_mqd;
>> }
>>
>> + r = amdgpu_userqueue_map(adev, queue);
>> + if (r < 0) {
>> + DRM_ERROR("Failed to map queue\n");
>> + goto free_ctx;
>> + }
>> +
>> ctx->userq = queue;
>> args->out.q_id = queue->queue_id;
>> args->out.flags = 0;
>> mutex_unlock(&adev->userq.userq_mutex);
>> return 0;
>>
>> +free_ctx:
>> + amdgpu_userqueue_free_context(adev, queue);
>> +
>> free_mqd:
>> amdgpu_userqueue_destroy_mqd(queue);
>>
>> @@ -362,6 +432,7 @@ void amdgpu_userqueue_destroy(struct amdgpu_device *adev, struct drm_file *filp,
>> struct amdgpu_usermode_queue *queue = ctx->userq;
>>
>> mutex_lock(&adev->userq.userq_mutex);
>> + amdgpu_userqueue_unmap(adev, queue);
>> amdgpu_userqueue_free_context(adev, queue);
>> amdgpu_userqueue_destroy_mqd(queue);
>> amdgpu_userqueue_remove_index(adev, queue);
>> --
>> 2.34.1
>>
next prev parent reply other threads:[~2023-01-03 9:39 UTC|newest]
Thread overview: 64+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-12-23 19:36 [RFC 0/7] RFC: Usermode queue for AMDGPU driver Shashank Sharma
2022-12-23 19:36 ` [RFC 1/7] drm/amdgpu: UAPI for user queue management Shashank Sharma
2022-12-24 20:20 ` Bas Nieuwenhuizen
2022-12-27 16:58 ` Alex Deucher
2023-01-02 11:27 ` Christian König
2023-01-03 19:51 ` Alex Deucher
2023-01-02 13:26 ` Christian König
2023-01-03 14:23 ` Alex Deucher
2023-01-03 18:29 ` Felix Kuehling
2023-01-03 19:17 ` Liu, Shaoyun
2023-01-03 19:22 ` Alex Deucher
2023-01-03 19:25 ` Liu, Shaoyun
2023-01-03 19:52 ` Alex Deucher
2023-01-03 20:05 ` Felix Kuehling
2023-01-03 19:18 ` Alex Deucher
2022-12-23 19:36 ` [RFC 2/7] drm/amdgpu: Add usermode queue for gfx work Shashank Sharma
2022-12-24 18:19 ` Oded Gabbay
2022-12-26 10:34 ` Shashank Sharma
2022-12-25 15:44 ` Christian König
2022-12-26 10:41 ` Shashank Sharma
2023-01-02 12:39 ` Christian König
2023-01-03 9:12 ` Shashank Sharma
2023-01-03 9:15 ` Christian König
2023-01-03 9:22 ` Shashank Sharma
2023-01-03 9:35 ` Christian König
2023-01-03 14:34 ` Alex Deucher
2023-01-03 14:50 ` Christian König
2022-12-29 17:41 ` Alex Deucher
2023-01-02 13:53 ` Christian König
2023-01-03 9:32 ` Shashank Sharma
2023-01-03 9:16 ` Shashank Sharma
2023-01-04 8:55 ` Zhu, Jiadong
2023-01-04 8:58 ` Shashank Sharma
2022-12-23 19:36 ` [RFC 3/7] drm/amdgpu: Create MQD for userspace queue Shashank Sharma
2022-12-29 17:47 ` Alex Deucher
2023-01-03 9:36 ` Shashank Sharma
2023-01-03 18:37 ` Felix Kuehling
2023-01-04 6:21 ` Yadav, Arvind
2023-01-04 9:10 ` Christian König
2023-01-04 9:13 ` Shashank Sharma
2023-01-04 9:17 ` Christian König
2023-01-04 9:23 ` Shashank Sharma
2023-01-04 14:35 ` Felix Kuehling
2023-01-04 14:38 ` Yadav, Arvind
2023-01-04 14:41 ` Shashank Sharma
2023-01-04 14:28 ` Alex Deucher
2022-12-23 19:36 ` [RFC 4/7] drm/amdgpu: Allocate doorbell slot for user queue Shashank Sharma
2022-12-29 17:50 ` Alex Deucher
2023-01-03 9:37 ` Shashank Sharma
2022-12-23 19:36 ` [RFC 5/7] drm/amdgpu: Create context for usermode queue Shashank Sharma
2022-12-29 17:54 ` Alex Deucher
2023-01-03 9:40 ` Shashank Sharma
2023-01-03 14:48 ` Alex Deucher
2022-12-23 19:36 ` [RFC 6/7] drm/amdgpu: Map userqueue into HW Shashank Sharma
2022-12-29 17:51 ` Alex Deucher
2023-01-03 9:38 ` Shashank Sharma [this message]
2022-12-23 19:36 ` [RFC 7/7] drm/amdgpu: Secure semaphore for usermode queue Shashank Sharma
2022-12-25 10:07 ` Zhang, Yifan
2022-12-27 9:32 ` Arunpravin Paneer Selvam
2022-12-29 18:02 ` [RFC 0/7] RFC: Usermode queue for AMDGPU driver Alex Deucher
2023-01-03 9:43 ` Shashank Sharma
2023-01-03 9:47 ` Christian König
2023-01-03 10:00 ` Shashank Sharma
2023-01-03 10:02 ` Christian König
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