[PATCH 00/16] DC Patches November 5, 2024

[PATCH 00/16] DC Patches November 5, 2024

[Hamza Mahfooz]

Cc: Daniel Wheeler <daniel.wheeler@amd.com>

Aric Cyr (1):
  drm/amd/display: 3.2.309

Aurabindo Pillai (1):
  drm/amd/display: Read DP tunneling support only for DPIA endpoints

Austin Zheng (1):
  drm/amd/display: Update SPL Taps Required For Integer Scaling

Dillon Varone (1):
  drm/amd/display: Require minimum VBlank size for stutter optimization

Emily Nie (1):
  drm/amd/display: disabling p-state checks for DCN31 and DCN314

Fudongwang (1):
  drm/amd/display: always blank stream before disable crtc

JinZe Xu (1):
  drm/amd/display: Use region6 size in fw_meta_info

Leon Huang (1):
  drm/amd/display: Refactor HPD IRQ error checking flow

Meenakshikumar Somasundaram (1):
  drm/amd/display: Adding flag for forced MST blocked discovery

Revalla Hari Krishna (1):
  drm/amd/display: Change parameters to fix certain compiler errors

Rodrigo Siqueira (2):
  drm/amd/display: Remove unused code
  drm/amd/display: Adjust VSDB parser for replay feature

Ryan Seto (1):
  drm/amd/display: Handle dml allocation failure to avoid crash

Tom Chung (2):
  drm/amd/display: Change some variable name of psr
  drm/amd/display: Fix Panel Replay not update screen correctly

Yihan Zhu (1):
  drm/amd/display: update pipe selection policy to check head pipe

 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 140 +++++++++++-------
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h |   2 +-
 .../amd/display/amdgpu_dm/amdgpu_dm_crtc.c    |   5 +-
 .../display/amdgpu_dm/amdgpu_dm_irq_params.h  |   2 +-
 .../gpu/drm/amd/display/dc/core/dc_state.c    |   3 +
 drivers/gpu/drm/amd/display/dc/dc.h           |   2 +-
 drivers/gpu/drm/amd/display/dc/dc_types.h     |   1 +
 .../dc/dcn10/dcn10_hw_sequencer_debug.c       |   2 +-
 drivers/gpu/drm/amd/display/dc/dm_services.h  |   2 +-
 .../dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c  |  11 +-
 .../display/dc/dml2/dml2_dc_resource_mgmt.c   |  19 ++-
 .../amd/display/dc/hwss/dcn31/dcn31_hwseq.c   |  13 +-
 .../dc/link/protocols/link_dp_capability.c    |   8 +-
 .../dc/link/protocols/link_dp_irq_handler.c   |  16 +-
 .../dc/resource/dcn10/dcn10_resource.c        |  13 --
 .../dc/resource/dcn31/dcn31_resource.c        |   2 +-
 .../dc/resource/dcn314/dcn314_resource.c      |   2 +-
 drivers/gpu/drm/amd/display/dc/spl/dc_spl.c   |  15 +-
 .../gpu/drm/amd/display/dmub/inc/dmub_cmd.h   |  35 ++++-
 .../gpu/drm/amd/display/dmub/src/dmub_srv.c   |   4 +-
 20 files changed, 182 insertions(+), 115 deletions(-)

-- 
2.46.1

[PATCH 01/16] drm/amd/display: Refactor HPD IRQ error checking flow

[Hamza Mahfooz]

From: Leon Huang <Leon.Huang1@amd.com>

[Why]
HPD error status does not cover Replay desync error status
while executing autotests and CTS tests.

[How]
Refactor the checking flow, reporting the HPD error based on
different eDP feature.

Reviewed-by: Robin Chen <robin.chen@amd.com>
Signed-off-by: Leon Huang <Leon.Huang1@amd.com>
Signed-off-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
---
 .../dc/link/protocols/link_dp_irq_handler.c      | 16 +++-------------
 1 file changed, 3 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c
index 96bf135b6f05..48abeaa88678 100644
--- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c
+++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c
@@ -221,21 +221,11 @@ static void handle_hpd_irq_replay_sink(struct dc_link *link)
 		&replay_error_status.raw,
 		sizeof(replay_error_status.raw));
 
-	link->replay_settings.config.replay_error_status.bits.LINK_CRC_ERROR =
-		replay_error_status.bits.LINK_CRC_ERROR;
-	link->replay_settings.config.replay_error_status.bits.DESYNC_ERROR =
-		replay_configuration.bits.DESYNC_ERROR_STATUS;
-	link->replay_settings.config.replay_error_status.bits.STATE_TRANSITION_ERROR =
-		replay_configuration.bits.STATE_TRANSITION_ERROR_STATUS;
-
-	if (link->replay_settings.config.replay_error_status.bits.LINK_CRC_ERROR ||
-		link->replay_settings.config.replay_error_status.bits.DESYNC_ERROR ||
-		link->replay_settings.config.replay_error_status.bits.STATE_TRANSITION_ERROR) {
+	if (replay_error_status.bits.LINK_CRC_ERROR ||
+		replay_configuration.bits.DESYNC_ERROR_STATUS ||
+		replay_configuration.bits.STATE_TRANSITION_ERROR_STATUS) {
 		bool allow_active;
 
-		if (link->replay_settings.config.replay_error_status.bits.DESYNC_ERROR)
-			link->replay_settings.config.received_desync_error_hpd = 1;
-
 		if (link->replay_settings.config.force_disable_desync_error_check)
 			return;
 
-- 
2.46.1

[PATCH 02/16] drm/amd/display: Change parameters to fix certain compiler errors

[Hamza Mahfooz]

From: Revalla Hari Krishna <Harikrishna.Revalla@amd.com>

[Why]
String literals must be assigned to const char pointers.

[How]
By adding const keyword to fix compilation errors.

Reviewed-by: Lohita Mudimela <lohita.mudimela@amd.com>
Signed-off-by: Revalla Hari Krishna <Harikrishna.Revalla@amd.com>
Signed-off-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c | 2 +-
 drivers/gpu/drm/amd/display/dc/dm_services.h                    | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c
index 05df502a54f2..88cf47a5ea75 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c
@@ -46,7 +46,7 @@
 #include "clk_mgr.h"
 
 __printf(3, 4)
-unsigned int snprintf_count(char *pbuf, unsigned int bufsize, char *fmt, ...)
+unsigned int snprintf_count(char *pbuf, unsigned int bufsize, const char *fmt, ...)
 {
 	int ret_vsnprintf;
 	unsigned int chars_printed;
diff --git a/drivers/gpu/drm/amd/display/dc/dm_services.h b/drivers/gpu/drm/amd/display/dc/dm_services.h
index 9405c47ee2a9..f81e5a4e1d6d 100644
--- a/drivers/gpu/drm/amd/display/dc/dm_services.h
+++ b/drivers/gpu/drm/amd/display/dc/dm_services.h
@@ -143,7 +143,7 @@ void generic_reg_wait(const struct dc_context *ctx,
 	unsigned int delay_between_poll_us, unsigned int time_out_num_tries,
 	const char *func_name, int line);
 
-unsigned int snprintf_count(char *pBuf, unsigned int bufSize, char *fmt, ...);
+unsigned int snprintf_count(char *pBuf, unsigned int bufSize, const char *fmt, ...);
 
 /* These macros need to be used with soc15 registers in order to retrieve
  * the actual offset.
-- 
2.46.1

[PATCH 03/16] drm/amd/display: Change some variable name of psr

[Hamza Mahfooz]

From: Tom Chung <chiahsuan.chung@amd.com>

Panel Replay feature may also use the same variable with PSR.
Change the variable name and make it not specify for PSR.

Reviewed-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Tom Chung <chiahsuan.chung@amd.com>
Signed-off-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
---
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 22 +++++++++----------
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h |  2 +-
 .../amd/display/amdgpu_dm/amdgpu_dm_crtc.c    |  2 +-
 .../display/amdgpu_dm/amdgpu_dm_irq_params.h  |  2 +-
 4 files changed, 14 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 7a1b5d5beeaf..570640c25b4b 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -6790,7 +6790,7 @@ create_stream_for_sink(struct drm_connector *connector,
 		if (stream->out_transfer_func.tf == TRANSFER_FUNCTION_GAMMA22)
 			tf = TRANSFER_FUNC_GAMMA_22;
 		mod_build_vsc_infopacket(stream, &stream->vsc_infopacket, stream->output_color_space, tf);
-		aconnector->psr_skip_count = AMDGPU_DM_PSR_ENTRY_DELAY;
+		aconnector->sr_skip_count = AMDGPU_DM_PSR_ENTRY_DELAY;
 
 	}
 finish:
@@ -9016,7 +9016,7 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
 			 * during the PSR-SU was disabled.
 			 */
 			if (acrtc_state->stream->link->psr_settings.psr_version >= DC_PSR_VERSION_SU_1 &&
-			    acrtc_attach->dm_irq_params.allow_psr_entry &&
+			    acrtc_attach->dm_irq_params.allow_sr_entry &&
 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
 			    !amdgpu_dm_crc_window_is_activated(acrtc_state->base.crtc) &&
 #endif
@@ -9251,27 +9251,27 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
 			}
 		}
 
-		/* Decrement skip count when PSR is enabled and we're doing fast updates. */
+		/* Decrement skip count when SR is enabled and we're doing fast updates. */
 		if (acrtc_state->update_type == UPDATE_TYPE_FAST &&
 		    acrtc_state->stream->link->psr_settings.psr_feature_enabled) {
 			struct amdgpu_dm_connector *aconn =
 				(struct amdgpu_dm_connector *)acrtc_state->stream->dm_stream_context;
 
-			if (aconn->psr_skip_count > 0)
-				aconn->psr_skip_count--;
+			if (aconn->sr_skip_count > 0)
+				aconn->sr_skip_count--;
 
-			/* Allow PSR when skip count is 0. */
-			acrtc_attach->dm_irq_params.allow_psr_entry = !aconn->psr_skip_count;
+			/* Allow SR when skip count is 0. */
+			acrtc_attach->dm_irq_params.allow_sr_entry = !aconn->sr_skip_count;
 
 			/*
-			 * If sink supports PSR SU, there is no need to rely on
-			 * a vblank event disable request to enable PSR. PSR SU
+			 * If sink supports PSR SU/Panel Replay, there is no need to rely on
+			 * a vblank event disable request to enable PSR/RP. PSR SU/RP
 			 * can be enabled immediately once OS demonstrates an
 			 * adequate number of fast atomic commits to notify KMD
 			 * of update events. See `vblank_control_worker()`.
 			 */
 			if (acrtc_state->stream->link->psr_settings.psr_version >= DC_PSR_VERSION_SU_1 &&
-			    acrtc_attach->dm_irq_params.allow_psr_entry &&
+			    acrtc_attach->dm_irq_params.allow_sr_entry &&
 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
 			    !amdgpu_dm_crc_window_is_activated(acrtc_state->base.crtc) &&
 #endif
@@ -9282,7 +9282,7 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
 			    500000000)
 				amdgpu_dm_psr_enable(acrtc_state->stream);
 		} else {
-			acrtc_attach->dm_irq_params.allow_psr_entry = false;
+			acrtc_attach->dm_irq_params.allow_sr_entry = false;
 		}
 
 		mutex_unlock(&dm->dc_lock);
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
index 25e95775c45c..6464a8378387 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
@@ -727,7 +727,7 @@ struct amdgpu_dm_connector {
 	/* Cached display modes */
 	struct drm_display_mode freesync_vid_base;
 
-	int psr_skip_count;
+	int sr_skip_count;
 	bool disallow_edp_enter_psr;
 
 	/* Record progress status of mst*/
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c
index 8b5bea799a24..31441f0ec4b0 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c
@@ -268,7 +268,7 @@ static void amdgpu_dm_crtc_vblank_control_worker(struct work_struct *work)
 	if (vblank_work->stream && vblank_work->stream->link) {
 		amdgpu_dm_crtc_set_panel_sr_feature(
 			vblank_work, vblank_work->enable,
-			vblank_work->acrtc->dm_irq_params.allow_psr_entry ||
+			vblank_work->acrtc->dm_irq_params.allow_sr_entry ||
 			vblank_work->stream->link->replay_settings.replay_feature_enabled);
 	}
 
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq_params.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq_params.h
index 5c9303241aeb..6a7ecc1e4602 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq_params.h
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq_params.h
@@ -33,7 +33,7 @@ struct dm_irq_params {
 	struct mod_vrr_params vrr_params;
 	struct dc_stream_state *stream;
 	int active_planes;
-	bool allow_psr_entry;
+	bool allow_sr_entry;
 	struct mod_freesync_config freesync_config;
 
 #ifdef CONFIG_DEBUG_FS
-- 
2.46.1

[PATCH 04/16] drm/amd/display: Fix Panel Replay not update screen correctly

[Hamza Mahfooz]

From: Tom Chung <chiahsuan.chung@amd.com>

[Why]
In certain use case such as KDE login screen, there will be no atomic
commit while do the frame update.
If the Panel Replay enabled, it will cause the screen not updated and
looks like system hang.

[How]
Delay few atomic commits before enabled the Panel Replay just like PSR.

Reviewed-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Tom Chung <chiahsuan.chung@amd.com>
Signed-off-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
---
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 111 +++++++++---------
 .../amd/display/amdgpu_dm/amdgpu_dm_crtc.c    |   5 +-
 2 files changed, 59 insertions(+), 57 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 570640c25b4b..fdc1d2d1afd9 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -8863,6 +8863,56 @@ static void amdgpu_dm_update_cursor(struct drm_plane *plane,
 	}
 }
 
+static void amdgpu_dm_enable_self_refresh(struct amdgpu_crtc *acrtc_attach,
+					  const struct dm_crtc_state *acrtc_state,
+					  const u64 current_ts)
+{
+	struct psr_settings *psr = &acrtc_state->stream->link->psr_settings;
+	struct replay_settings *pr = &acrtc_state->stream->link->replay_settings;
+	struct amdgpu_dm_connector *aconn =
+		(struct amdgpu_dm_connector *)acrtc_state->stream->dm_stream_context;
+
+	if (acrtc_state->update_type > UPDATE_TYPE_FAST) {
+		if (pr->config.replay_supported && !pr->replay_feature_enabled)
+			amdgpu_dm_link_setup_replay(acrtc_state->stream->link, aconn);
+		else if (psr->psr_version != DC_PSR_VERSION_UNSUPPORTED &&
+			     !psr->psr_feature_enabled)
+			if (!aconn->disallow_edp_enter_psr)
+				amdgpu_dm_link_setup_psr(acrtc_state->stream);
+	}
+
+	/* Decrement skip count when SR is enabled and we're doing fast updates. */
+	if (acrtc_state->update_type == UPDATE_TYPE_FAST &&
+	    (psr->psr_feature_enabled || pr->config.replay_supported)) {
+		if (aconn->sr_skip_count > 0)
+			aconn->sr_skip_count--;
+
+		/* Allow SR when skip count is 0. */
+		acrtc_attach->dm_irq_params.allow_sr_entry = !aconn->sr_skip_count;
+
+		/*
+		 * If sink supports PSR SU/Panel Replay, there is no need to rely on
+		 * a vblank event disable request to enable PSR/RP. PSR SU/RP
+		 * can be enabled immediately once OS demonstrates an
+		 * adequate number of fast atomic commits to notify KMD
+		 * of update events. See `vblank_control_worker()`.
+		 */
+		if (acrtc_attach->dm_irq_params.allow_sr_entry &&
+#ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
+		    !amdgpu_dm_crc_window_is_activated(acrtc_state->base.crtc) &&
+#endif
+		    (current_ts - psr->psr_dirty_rects_change_timestamp_ns) > 500000000) {
+			if (pr->replay_feature_enabled && !pr->replay_allow_active)
+				amdgpu_dm_replay_enable(acrtc_state->stream, true);
+			if (psr->psr_version >= DC_PSR_VERSION_SU_1 &&
+			    !psr->psr_allow_active && !aconn->disallow_edp_enter_psr)
+				amdgpu_dm_psr_enable(acrtc_state->stream);
+		}
+	} else {
+		acrtc_attach->dm_irq_params.allow_sr_entry = false;
+	}
+}
+
 static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
 				    struct drm_device *dev,
 				    struct amdgpu_display_manager *dm,
@@ -9191,9 +9241,12 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
 			bundle->stream_update.abm_level = &acrtc_state->abm_level;
 
 		mutex_lock(&dm->dc_lock);
-		if ((acrtc_state->update_type > UPDATE_TYPE_FAST) &&
-				acrtc_state->stream->link->psr_settings.psr_allow_active)
-			amdgpu_dm_psr_disable(acrtc_state->stream);
+		if (acrtc_state->update_type > UPDATE_TYPE_FAST) {
+			if (acrtc_state->stream->link->replay_settings.replay_allow_active)
+				amdgpu_dm_replay_disable(acrtc_state->stream);
+			if (acrtc_state->stream->link->psr_settings.psr_allow_active)
+				amdgpu_dm_psr_disable(acrtc_state->stream);
+		}
 		mutex_unlock(&dm->dc_lock);
 
 		/*
@@ -9234,57 +9287,7 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
 			dm_update_pflip_irq_state(drm_to_adev(dev),
 						  acrtc_attach);
 
-		if (acrtc_state->update_type > UPDATE_TYPE_FAST) {
-			if (acrtc_state->stream->link->replay_settings.config.replay_supported &&
-					!acrtc_state->stream->link->replay_settings.replay_feature_enabled) {
-				struct amdgpu_dm_connector *aconn =
-					(struct amdgpu_dm_connector *)acrtc_state->stream->dm_stream_context;
-				amdgpu_dm_link_setup_replay(acrtc_state->stream->link, aconn);
-			} else if (acrtc_state->stream->link->psr_settings.psr_version != DC_PSR_VERSION_UNSUPPORTED &&
-					!acrtc_state->stream->link->psr_settings.psr_feature_enabled) {
-
-				struct amdgpu_dm_connector *aconn = (struct amdgpu_dm_connector *)
-					acrtc_state->stream->dm_stream_context;
-
-				if (!aconn->disallow_edp_enter_psr)
-					amdgpu_dm_link_setup_psr(acrtc_state->stream);
-			}
-		}
-
-		/* Decrement skip count when SR is enabled and we're doing fast updates. */
-		if (acrtc_state->update_type == UPDATE_TYPE_FAST &&
-		    acrtc_state->stream->link->psr_settings.psr_feature_enabled) {
-			struct amdgpu_dm_connector *aconn =
-				(struct amdgpu_dm_connector *)acrtc_state->stream->dm_stream_context;
-
-			if (aconn->sr_skip_count > 0)
-				aconn->sr_skip_count--;
-
-			/* Allow SR when skip count is 0. */
-			acrtc_attach->dm_irq_params.allow_sr_entry = !aconn->sr_skip_count;
-
-			/*
-			 * If sink supports PSR SU/Panel Replay, there is no need to rely on
-			 * a vblank event disable request to enable PSR/RP. PSR SU/RP
-			 * can be enabled immediately once OS demonstrates an
-			 * adequate number of fast atomic commits to notify KMD
-			 * of update events. See `vblank_control_worker()`.
-			 */
-			if (acrtc_state->stream->link->psr_settings.psr_version >= DC_PSR_VERSION_SU_1 &&
-			    acrtc_attach->dm_irq_params.allow_sr_entry &&
-#ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
-			    !amdgpu_dm_crc_window_is_activated(acrtc_state->base.crtc) &&
-#endif
-			    !acrtc_state->stream->link->psr_settings.psr_allow_active &&
-			    !aconn->disallow_edp_enter_psr &&
-			    (timestamp_ns -
-			    acrtc_state->stream->link->psr_settings.psr_dirty_rects_change_timestamp_ns) >
-			    500000000)
-				amdgpu_dm_psr_enable(acrtc_state->stream);
-		} else {
-			acrtc_attach->dm_irq_params.allow_sr_entry = false;
-		}
-
+		amdgpu_dm_enable_self_refresh(acrtc_attach, acrtc_state, timestamp_ns);
 		mutex_unlock(&dm->dc_lock);
 	}
 
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c
index 31441f0ec4b0..64a041c2af05 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c
@@ -265,11 +265,10 @@ static void amdgpu_dm_crtc_vblank_control_worker(struct work_struct *work)
 	 * where the SU region is the full hactive*vactive region. See
 	 * fill_dc_dirty_rects().
 	 */
-	if (vblank_work->stream && vblank_work->stream->link) {
+	if (vblank_work->stream && vblank_work->stream->link && vblank_work->acrtc) {
 		amdgpu_dm_crtc_set_panel_sr_feature(
 			vblank_work, vblank_work->enable,
-			vblank_work->acrtc->dm_irq_params.allow_sr_entry ||
-			vblank_work->stream->link->replay_settings.replay_feature_enabled);
+			vblank_work->acrtc->dm_irq_params.allow_sr_entry);
 	}
 
 	if (dm->active_vblank_irq_count == 0)
-- 
2.46.1

Re: [PATCH 04/16] drm/amd/display: Fix Panel Replay not update screen correctly

[Mario Limonciello]

On 11/5/2024 14:22, Hamza Mahfooz wrote:
> From: Tom Chung <chiahsuan.chung@amd.com>
> 
> [Why]
> In certain use case such as KDE login screen, there will be no atomic
> commit while do the frame update.
> If the Panel Replay enabled, it will cause the screen not updated and
> looks like system hang.
> 
> [How]
> Delay few atomic commits before enabled the Panel Replay just like PSR.
> 
> Reviewed-by: Leo Li <sunpeng.li@amd.com>
> Signed-off-by: Tom Chung <chiahsuan.chung@amd.com>
> Signed-off-by: Hamza Mahfooz <hamza.mahfooz@amd.com>

As this is an issue reported in the drm/amd tracker and we have panel 
replay in 6.11.y with active reports of this issue a few other tags that 
this should close and associate with.

Cc: stable@vger.kernel.org # 6.11+
Fixes: be64336307a6c ("drm/amd/display: Re-enable panel replay feature")
Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/3686
Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/3682

> ---
>   .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 111 +++++++++---------
>   .../amd/display/amdgpu_dm/amdgpu_dm_crtc.c    |   5 +-
>   2 files changed, 59 insertions(+), 57 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> index 570640c25b4b..fdc1d2d1afd9 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> @@ -8863,6 +8863,56 @@ static void amdgpu_dm_update_cursor(struct drm_plane *plane,
>   	}
>   }
>   
> +static void amdgpu_dm_enable_self_refresh(struct amdgpu_crtc *acrtc_attach,
> +					  const struct dm_crtc_state *acrtc_state,
> +					  const u64 current_ts)
> +{
> +	struct psr_settings *psr = &acrtc_state->stream->link->psr_settings;
> +	struct replay_settings *pr = &acrtc_state->stream->link->replay_settings;
> +	struct amdgpu_dm_connector *aconn =
> +		(struct amdgpu_dm_connector *)acrtc_state->stream->dm_stream_context;
> +
> +	if (acrtc_state->update_type > UPDATE_TYPE_FAST) {
> +		if (pr->config.replay_supported && !pr->replay_feature_enabled)
> +			amdgpu_dm_link_setup_replay(acrtc_state->stream->link, aconn);
> +		else if (psr->psr_version != DC_PSR_VERSION_UNSUPPORTED &&
> +			     !psr->psr_feature_enabled)
> +			if (!aconn->disallow_edp_enter_psr)
> +				amdgpu_dm_link_setup_psr(acrtc_state->stream);
> +	}
> +
> +	/* Decrement skip count when SR is enabled and we're doing fast updates. */
> +	if (acrtc_state->update_type == UPDATE_TYPE_FAST &&
> +	    (psr->psr_feature_enabled || pr->config.replay_supported)) {
> +		if (aconn->sr_skip_count > 0)
> +			aconn->sr_skip_count--;
> +
> +		/* Allow SR when skip count is 0. */
> +		acrtc_attach->dm_irq_params.allow_sr_entry = !aconn->sr_skip_count;
> +
> +		/*
> +		 * If sink supports PSR SU/Panel Replay, there is no need to rely on
> +		 * a vblank event disable request to enable PSR/RP. PSR SU/RP
> +		 * can be enabled immediately once OS demonstrates an
> +		 * adequate number of fast atomic commits to notify KMD
> +		 * of update events. See `vblank_control_worker()`.
> +		 */
> +		if (acrtc_attach->dm_irq_params.allow_sr_entry &&
> +#ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
> +		    !amdgpu_dm_crc_window_is_activated(acrtc_state->base.crtc) &&
> +#endif
> +		    (current_ts - psr->psr_dirty_rects_change_timestamp_ns) > 500000000) {
> +			if (pr->replay_feature_enabled && !pr->replay_allow_active)
> +				amdgpu_dm_replay_enable(acrtc_state->stream, true);
> +			if (psr->psr_version >= DC_PSR_VERSION_SU_1 &&
> +			    !psr->psr_allow_active && !aconn->disallow_edp_enter_psr)
> +				amdgpu_dm_psr_enable(acrtc_state->stream);
> +		}
> +	} else {
> +		acrtc_attach->dm_irq_params.allow_sr_entry = false;
> +	}
> +}
> +
>   static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
>   				    struct drm_device *dev,
>   				    struct amdgpu_display_manager *dm,
> @@ -9191,9 +9241,12 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
>   			bundle->stream_update.abm_level = &acrtc_state->abm_level;
>   
>   		mutex_lock(&dm->dc_lock);
> -		if ((acrtc_state->update_type > UPDATE_TYPE_FAST) &&
> -				acrtc_state->stream->link->psr_settings.psr_allow_active)
> -			amdgpu_dm_psr_disable(acrtc_state->stream);
> +		if (acrtc_state->update_type > UPDATE_TYPE_FAST) {
> +			if (acrtc_state->stream->link->replay_settings.replay_allow_active)
> +				amdgpu_dm_replay_disable(acrtc_state->stream);
> +			if (acrtc_state->stream->link->psr_settings.psr_allow_active)
> +				amdgpu_dm_psr_disable(acrtc_state->stream);
> +		}
>   		mutex_unlock(&dm->dc_lock);
>   
>   		/*
> @@ -9234,57 +9287,7 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
>   			dm_update_pflip_irq_state(drm_to_adev(dev),
>   						  acrtc_attach);
>   
> -		if (acrtc_state->update_type > UPDATE_TYPE_FAST) {
> -			if (acrtc_state->stream->link->replay_settings.config.replay_supported &&
> -					!acrtc_state->stream->link->replay_settings.replay_feature_enabled) {
> -				struct amdgpu_dm_connector *aconn =
> -					(struct amdgpu_dm_connector *)acrtc_state->stream->dm_stream_context;
> -				amdgpu_dm_link_setup_replay(acrtc_state->stream->link, aconn);
> -			} else if (acrtc_state->stream->link->psr_settings.psr_version != DC_PSR_VERSION_UNSUPPORTED &&
> -					!acrtc_state->stream->link->psr_settings.psr_feature_enabled) {
> -
> -				struct amdgpu_dm_connector *aconn = (struct amdgpu_dm_connector *)
> -					acrtc_state->stream->dm_stream_context;
> -
> -				if (!aconn->disallow_edp_enter_psr)
> -					amdgpu_dm_link_setup_psr(acrtc_state->stream);
> -			}
> -		}
> -
> -		/* Decrement skip count when SR is enabled and we're doing fast updates. */
> -		if (acrtc_state->update_type == UPDATE_TYPE_FAST &&
> -		    acrtc_state->stream->link->psr_settings.psr_feature_enabled) {
> -			struct amdgpu_dm_connector *aconn =
> -				(struct amdgpu_dm_connector *)acrtc_state->stream->dm_stream_context;
> -
> -			if (aconn->sr_skip_count > 0)
> -				aconn->sr_skip_count--;
> -
> -			/* Allow SR when skip count is 0. */
> -			acrtc_attach->dm_irq_params.allow_sr_entry = !aconn->sr_skip_count;
> -
> -			/*
> -			 * If sink supports PSR SU/Panel Replay, there is no need to rely on
> -			 * a vblank event disable request to enable PSR/RP. PSR SU/RP
> -			 * can be enabled immediately once OS demonstrates an
> -			 * adequate number of fast atomic commits to notify KMD
> -			 * of update events. See `vblank_control_worker()`.
> -			 */
> -			if (acrtc_state->stream->link->psr_settings.psr_version >= DC_PSR_VERSION_SU_1 &&
> -			    acrtc_attach->dm_irq_params.allow_sr_entry &&
> -#ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
> -			    !amdgpu_dm_crc_window_is_activated(acrtc_state->base.crtc) &&
> -#endif
> -			    !acrtc_state->stream->link->psr_settings.psr_allow_active &&
> -			    !aconn->disallow_edp_enter_psr &&
> -			    (timestamp_ns -
> -			    acrtc_state->stream->link->psr_settings.psr_dirty_rects_change_timestamp_ns) >
> -			    500000000)
> -				amdgpu_dm_psr_enable(acrtc_state->stream);
> -		} else {
> -			acrtc_attach->dm_irq_params.allow_sr_entry = false;
> -		}
> -
> +		amdgpu_dm_enable_self_refresh(acrtc_attach, acrtc_state, timestamp_ns);
>   		mutex_unlock(&dm->dc_lock);
>   	}
>   
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c
> index 31441f0ec4b0..64a041c2af05 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c
> @@ -265,11 +265,10 @@ static void amdgpu_dm_crtc_vblank_control_worker(struct work_struct *work)
>   	 * where the SU region is the full hactive*vactive region. See
>   	 * fill_dc_dirty_rects().
>   	 */
> -	if (vblank_work->stream && vblank_work->stream->link) {
> +	if (vblank_work->stream && vblank_work->stream->link && vblank_work->acrtc) {
>   		amdgpu_dm_crtc_set_panel_sr_feature(
>   			vblank_work, vblank_work->enable,
> -			vblank_work->acrtc->dm_irq_params.allow_sr_entry ||
> -			vblank_work->stream->link->replay_settings.replay_feature_enabled);
> +			vblank_work->acrtc->dm_irq_params.allow_sr_entry);
>   	}
>   
>   	if (dm->active_vblank_irq_count == 0)

Re: [PATCH 04/16] drm/amd/display: Fix Panel Replay not update screen correctly

[Mario Limonciello]

On 11/6/2024 14:25, Mario Limonciello wrote:
> On 11/5/2024 14:22, Hamza Mahfooz wrote:
>> From: Tom Chung <chiahsuan.chung@amd.com>
>>
>> [Why]
>> In certain use case such as KDE login screen, there will be no atomic
>> commit while do the frame update.
>> If the Panel Replay enabled, it will cause the screen not updated and
>> looks like system hang.
>>
>> [How]
>> Delay few atomic commits before enabled the Panel Replay just like PSR.
>>
>> Reviewed-by: Leo Li <sunpeng.li@amd.com>
>> Signed-off-by: Tom Chung <chiahsuan.chung@amd.com>
>> Signed-off-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
> 
> As this is an issue reported in the drm/amd tracker and we have panel 
> replay in 6.11.y with active reports of this issue a few other tags that 
> this should close and associate with.
> 
> Cc: stable@vger.kernel.org # 6.11+
> Fixes: be64336307a6c ("drm/amd/display: Re-enable panel replay feature")
> Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/3686
> Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/3682

And one of the reporterers for those bugs tested it helps their issue,
so here is a tag for them.

Tested-By: Corey Hickey <bugfood-c@fatooh.org>

> 
>> ---
>>   .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 111 +++++++++---------
>>   .../amd/display/amdgpu_dm/amdgpu_dm_crtc.c    |   5 +-
>>   2 files changed, 59 insertions(+), 57 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/ 
>> drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
>> index 570640c25b4b..fdc1d2d1afd9 100644
>> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
>> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
>> @@ -8863,6 +8863,56 @@ static void amdgpu_dm_update_cursor(struct 
>> drm_plane *plane,
>>       }
>>   }
>> +static void amdgpu_dm_enable_self_refresh(struct amdgpu_crtc 
>> *acrtc_attach,
>> +                      const struct dm_crtc_state *acrtc_state,
>> +                      const u64 current_ts)
>> +{
>> +    struct psr_settings *psr = &acrtc_state->stream->link->psr_settings;
>> +    struct replay_settings *pr = &acrtc_state->stream->link- 
>> >replay_settings;
>> +    struct amdgpu_dm_connector *aconn =
>> +        (struct amdgpu_dm_connector *)acrtc_state->stream- 
>> >dm_stream_context;
>> +
>> +    if (acrtc_state->update_type > UPDATE_TYPE_FAST) {
>> +        if (pr->config.replay_supported && !pr->replay_feature_enabled)
>> +            amdgpu_dm_link_setup_replay(acrtc_state->stream->link, 
>> aconn);
>> +        else if (psr->psr_version != DC_PSR_VERSION_UNSUPPORTED &&
>> +                 !psr->psr_feature_enabled)
>> +            if (!aconn->disallow_edp_enter_psr)
>> +                amdgpu_dm_link_setup_psr(acrtc_state->stream);
>> +    }
>> +
>> +    /* Decrement skip count when SR is enabled and we're doing fast 
>> updates. */
>> +    if (acrtc_state->update_type == UPDATE_TYPE_FAST &&
>> +        (psr->psr_feature_enabled || pr->config.replay_supported)) {
>> +        if (aconn->sr_skip_count > 0)
>> +            aconn->sr_skip_count--;
>> +
>> +        /* Allow SR when skip count is 0. */
>> +        acrtc_attach->dm_irq_params.allow_sr_entry = !aconn- 
>> >sr_skip_count;
>> +
>> +        /*
>> +         * If sink supports PSR SU/Panel Replay, there is no need to 
>> rely on
>> +         * a vblank event disable request to enable PSR/RP. PSR SU/RP
>> +         * can be enabled immediately once OS demonstrates an
>> +         * adequate number of fast atomic commits to notify KMD
>> +         * of update events. See `vblank_control_worker()`.
>> +         */
>> +        if (acrtc_attach->dm_irq_params.allow_sr_entry &&
>> +#ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
>> +            !amdgpu_dm_crc_window_is_activated(acrtc_state- 
>> >base.crtc) &&
>> +#endif
>> +            (current_ts - psr->psr_dirty_rects_change_timestamp_ns) > 
>> 500000000) {
>> +            if (pr->replay_feature_enabled && !pr->replay_allow_active)
>> +                amdgpu_dm_replay_enable(acrtc_state->stream, true);
>> +            if (psr->psr_version >= DC_PSR_VERSION_SU_1 &&
>> +                !psr->psr_allow_active && !aconn- 
>> >disallow_edp_enter_psr)
>> +                amdgpu_dm_psr_enable(acrtc_state->stream);
>> +        }
>> +    } else {
>> +        acrtc_attach->dm_irq_params.allow_sr_entry = false;
>> +    }
>> +}
>> +
>>   static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
>>                       struct drm_device *dev,
>>                       struct amdgpu_display_manager *dm,
>> @@ -9191,9 +9241,12 @@ static void amdgpu_dm_commit_planes(struct 
>> drm_atomic_state *state,
>>               bundle->stream_update.abm_level = &acrtc_state->abm_level;
>>           mutex_lock(&dm->dc_lock);
>> -        if ((acrtc_state->update_type > UPDATE_TYPE_FAST) &&
>> -                acrtc_state->stream->link- 
>> >psr_settings.psr_allow_active)
>> -            amdgpu_dm_psr_disable(acrtc_state->stream);
>> +        if (acrtc_state->update_type > UPDATE_TYPE_FAST) {
>> +            if (acrtc_state->stream->link- 
>> >replay_settings.replay_allow_active)
>> +                amdgpu_dm_replay_disable(acrtc_state->stream);
>> +            if (acrtc_state->stream->link- 
>> >psr_settings.psr_allow_active)
>> +                amdgpu_dm_psr_disable(acrtc_state->stream);
>> +        }
>>           mutex_unlock(&dm->dc_lock);
>>           /*
>> @@ -9234,57 +9287,7 @@ static void amdgpu_dm_commit_planes(struct 
>> drm_atomic_state *state,
>>               dm_update_pflip_irq_state(drm_to_adev(dev),
>>                             acrtc_attach);
>> -        if (acrtc_state->update_type > UPDATE_TYPE_FAST) {
>> -            if (acrtc_state->stream->link- 
>> >replay_settings.config.replay_supported &&
>> -                    !acrtc_state->stream->link- 
>> >replay_settings.replay_feature_enabled) {
>> -                struct amdgpu_dm_connector *aconn =
>> -                    (struct amdgpu_dm_connector *)acrtc_state- 
>> >stream->dm_stream_context;
>> -                amdgpu_dm_link_setup_replay(acrtc_state->stream- 
>> >link, aconn);
>> -            } else if (acrtc_state->stream->link- 
>> >psr_settings.psr_version != DC_PSR_VERSION_UNSUPPORTED &&
>> -                    !acrtc_state->stream->link- 
>> >psr_settings.psr_feature_enabled) {
>> -
>> -                struct amdgpu_dm_connector *aconn = (struct 
>> amdgpu_dm_connector *)
>> -                    acrtc_state->stream->dm_stream_context;
>> -
>> -                if (!aconn->disallow_edp_enter_psr)
>> -                    amdgpu_dm_link_setup_psr(acrtc_state->stream);
>> -            }
>> -        }
>> -
>> -        /* Decrement skip count when SR is enabled and we're doing 
>> fast updates. */
>> -        if (acrtc_state->update_type == UPDATE_TYPE_FAST &&
>> -            acrtc_state->stream->link- 
>> >psr_settings.psr_feature_enabled) {
>> -            struct amdgpu_dm_connector *aconn =
>> -                (struct amdgpu_dm_connector *)acrtc_state->stream- 
>> >dm_stream_context;
>> -
>> -            if (aconn->sr_skip_count > 0)
>> -                aconn->sr_skip_count--;
>> -
>> -            /* Allow SR when skip count is 0. */
>> -            acrtc_attach->dm_irq_params.allow_sr_entry = !aconn- 
>> >sr_skip_count;
>> -
>> -            /*
>> -             * If sink supports PSR SU/Panel Replay, there is no need 
>> to rely on
>> -             * a vblank event disable request to enable PSR/RP. PSR 
>> SU/RP
>> -             * can be enabled immediately once OS demonstrates an
>> -             * adequate number of fast atomic commits to notify KMD
>> -             * of update events. See `vblank_control_worker()`.
>> -             */
>> -            if (acrtc_state->stream->link->psr_settings.psr_version 
>> >= DC_PSR_VERSION_SU_1 &&
>> -                acrtc_attach->dm_irq_params.allow_sr_entry &&
>> -#ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
>> -                !amdgpu_dm_crc_window_is_activated(acrtc_state- 
>> >base.crtc) &&
>> -#endif
>> -                !acrtc_state->stream->link- 
>> >psr_settings.psr_allow_active &&
>> -                !aconn->disallow_edp_enter_psr &&
>> -                (timestamp_ns -
>> -                acrtc_state->stream->link- 
>> >psr_settings.psr_dirty_rects_change_timestamp_ns) >
>> -                500000000)
>> -                amdgpu_dm_psr_enable(acrtc_state->stream);
>> -        } else {
>> -            acrtc_attach->dm_irq_params.allow_sr_entry = false;
>> -        }
>> -
>> +        amdgpu_dm_enable_self_refresh(acrtc_attach, acrtc_state, 
>> timestamp_ns);
>>           mutex_unlock(&dm->dc_lock);
>>       }
>> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c b/ 
>> drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c
>> index 31441f0ec4b0..64a041c2af05 100644
>> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c
>> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c
>> @@ -265,11 +265,10 @@ static void 
>> amdgpu_dm_crtc_vblank_control_worker(struct work_struct *work)
>>        * where the SU region is the full hactive*vactive region. See
>>        * fill_dc_dirty_rects().
>>        */
>> -    if (vblank_work->stream && vblank_work->stream->link) {
>> +    if (vblank_work->stream && vblank_work->stream->link && 
>> vblank_work->acrtc) {
>>           amdgpu_dm_crtc_set_panel_sr_feature(
>>               vblank_work, vblank_work->enable,
>> -            vblank_work->acrtc->dm_irq_params.allow_sr_entry ||
>> -            vblank_work->stream->link- 
>> >replay_settings.replay_feature_enabled);
>> +            vblank_work->acrtc->dm_irq_params.allow_sr_entry);
>>       }
>>       if (dm->active_vblank_irq_count == 0)
> 

Re: [PATCH 04/16] drm/amd/display: Fix Panel Replay not update screen correctly

[Mario Limonciello]

On 11/7/2024 08:15, Mario Limonciello wrote:
> On 11/6/2024 14:25, Mario Limonciello wrote:
>> On 11/5/2024 14:22, Hamza Mahfooz wrote:
>>> From: Tom Chung <chiahsuan.chung@amd.com>
>>>
>>> [Why]
>>> In certain use case such as KDE login screen, there will be no atomic
>>> commit while do the frame update.
>>> If the Panel Replay enabled, it will cause the screen not updated and
>>> looks like system hang.
>>>
>>> [How]
>>> Delay few atomic commits before enabled the Panel Replay just like PSR.
>>>
>>> Reviewed-by: Leo Li <sunpeng.li@amd.com>
>>> Signed-off-by: Tom Chung <chiahsuan.chung@amd.com>
>>> Signed-off-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
>>
>> As this is an issue reported in the drm/amd tracker and we have panel 
>> replay in 6.11.y with active reports of this issue a few other tags 
>> that this should close and associate with.
>>
>> Cc: stable@vger.kernel.org # 6.11+
>> Fixes: be64336307a6c ("drm/amd/display: Re-enable panel replay feature")
>> Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/3686
>> Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/3682
> 
> And one of the reporterers for those bugs tested it helps their issue,
> so here is a tag for them.
> 
> Tested-By: Corey Hickey <bugfood-c@fatooh.org>

Tested-By: James Courtier-Dutton <james.dutton@gmail.com>

> 
>>
>>> ---
>>>   .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 111 +++++++++---------
>>>   .../amd/display/amdgpu_dm/amdgpu_dm_crtc.c    |   5 +-
>>>   2 files changed, 59 insertions(+), 57 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/ 
>>> drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
>>> index 570640c25b4b..fdc1d2d1afd9 100644
>>> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
>>> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
>>> @@ -8863,6 +8863,56 @@ static void amdgpu_dm_update_cursor(struct 
>>> drm_plane *plane,
>>>       }
>>>   }
>>> +static void amdgpu_dm_enable_self_refresh(struct amdgpu_crtc 
>>> *acrtc_attach,
>>> +                      const struct dm_crtc_state *acrtc_state,
>>> +                      const u64 current_ts)
>>> +{
>>> +    struct psr_settings *psr = &acrtc_state->stream->link- 
>>> >psr_settings;
>>> +    struct replay_settings *pr = &acrtc_state->stream->link- 
>>> >replay_settings;
>>> +    struct amdgpu_dm_connector *aconn =
>>> +        (struct amdgpu_dm_connector *)acrtc_state->stream- 
>>> >dm_stream_context;
>>> +
>>> +    if (acrtc_state->update_type > UPDATE_TYPE_FAST) {
>>> +        if (pr->config.replay_supported && !pr->replay_feature_enabled)
>>> +            amdgpu_dm_link_setup_replay(acrtc_state->stream->link, 
>>> aconn);
>>> +        else if (psr->psr_version != DC_PSR_VERSION_UNSUPPORTED &&
>>> +                 !psr->psr_feature_enabled)
>>> +            if (!aconn->disallow_edp_enter_psr)
>>> +                amdgpu_dm_link_setup_psr(acrtc_state->stream);
>>> +    }
>>> +
>>> +    /* Decrement skip count when SR is enabled and we're doing fast 
>>> updates. */
>>> +    if (acrtc_state->update_type == UPDATE_TYPE_FAST &&
>>> +        (psr->psr_feature_enabled || pr->config.replay_supported)) {
>>> +        if (aconn->sr_skip_count > 0)
>>> +            aconn->sr_skip_count--;
>>> +
>>> +        /* Allow SR when skip count is 0. */
>>> +        acrtc_attach->dm_irq_params.allow_sr_entry = !aconn- 
>>> >sr_skip_count;
>>> +
>>> +        /*
>>> +         * If sink supports PSR SU/Panel Replay, there is no need to 
>>> rely on
>>> +         * a vblank event disable request to enable PSR/RP. PSR SU/RP
>>> +         * can be enabled immediately once OS demonstrates an
>>> +         * adequate number of fast atomic commits to notify KMD
>>> +         * of update events. See `vblank_control_worker()`.
>>> +         */
>>> +        if (acrtc_attach->dm_irq_params.allow_sr_entry &&
>>> +#ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
>>> +            !amdgpu_dm_crc_window_is_activated(acrtc_state- 
>>> >base.crtc) &&
>>> +#endif
>>> +            (current_ts - psr->psr_dirty_rects_change_timestamp_ns) 
>>> > 500000000) {
>>> +            if (pr->replay_feature_enabled && !pr->replay_allow_active)
>>> +                amdgpu_dm_replay_enable(acrtc_state->stream, true);
>>> +            if (psr->psr_version >= DC_PSR_VERSION_SU_1 &&
>>> +                !psr->psr_allow_active && !aconn- 
>>> >disallow_edp_enter_psr)
>>> +                amdgpu_dm_psr_enable(acrtc_state->stream);
>>> +        }
>>> +    } else {
>>> +        acrtc_attach->dm_irq_params.allow_sr_entry = false;
>>> +    }
>>> +}
>>> +
>>>   static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
>>>                       struct drm_device *dev,
>>>                       struct amdgpu_display_manager *dm,
>>> @@ -9191,9 +9241,12 @@ static void amdgpu_dm_commit_planes(struct 
>>> drm_atomic_state *state,
>>>               bundle->stream_update.abm_level = &acrtc_state->abm_level;
>>>           mutex_lock(&dm->dc_lock);
>>> -        if ((acrtc_state->update_type > UPDATE_TYPE_FAST) &&
>>> -                acrtc_state->stream->link- 
>>> >psr_settings.psr_allow_active)
>>> -            amdgpu_dm_psr_disable(acrtc_state->stream);
>>> +        if (acrtc_state->update_type > UPDATE_TYPE_FAST) {
>>> +            if (acrtc_state->stream->link- 
>>> >replay_settings.replay_allow_active)
>>> +                amdgpu_dm_replay_disable(acrtc_state->stream);
>>> +            if (acrtc_state->stream->link- 
>>> >psr_settings.psr_allow_active)
>>> +                amdgpu_dm_psr_disable(acrtc_state->stream);
>>> +        }
>>>           mutex_unlock(&dm->dc_lock);
>>>           /*
>>> @@ -9234,57 +9287,7 @@ static void amdgpu_dm_commit_planes(struct 
>>> drm_atomic_state *state,
>>>               dm_update_pflip_irq_state(drm_to_adev(dev),
>>>                             acrtc_attach);
>>> -        if (acrtc_state->update_type > UPDATE_TYPE_FAST) {
>>> -            if (acrtc_state->stream->link- 
>>> >replay_settings.config.replay_supported &&
>>> -                    !acrtc_state->stream->link- 
>>> >replay_settings.replay_feature_enabled) {
>>> -                struct amdgpu_dm_connector *aconn =
>>> -                    (struct amdgpu_dm_connector *)acrtc_state- 
>>> >stream->dm_stream_context;
>>> -                amdgpu_dm_link_setup_replay(acrtc_state->stream- 
>>> >link, aconn);
>>> -            } else if (acrtc_state->stream->link- 
>>> >psr_settings.psr_version != DC_PSR_VERSION_UNSUPPORTED &&
>>> -                    !acrtc_state->stream->link- 
>>> >psr_settings.psr_feature_enabled) {
>>> -
>>> -                struct amdgpu_dm_connector *aconn = (struct 
>>> amdgpu_dm_connector *)
>>> -                    acrtc_state->stream->dm_stream_context;
>>> -
>>> -                if (!aconn->disallow_edp_enter_psr)
>>> -                    amdgpu_dm_link_setup_psr(acrtc_state->stream);
>>> -            }
>>> -        }
>>> -
>>> -        /* Decrement skip count when SR is enabled and we're doing 
>>> fast updates. */
>>> -        if (acrtc_state->update_type == UPDATE_TYPE_FAST &&
>>> -            acrtc_state->stream->link- 
>>> >psr_settings.psr_feature_enabled) {
>>> -            struct amdgpu_dm_connector *aconn =
>>> -                (struct amdgpu_dm_connector *)acrtc_state->stream- 
>>> >dm_stream_context;
>>> -
>>> -            if (aconn->sr_skip_count > 0)
>>> -                aconn->sr_skip_count--;
>>> -
>>> -            /* Allow SR when skip count is 0. */
>>> -            acrtc_attach->dm_irq_params.allow_sr_entry = !aconn- 
>>> >sr_skip_count;
>>> -
>>> -            /*
>>> -             * If sink supports PSR SU/Panel Replay, there is no 
>>> need to rely on
>>> -             * a vblank event disable request to enable PSR/RP. PSR 
>>> SU/RP
>>> -             * can be enabled immediately once OS demonstrates an
>>> -             * adequate number of fast atomic commits to notify KMD
>>> -             * of update events. See `vblank_control_worker()`.
>>> -             */
>>> -            if (acrtc_state->stream->link->psr_settings.psr_version 
>>> >= DC_PSR_VERSION_SU_1 &&
>>> -                acrtc_attach->dm_irq_params.allow_sr_entry &&
>>> -#ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
>>> -                !amdgpu_dm_crc_window_is_activated(acrtc_state- 
>>> >base.crtc) &&
>>> -#endif
>>> -                !acrtc_state->stream->link- 
>>> >psr_settings.psr_allow_active &&
>>> -                !aconn->disallow_edp_enter_psr &&
>>> -                (timestamp_ns -
>>> -                acrtc_state->stream->link- 
>>> >psr_settings.psr_dirty_rects_change_timestamp_ns) >
>>> -                500000000)
>>> -                amdgpu_dm_psr_enable(acrtc_state->stream);
>>> -        } else {
>>> -            acrtc_attach->dm_irq_params.allow_sr_entry = false;
>>> -        }
>>> -
>>> +        amdgpu_dm_enable_self_refresh(acrtc_attach, acrtc_state, 
>>> timestamp_ns);
>>>           mutex_unlock(&dm->dc_lock);
>>>       }
>>> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c 
>>> b/ drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c
>>> index 31441f0ec4b0..64a041c2af05 100644
>>> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c
>>> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c
>>> @@ -265,11 +265,10 @@ static void 
>>> amdgpu_dm_crtc_vblank_control_worker(struct work_struct *work)
>>>        * where the SU region is the full hactive*vactive region. See
>>>        * fill_dc_dirty_rects().
>>>        */
>>> -    if (vblank_work->stream && vblank_work->stream->link) {
>>> +    if (vblank_work->stream && vblank_work->stream->link && 
>>> vblank_work->acrtc) {
>>>           amdgpu_dm_crtc_set_panel_sr_feature(
>>>               vblank_work, vblank_work->enable,
>>> -            vblank_work->acrtc->dm_irq_params.allow_sr_entry ||
>>> -            vblank_work->stream->link- 
>>> >replay_settings.replay_feature_enabled);
>>> +            vblank_work->acrtc->dm_irq_params.allow_sr_entry);
>>>       }
>>>       if (dm->active_vblank_irq_count == 0)
>>
> 

[PATCH 05/16] drm/amd/display: Adding flag for forced MST blocked discovery

[Hamza Mahfooz]

From: Meenakshikumar Somasundaram <meenakshikumar.somasundaram@amd.com>

[Why]
Need a flag to force MST blocked discovery for certain branch devices.

[How]
Added a flag to force MST blocked discovery in struct dc_panel_patch.

Reviewed-by: PeiChen Huang <peichen.huang@amd.com>
Reviewed-by: Wenjing Liu <wenjing.liu@amd.com>
Signed-off-by: Meenakshikumar Somasundaram <meenakshikumar.somasundaram@amd.com>
Signed-off-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dc_types.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h b/drivers/gpu/drm/amd/display/dc/dc_types.h
index 1fd030e3f4be..edf4df1d03b5 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_types.h
@@ -181,6 +181,7 @@ struct dc_panel_patch {
 	unsigned int disable_colorimetry;
 	uint8_t blankstream_before_otg_off;
 	bool oled_optimize_display_on;
+	unsigned int force_mst_blocked_discovery;
 };
 
 struct dc_edid_caps {
-- 
2.46.1

[PATCH 06/16] drm/amd/display: Read DP tunneling support only for DPIA endpoints

[Hamza Mahfooz]

From: Aurabindo Pillai <aurabindo.pillai@amd.com>

Unconditionally reading DP tunneling support results in extraneous
errors messages on certain devices. Fix this by guarding the DPCD read
for DP tunneling support for USB4 DPIA endpoints.

Reviewed-by: Meenakshikumar Somasundaram <meenakshikumar.somasundaram@amd.com>
Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
---
 .../amd/display/dc/link/protocols/link_dp_capability.c    | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c
index 72ef0c3a7ebd..9dabaf682171 100644
--- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c
+++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c
@@ -1633,9 +1633,11 @@ static bool retrieve_link_cap(struct dc_link *link)
 	}
 
 	/* Read DP tunneling information. */
-	status = dpcd_get_tunneling_device_data(link);
-	if (status != DC_OK)
-		dm_error("%s: Read tunneling device data failed.\n", __func__);
+	if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) {
+		status = dpcd_get_tunneling_device_data(link);
+		if (status != DC_OK)
+			dm_error("%s: Read tunneling device data failed.\n", __func__);
+	}
 
 	dpcd_set_source_specific_data(link);
 	/* Sink may need to configure internals based on vendor, so allow some
-- 
2.46.1

[PATCH 07/16] drm/amd/display: always blank stream before disable crtc

[Hamza Mahfooz]

From: Fudongwang <Fudong.Wang@amd.com>

Garbage will show due to dig is on. So blank stream needed.

Cc: stable@vger.kernel.org
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Fudongwang <Fudong.Wang@amd.com>
Signed-off-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
---
 .../gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c    | 10 ++++++----
 1 file changed, 6 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c
index 036cb7e9b5bb..59b2e87317e3 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c
@@ -519,15 +519,18 @@ static void dcn31_reset_back_end_for_pipe(
 
 	dc->hwss.set_abm_immediate_disable(pipe_ctx);
 
-	if ((!pipe_ctx->stream->dpms_off || pipe_ctx->stream->link->link_status.link_active)
-		&& pipe_ctx->stream->sink && pipe_ctx->stream->sink->edid_caps.panel_patch.blankstream_before_otg_off) {
+	link = pipe_ctx->stream->link;
+
+	if ((!pipe_ctx->stream->dpms_off || link->link_status.link_active) &&
+		(link->connector_signal == SIGNAL_TYPE_EDP))
 		dc->hwss.blank_stream(pipe_ctx);
-	}
 
 	pipe_ctx->stream_res.tg->funcs->set_dsc_config(
 			pipe_ctx->stream_res.tg,
 			OPTC_DSC_DISABLED, 0, 0);
+
 	pipe_ctx->stream_res.tg->funcs->disable_crtc(pipe_ctx->stream_res.tg);
+
 	pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, false);
 	if (pipe_ctx->stream_res.tg->funcs->set_odm_bypass)
 		pipe_ctx->stream_res.tg->funcs->set_odm_bypass(
@@ -539,7 +542,6 @@ static void dcn31_reset_back_end_for_pipe(
 		pipe_ctx->stream_res.tg->funcs->set_drr(
 				pipe_ctx->stream_res.tg, NULL);
 
-	link = pipe_ctx->stream->link;
 	/* DPMS may already disable or */
 	/* dpms_off status is incorrect due to fastboot
 	 * feature. When system resume from S4 with second
-- 
2.46.1

[PATCH 08/16] drm/amd/display: disabling p-state checks for DCN31 and DCN314

[Hamza Mahfooz]

From: Emily Nie <Emily.Nie@amd.com>

[Why]
IGT displays Dmesg warnings which are likely false

[How]
Disabling p-state checks leading to this warning for DCN31 and DCN314

Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Emily Nie <Emily.Nie@amd.com>
Signed-off-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
---
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 23 +++++++++++++++++++
 .../dc/resource/dcn31/dcn31_resource.c        |  2 +-
 .../dc/resource/dcn314/dcn314_resource.c      |  2 +-
 3 files changed, 25 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index fdc1d2d1afd9..1d47719e7af1 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -1307,6 +1307,29 @@ static int dm_dmub_hw_init(struct amdgpu_device *adev)
 	DRM_INFO("DMUB hardware initialized: version=0x%08X\n",
 		 adev->dm.dmcub_fw_version);
 
+	/* Keeping sanity checks off if
+	 * DCN31 >= 4.0.59.0
+	 * DCN314 >= 8.0.16.0
+	 * Otherwise, turn on sanity checks
+	 */
+	switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {
+	case IP_VERSION(3, 1, 2):
+	case IP_VERSION(3, 1, 3):
+		if (adev->dm.dmcub_fw_version &&
+			adev->dm.dmcub_fw_version >= DMUB_FW_VERSION(4, 0, 0) &&
+			adev->dm.dmcub_fw_version < DMUB_FW_VERSION(4, 0, 59))
+				adev->dm.dc->debug.sanity_checks = true;
+		break;
+	case IP_VERSION(3, 1, 4):
+		if (adev->dm.dmcub_fw_version &&
+			adev->dm.dmcub_fw_version >= DMUB_FW_VERSION(4, 0, 0) &&
+			adev->dm.dmcub_fw_version < DMUB_FW_VERSION(8, 0, 16))
+				adev->dm.dc->debug.sanity_checks = true;
+		break;
+	default:
+		break;
+	}
+
 	return 0;
 }
 
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
index f71a5b8286b2..c16cf1c8f7f9 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
@@ -868,7 +868,7 @@ static const struct dc_debug_options debug_defaults_drv = {
 	.max_downscale_src_width = 4096,/*upto true 4K*/
 	.disable_pplib_wm_range = false,
 	.scl_reset_length10 = true,
-	.sanity_checks = true,
+	.sanity_checks = false,
 	.underflow_assert_delay_us = 0xFFFFFFFF,
 	.dwb_fi_phase = -1, // -1 = disable,
 	.dmub_command_table = true,
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
index 8aa10da68432..c0f48c78e968 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
@@ -888,7 +888,7 @@ static const struct dc_debug_options debug_defaults_drv = {
 	.max_downscale_src_width = 4096,/*upto true 4k*/
 	.disable_pplib_wm_range = false,
 	.scl_reset_length10 = true,
-	.sanity_checks = true,
+	.sanity_checks = false,
 	.underflow_assert_delay_us = 0xFFFFFFFF,
 	.dwb_fi_phase = -1, // -1 = disable,
 	.dmub_command_table = true,
-- 
2.46.1

[PATCH 09/16] drm/amd/display: Update SPL Taps Required For Integer Scaling

[Hamza Mahfooz]

From: Austin Zheng <Austin.Zheng@amd.com>

Number of taps is incorrectly being set when integer scaling is enabled.
Taps required when src_rect != dst_rect previously not considered.
Perform the calculations when integer scaling is enabled.
Set taps to 1 if the scaling ratio is 1:1.

Reviewed-by: Samson Tam <samson.tam@amd.com>
Signed-off-by: Austin Zheng <Austin.Zheng@amd.com>
Signed-off-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
---
 drivers/gpu/drm/amd/display/dc/spl/dc_spl.c | 15 +++++++++++----
 1 file changed, 11 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/spl/dc_spl.c b/drivers/gpu/drm/amd/display/dc/spl/dc_spl.c
index a29a9f131e04..614276200aa0 100644
--- a/drivers/gpu/drm/amd/display/dc/spl/dc_spl.c
+++ b/drivers/gpu/drm/amd/display/dc/spl/dc_spl.c
@@ -910,6 +910,16 @@ static void spl_get_taps_non_adaptive_scaler(
 		spl_scratch->scl_data.taps.h_taps_c = in_taps->h_taps_c - 1;
 	else
 		spl_scratch->scl_data.taps.h_taps_c = in_taps->h_taps_c;
+
+	if (IDENTITY_RATIO(spl_scratch->scl_data.ratios.horz))
+		spl_scratch->scl_data.taps.h_taps = 1;
+	if (IDENTITY_RATIO(spl_scratch->scl_data.ratios.vert))
+		spl_scratch->scl_data.taps.v_taps = 1;
+	if (IDENTITY_RATIO(spl_scratch->scl_data.ratios.horz_c))
+		spl_scratch->scl_data.taps.h_taps_c = 1;
+	if (IDENTITY_RATIO(spl_scratch->scl_data.ratios.vert_c))
+		spl_scratch->scl_data.taps.v_taps_c = 1;
+
 }
 
 /* Calculate optimal number of taps */
@@ -936,10 +946,7 @@ static bool spl_get_optimal_number_of_taps(
 
 	/* Disable adaptive scaler and sharpener when integer scaling is enabled */
 	if (spl_in->scaling_quality.integer_scaling) {
-		spl_scratch->scl_data.taps.h_taps = 1;
-		spl_scratch->scl_data.taps.v_taps = 1;
-		spl_scratch->scl_data.taps.v_taps_c = 1;
-		spl_scratch->scl_data.taps.h_taps_c = 1;
+		spl_get_taps_non_adaptive_scaler(spl_scratch, in_taps);
 		*enable_easf_v = false;
 		*enable_easf_h = false;
 		*enable_isharp = false;
-- 
2.46.1

[PATCH 10/16] drm/amd/display: Use region6 size in fw_meta_info

[Hamza Mahfooz]

From: JinZe Xu <jinze.xu@amd.com>

[Why]
If driver allocated region6 size is not same as the size in firmware,
dmcub won't enable region6.

[How]
Use region6 size in dmcub_fw_meta instead of a constant value.

Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: JinZe Xu <jinze.xu@amd.com>
Signed-off-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
---
 drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
index db16066bc893..a3f3ff5d49ac 100644
--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
+++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
@@ -497,6 +497,7 @@ enum dmub_status
 	const struct dmub_fw_meta_info *fw_info;
 	uint32_t fw_state_size = DMUB_FW_STATE_SIZE;
 	uint32_t trace_buffer_size = DMUB_TRACE_BUFFER_SIZE;
+	uint32_t shared_state_size = DMUB_FW_HEADER_SHARED_STATE_SIZE;
 	uint32_t window_sizes[DMUB_WINDOW_TOTAL] = { 0 };
 
 	if (!dmub->sw_init)
@@ -514,6 +515,7 @@ enum dmub_status
 
 		fw_state_size = fw_info->fw_region_size;
 		trace_buffer_size = fw_info->trace_buffer_size;
+		shared_state_size = fw_info->shared_state_size;
 
 		/**
 		 * If DM didn't fill in a version, then fill it in based on
@@ -534,7 +536,7 @@ enum dmub_status
 	window_sizes[DMUB_WINDOW_5_TRACEBUFF] = trace_buffer_size;
 	window_sizes[DMUB_WINDOW_6_FW_STATE] = fw_state_size;
 	window_sizes[DMUB_WINDOW_7_SCRATCH_MEM] = DMUB_SCRATCH_MEM_SIZE;
-	window_sizes[DMUB_WINDOW_SHARED_STATE] = DMUB_FW_HEADER_SHARED_STATE_SIZE;
+	window_sizes[DMUB_WINDOW_SHARED_STATE] = max(DMUB_FW_HEADER_SHARED_STATE_SIZE, shared_state_size);
 
 	out->fb_size =
 		dmub_srv_calc_regions_for_memory_type(params, out, window_sizes, DMUB_WINDOW_MEMORY_TYPE_FB);
-- 
2.46.1

[PATCH 11/16] drm/amd/display: Handle dml allocation failure to avoid crash

[Hamza Mahfooz]

From: Ryan Seto <ryanseto@amd.com>

[Why]
In the case where a dml allocation fails for any reason, the
current state's dml contexts would no longer be valid. Then
subsequent calls dc_state_copy_internal would shallow copy
invalid memory and if the new state was released, a double
free would occur.

[How]
Reset dml pointers in new_state to NULL and avoid invalid
pointer

Cc: stable@vger.kernel.org
Reviewed-by: Dillon Varone <dillon.varone@amd.com>
Signed-off-by: Ryan Seto <ryanseto@amd.com>
Signed-off-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc_state.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_state.c b/drivers/gpu/drm/amd/display/dc/core/dc_state.c
index 2597e3fd562b..e006f816ff2f 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_state.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_state.c
@@ -265,6 +265,9 @@ struct dc_state *dc_state_create_copy(struct dc_state *src_state)
 	dc_state_copy_internal(new_state, src_state);
 
 #ifdef CONFIG_DRM_AMD_DC_FP
+	new_state->bw_ctx.dml2 = NULL;
+	new_state->bw_ctx.dml2_dc_power_source = NULL;
+
 	if (src_state->bw_ctx.dml2 &&
 			!dml2_create_copy(&new_state->bw_ctx.dml2, src_state->bw_ctx.dml2)) {
 		dc_state_release(new_state);
-- 
2.46.1

[PATCH 12/16] drm/amd/display: Require minimum VBlank size for stutter optimization

[Hamza Mahfooz]

From: Dillon Varone <dillon.varone@amd.com>

If the nominal VBlank is too small, optimizing for stutter can cause
the prefetch bandwidth to increase drasticaly, resulting in higher
clock and power requirements. Only optimize if it is >3x the stutter
latency.

Cc: stable@vger.kernel.org
Reviewed-by: Austin Zheng <austin.zheng@amd.com>
Signed-off-by: Dillon Varone <dillon.varone@amd.com>
Signed-off-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
---
 .../dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c  | 11 +++++++++--
 1 file changed, 9 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c b/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
index 5a09dd298e6f..92269f0e50ed 100644
--- a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
+++ b/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
@@ -8,6 +8,7 @@
 #include "dml2_pmo_dcn4_fams2.h"
 
 static const double MIN_VACTIVE_MARGIN_PCT = 0.25; // We need more than non-zero margin because DET buffer granularity can alter vactive latency hiding
+static const double MIN_BLANK_STUTTER_FACTOR = 3.0;
 
 static const struct dml2_pmo_pstate_strategy base_strategy_list_1_display[] = {
 	// VActive Preferred
@@ -2140,6 +2141,7 @@ bool pmo_dcn4_fams2_init_for_stutter(struct dml2_pmo_init_for_stutter_in_out *in
 	struct dml2_pmo_instance *pmo = in_out->instance;
 	bool stutter_period_meets_z8_eco = true;
 	bool z8_stutter_optimization_too_expensive = false;
+	bool stutter_optimization_too_expensive = false;
 	double line_time_us, vblank_nom_time_us;
 
 	unsigned int i;
@@ -2161,10 +2163,15 @@ bool pmo_dcn4_fams2_init_for_stutter(struct dml2_pmo_init_for_stutter_in_out *in
 		line_time_us = (double)in_out->base_display_config->display_config.stream_descriptors[i].timing.h_total / (in_out->base_display_config->display_config.stream_descriptors[i].timing.pixel_clock_khz * 1000) * 1000000;
 		vblank_nom_time_us = line_time_us * in_out->base_display_config->display_config.stream_descriptors[i].timing.vblank_nom;
 
-		if (vblank_nom_time_us < pmo->soc_bb->power_management_parameters.z8_stutter_exit_latency_us) {
+		if (vblank_nom_time_us < pmo->soc_bb->power_management_parameters.z8_stutter_exit_latency_us * MIN_BLANK_STUTTER_FACTOR) {
 			z8_stutter_optimization_too_expensive = true;
 			break;
 		}
+
+		if (vblank_nom_time_us < pmo->soc_bb->power_management_parameters.stutter_enter_plus_exit_latency_us * MIN_BLANK_STUTTER_FACTOR) {
+			stutter_optimization_too_expensive = true;
+			break;
+		}
 	}
 
 	pmo->scratch.pmo_dcn4.num_stutter_candidates = 0;
@@ -2180,7 +2187,7 @@ bool pmo_dcn4_fams2_init_for_stutter(struct dml2_pmo_init_for_stutter_in_out *in
 		pmo->scratch.pmo_dcn4.z8_vblank_optimizable = false;
 	}
 
-	if (pmo->soc_bb->power_management_parameters.stutter_enter_plus_exit_latency_us > 0) {
+	if (!stutter_optimization_too_expensive && pmo->soc_bb->power_management_parameters.stutter_enter_plus_exit_latency_us > 0) {
 		pmo->scratch.pmo_dcn4.optimal_vblank_reserved_time_for_stutter_us[pmo->scratch.pmo_dcn4.num_stutter_candidates] = (unsigned int)pmo->soc_bb->power_management_parameters.stutter_enter_plus_exit_latency_us;
 		pmo->scratch.pmo_dcn4.num_stutter_candidates++;
 	}
-- 
2.46.1

[PATCH 13/16] drm/amd/display: update pipe selection policy to check head pipe

[Hamza Mahfooz]

From: Yihan Zhu <Yihan.Zhu@amd.com>

[Why]
No check on head pipe during the dml to dc hw mapping will allow illegal
pipe usage. This will result in a wrong pipe topology to cause mpcc tree
totally mess up then cause a display hang.

[How]
Avoid to use the pipe is head in all check and avoid ODM slice during
preferred pipe check.

Cc: stable@vger.kernel.org
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Yihan Zhu <Yihan.Zhu@amd.com>
Signed-off-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
---
 .../display/dc/dml2/dml2_dc_resource_mgmt.c   | 19 ++++++++++++++++++-
 1 file changed, 18 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c b/drivers/gpu/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c
index 6eccf0241d85..9be9ed7e01d3 100644
--- a/drivers/gpu/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c
+++ b/drivers/gpu/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c
@@ -258,12 +258,23 @@ static unsigned int find_preferred_pipe_candidates(const struct dc_state *existi
 	 * However this condition comes with a caveat. We need to ignore pipes that will
 	 * require a change in OPP but still have the same stream id. For example during
 	 * an MPC to ODM transiton.
+	 *
+	 * Adding check to avoid pipe select on the head pipe by utilizing dc resource
+	 * helper function resource_get_primary_dpp_pipe and comparing the pipe index.
 	 */
 	if (existing_state) {
 		for (i = 0; i < pipe_count; i++) {
 			if (existing_state->res_ctx.pipe_ctx[i].stream && existing_state->res_ctx.pipe_ctx[i].stream->stream_id == stream_id) {
+				struct pipe_ctx *head_pipe =
+					resource_get_primary_dpp_pipe(&existing_state->res_ctx.pipe_ctx[i]);
+
+				// we should always respect the head pipe from selection
+				if (head_pipe && head_pipe->pipe_idx == i)
+					continue;
 				if (existing_state->res_ctx.pipe_ctx[i].plane_res.hubp &&
-					existing_state->res_ctx.pipe_ctx[i].plane_res.hubp->opp_id != i)
+					existing_state->res_ctx.pipe_ctx[i].plane_res.hubp->opp_id != i &&
+						(existing_state->res_ctx.pipe_ctx[i].prev_odm_pipe ||
+						existing_state->res_ctx.pipe_ctx[i].next_odm_pipe))
 					continue;
 
 				preferred_pipe_candidates[num_preferred_candidates++] = i;
@@ -292,6 +303,12 @@ static unsigned int find_last_resort_pipe_candidates(const struct dc_state *exis
 	 */
 	if (existing_state) {
 		for (i  = 0; i < pipe_count; i++) {
+			struct pipe_ctx *head_pipe =
+				resource_get_primary_dpp_pipe(&existing_state->res_ctx.pipe_ctx[i]);
+
+			// we should always respect the head pipe from selection
+			if (head_pipe && head_pipe->pipe_idx == i)
+				continue;
 			if ((existing_state->res_ctx.pipe_ctx[i].plane_res.hubp &&
 				existing_state->res_ctx.pipe_ctx[i].plane_res.hubp->opp_id != i) ||
 				existing_state->res_ctx.pipe_ctx[i].stream_res.tg)
-- 
2.46.1

[PATCH 14/16] drm/amd/display: Remove unused code

[Hamza Mahfooz]

From: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>

This commit removes a legacy debug_defaults_diags struct.

Reviewed-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
---
 .../amd/display/dc/resource/dcn10/dcn10_resource.c  | 13 -------------
 1 file changed, 13 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c
index 4f1bd71b9ad9..770a380cc03d 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c
@@ -559,17 +559,6 @@ static const struct dc_debug_options debug_defaults_drv = {
 		.using_dml2 = false,
 };
 
-static const struct dc_debug_options debug_defaults_diags = {
-		.disable_dmcu = false,
-		.force_abm_enable = false,
-		.clock_trace = true,
-		.disable_stutter = true,
-		.disable_pplib_clock_request = true,
-		.disable_pplib_wm_range = true,
-		.underflow_assert_delay_us = 0xFFFFFFFF,
-		.enable_legacy_fast_update = true,
-};
-
 static void dcn10_dpp_destroy(struct dpp **dpp)
 {
 	kfree(TO_DCN10_DPP(*dpp));
@@ -1398,8 +1387,6 @@ static bool dcn10_resource_construct(
 
 	if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
 		dc->debug = debug_defaults_drv;
-	else
-		dc->debug = debug_defaults_diags;
 
 	/*************************************************
 	 *  Create resources                             *
-- 
2.46.1

[PATCH 15/16] drm/amd/display: Adjust VSDB parser for replay feature

[Hamza Mahfooz]

From: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>

At some point, the IEEE ID identification for the replay check in the
AMD EDID was added. However, this check causes the following
out-of-bounds issues when using KASAN:

[   27.804016] BUG: KASAN: slab-out-of-bounds in amdgpu_dm_update_freesync_caps+0xefa/0x17a0 [amdgpu]
[   27.804788] Read of size 1 at addr ffff8881647fdb00 by task systemd-udevd/383

...

[   27.821207] Memory state around the buggy address:
[   27.821215]  ffff8881647fda00: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
[   27.821224]  ffff8881647fda80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
[   27.821234] >ffff8881647fdb00: fc fc fc fc fc fc fc fc fc fc fc fc fc fc fc fc
[   27.821243]                    ^
[   27.821250]  ffff8881647fdb80: fc fc fc fc fc fc fc fc fc fc fc fc fc fc fc fc
[   27.821259]  ffff8881647fdc00: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
[   27.821268] ==================================================================

This is caused because the ID extraction happens outside of the range of
the edid lenght. This commit addresses this issue by considering the
amd_vsdb_block size.

Cc: ChiaHsuan Chung <chiahsuan.chung@amd.com>
Reviewed-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 1d47719e7af1..8381afbe6e4d 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -12096,7 +12096,7 @@ static int parse_amd_vsdb(struct amdgpu_dm_connector *aconnector,
 			break;
 	}
 
-	while (j < EDID_LENGTH) {
+	while (j < EDID_LENGTH - sizeof(struct amd_vsdb_block)) {
 		struct amd_vsdb_block *amd_vsdb = (struct amd_vsdb_block *)&edid_ext[j];
 		unsigned int ieeeId = (amd_vsdb->ieee_id[2] << 16) | (amd_vsdb->ieee_id[1] << 8) | (amd_vsdb->ieee_id[0]);
 
-- 
2.46.1

[PATCH 16/16] drm/amd/display: 3.2.309

[Hamza Mahfooz]

From: Aric Cyr <aric.cyr@amd.com>

This version brings along the following:

- DML2 fixes
- DP fixes
- DPMS fix
- HPD fixes
- Misc cleanup
- ODM fix
- Replay fix
- SPL fix

Reviewed-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Aric Cyr <aric.cyr@amd.com>
Signed-off-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dc.h           |  2 +-
 .../amd/display/dc/hwss/dcn31/dcn31_hwseq.c   |  3 +-
 .../gpu/drm/amd/display/dmub/inc/dmub_cmd.h   | 35 +++++++++++++++----
 3 files changed, 32 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index ad9ce3d0bfcf..e143fab00a86 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -55,7 +55,7 @@ struct aux_payload;
 struct set_config_cmd_payload;
 struct dmub_notification;
 
-#define DC_VER "3.2.308"
+#define DC_VER "3.2.309"
 
 #define MAX_SURFACES 3
 #define MAX_PLANES 6
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c
index 59b2e87317e3..03ba01f4ace1 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c
@@ -653,7 +653,8 @@ static void dmub_abm_set_backlight(struct dc_context *dc,
 	cmd.abm_set_backlight.header.sub_type = DMUB_CMD__ABM_SET_BACKLIGHT;
 	cmd.abm_set_backlight.abm_set_backlight_data.frame_ramp = backlight_level_params->frame_ramp;
 	cmd.abm_set_backlight.abm_set_backlight_data.backlight_user_level = backlight_level_params->backlight_pwm_u16_16;
-	cmd.abm_set_backlight.abm_set_backlight_data.backlight_control_type = backlight_level_params->control_type;
+	cmd.abm_set_backlight.abm_set_backlight_data.backlight_control_type =
+		(enum dmub_backlight_control_type) backlight_level_params->control_type;
 	cmd.abm_set_backlight.abm_set_backlight_data.min_luminance = backlight_level_params->min_luminance;
 	cmd.abm_set_backlight.abm_set_backlight_data.max_luminance = backlight_level_params->max_luminance;
 	cmd.abm_set_backlight.abm_set_backlight_data.min_backlight_pwm = backlight_level_params->min_backlight_pwm;
diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
index a9b90fa00b88..b800a507d1e0 100644
--- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
+++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
@@ -4426,6 +4426,24 @@ struct dmub_rb_cmd_abm_set_pipe {
 	struct dmub_cmd_abm_set_pipe_data abm_set_pipe_data;
 };
 
+/**
+ * Type of backlight control method to be used by ABM module
+ */
+enum dmub_backlight_control_type {
+	/**
+	 * PWM Backlight control
+	 */
+	DMU_BACKLIGHT_CONTROL_PWM = 0,
+	/**
+	 * VESA Aux-based backlight control
+	 */
+	DMU_BACKLIGHT_CONTROL_VESA_AUX = 1,
+	/**
+	 * AMD DPCD Aux-based backlight control
+	 */
+	DMU_BACKLIGHT_CONTROL_AMD_AUX = 2,
+};
+
 /**
  * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command.
  */
@@ -4452,18 +4470,23 @@ struct dmub_cmd_abm_set_backlight_data {
 	 */
 	uint8_t panel_mask;
 
+	/**
+	 * AUX HW Instance.
+	 */
+	uint8_t aux_inst;
+
+	/**
+	 * Explicit padding to 4 byte boundary.
+	 */
+	uint8_t pad[1];
+
 	/**
 	 * Backlight control type.
 	 * Value 0 is PWM backlight control.
 	 * Value 1 is VAUX backlight control.
 	 * Value 2 is AMD DPCD AUX backlight control.
 	 */
-	uint8_t backlight_control_type;
-
-	/**
-	 * AUX HW instance.
-	 */
-	uint8_t aux_inst;
+	enum dmub_backlight_control_type backlight_control_type;
 
 	/**
 	 * Minimum luminance in nits.
-- 
2.46.1