From: "Christian König" <ckoenig.leichtzumerken@gmail.com>
To: YuBiao Wang <YuBiao.Wang@amd.com>, amd-gfx@lists.freedesktop.org
Cc: "Andrey Grodzovsky" <Andrey.Grodzovsky@amd.com>,
"Jack Xiao" <Jack.Xiao@amd.com>, "Feifei Xu" <Feifei.Xu@amd.com>,
horace.chen@amd.com, "Kevin Wang" <Kevin1.Wang@amd.com>,
"Christian König" <christian.koenig@amd.com>,
"Tuikov Luben" <Luben.Tuikov@amd.com>,
"Deucher Alexander" <Alexander.Deucher@amd.com>,
"Evan Quan" <Evan.Quan@amd.com>,
"Jingwen Chen" <Jingwen.Chen2@amd.com>,
"Monk Liu" <Monk.Liu@amd.com>,
"Hawking Zhang" <Hawking.Zhang@amd.com>
Subject: Re: [PATCH] drm/amd/amdgpu: Avoid writing GMC registers under sriov in gmc9
Date: Tue, 2 Nov 2021 12:10:54 +0100 [thread overview]
Message-ID: <9a5c58de-ef3d-a3ee-0f7e-393bd7d239da@gmail.com> (raw)
In-Reply-To: <20211102102500.109229-1-YuBiao.Wang@amd.com>
Am 02.11.21 um 11:25 schrieb YuBiao Wang:
> [Why]
> For Vega10, disabling gart of gfxhub and mmhub could mess up KIQ and PSP under sriov mode, and lead to DMAR on host side.
>
> [How]
> Do not call gmc_gart_disable under sriov but keep vram_unpin to avoid
> pin_count leak.
NAK, if you want to do this you should probably avoid the write in the
low level hardware callbacks and not here.
Christian.
>
> Signed-off-by: YuBiao Wang <YuBiao.Wang@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> index cb82404df534..365059a20ae8 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> @@ -1793,14 +1793,13 @@ static void gmc_v9_0_gart_disable(struct amdgpu_device *adev)
> {
> adev->gfxhub.funcs->gart_disable(adev);
> adev->mmhub.funcs->gart_disable(adev);
> - amdgpu_gart_table_vram_unpin(adev);
> }
>
> static int gmc_v9_0_hw_fini(void *handle)
> {
> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>
> - gmc_v9_0_gart_disable(adev);
> + amdgpu_gart_table_vram_unpin(adev);
>
> if (amdgpu_sriov_vf(adev)) {
> /* full access mode, so don't touch any GMC register */
> @@ -1808,6 +1807,7 @@ static int gmc_v9_0_hw_fini(void *handle)
> return 0;
> }
>
> + gmc_v9_0_gart_disable(adev);
> amdgpu_irq_put(adev, &adev->gmc.ecc_irq, 0);
> amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0);
>
next prev parent reply other threads:[~2021-11-02 11:10 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-11-02 10:25 [PATCH] drm/amd/amdgpu: Avoid writing GMC registers under sriov in gmc9 YuBiao Wang
2021-11-02 11:10 ` Christian König [this message]
-- strict thread matches above, loose matches on Subject: below --
2021-11-04 2:55 YuBiao Wang
2021-11-04 7:49 ` Christian König
2021-11-04 7:58 ` Christian König
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=9a5c58de-ef3d-a3ee-0f7e-393bd7d239da@gmail.com \
--to=ckoenig.leichtzumerken@gmail.com \
--cc=Alexander.Deucher@amd.com \
--cc=Andrey.Grodzovsky@amd.com \
--cc=Evan.Quan@amd.com \
--cc=Feifei.Xu@amd.com \
--cc=Hawking.Zhang@amd.com \
--cc=Jack.Xiao@amd.com \
--cc=Jingwen.Chen2@amd.com \
--cc=Kevin1.Wang@amd.com \
--cc=Luben.Tuikov@amd.com \
--cc=Monk.Liu@amd.com \
--cc=YuBiao.Wang@amd.com \
--cc=amd-gfx@lists.freedesktop.org \
--cc=christian.koenig@amd.com \
--cc=horace.chen@amd.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox