* [PATCH] drm/amd/amdgpu: Avoid writing GMC registers under sriov in gmc9
@ 2021-11-02 10:25 YuBiao Wang
2021-11-02 11:10 ` Christian König
0 siblings, 1 reply; 5+ messages in thread
From: YuBiao Wang @ 2021-11-02 10:25 UTC (permalink / raw)
To: amd-gfx
Cc: YuBiao Wang, Andrey Grodzovsky, Jack Xiao, Feifei Xu, horace.chen,
Kevin Wang, Tuikov Luben, Deucher Alexander, Jingwen Chen,
Evan Quan, Christian König, Monk Liu, Hawking Zhang
[Why]
For Vega10, disabling gart of gfxhub and mmhub could mess up KIQ and PSP under sriov mode, and lead to DMAR on host side.
[How]
Do not call gmc_gart_disable under sriov but keep vram_unpin to avoid
pin_count leak.
Signed-off-by: YuBiao Wang <YuBiao.Wang@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index cb82404df534..365059a20ae8 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -1793,14 +1793,13 @@ static void gmc_v9_0_gart_disable(struct amdgpu_device *adev)
{
adev->gfxhub.funcs->gart_disable(adev);
adev->mmhub.funcs->gart_disable(adev);
- amdgpu_gart_table_vram_unpin(adev);
}
static int gmc_v9_0_hw_fini(void *handle)
{
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- gmc_v9_0_gart_disable(adev);
+ amdgpu_gart_table_vram_unpin(adev);
if (amdgpu_sriov_vf(adev)) {
/* full access mode, so don't touch any GMC register */
@@ -1808,6 +1807,7 @@ static int gmc_v9_0_hw_fini(void *handle)
return 0;
}
+ gmc_v9_0_gart_disable(adev);
amdgpu_irq_put(adev, &adev->gmc.ecc_irq, 0);
amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0);
--
2.25.1
^ permalink raw reply related [flat|nested] 5+ messages in thread* Re: [PATCH] drm/amd/amdgpu: Avoid writing GMC registers under sriov in gmc9
2021-11-02 10:25 [PATCH] drm/amd/amdgpu: Avoid writing GMC registers under sriov in gmc9 YuBiao Wang
@ 2021-11-02 11:10 ` Christian König
0 siblings, 0 replies; 5+ messages in thread
From: Christian König @ 2021-11-02 11:10 UTC (permalink / raw)
To: YuBiao Wang, amd-gfx
Cc: Andrey Grodzovsky, Jack Xiao, Feifei Xu, horace.chen, Kevin Wang,
Christian König, Tuikov Luben, Deucher Alexander, Evan Quan,
Jingwen Chen, Monk Liu, Hawking Zhang
Am 02.11.21 um 11:25 schrieb YuBiao Wang:
> [Why]
> For Vega10, disabling gart of gfxhub and mmhub could mess up KIQ and PSP under sriov mode, and lead to DMAR on host side.
>
> [How]
> Do not call gmc_gart_disable under sriov but keep vram_unpin to avoid
> pin_count leak.
NAK, if you want to do this you should probably avoid the write in the
low level hardware callbacks and not here.
Christian.
>
> Signed-off-by: YuBiao Wang <YuBiao.Wang@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> index cb82404df534..365059a20ae8 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> @@ -1793,14 +1793,13 @@ static void gmc_v9_0_gart_disable(struct amdgpu_device *adev)
> {
> adev->gfxhub.funcs->gart_disable(adev);
> adev->mmhub.funcs->gart_disable(adev);
> - amdgpu_gart_table_vram_unpin(adev);
> }
>
> static int gmc_v9_0_hw_fini(void *handle)
> {
> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>
> - gmc_v9_0_gart_disable(adev);
> + amdgpu_gart_table_vram_unpin(adev);
>
> if (amdgpu_sriov_vf(adev)) {
> /* full access mode, so don't touch any GMC register */
> @@ -1808,6 +1807,7 @@ static int gmc_v9_0_hw_fini(void *handle)
> return 0;
> }
>
> + gmc_v9_0_gart_disable(adev);
> amdgpu_irq_put(adev, &adev->gmc.ecc_irq, 0);
> amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0);
>
^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH] drm/amd/amdgpu: Avoid writing GMC registers under sriov in gmc9
@ 2021-11-04 2:55 YuBiao Wang
2021-11-04 7:49 ` Christian König
0 siblings, 1 reply; 5+ messages in thread
From: YuBiao Wang @ 2021-11-04 2:55 UTC (permalink / raw)
To: amd-gfx
Cc: YuBiao Wang, Andrey Grodzovsky, Jack Xiao, Feifei Xu, horace.chen,
Kevin Wang, Tuikov Luben, Deucher Alexander, Jingwen Chen,
Evan Quan, Christian König, Monk Liu, Hawking Zhang
[Why]
For Vega10, disabling gart of gfxhub and mmhub could mess up KIQ and PSP
under sriov mode, and lead to DMAR on host side.
[How]
Skip writing GMC registers under sriov.
Signed-off-by: YuBiao Wang <YuBiao.Wang@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | 26 +++++++++++++-----------
1 file changed, 14 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
index bda1542ef1dd..f9a7349eb601 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
@@ -348,18 +348,20 @@ static void gfxhub_v1_0_gart_disable(struct amdgpu_device *adev)
WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT0_CNTL,
i * hub->ctx_distance, 0);
- /* Setup TLB control */
- tmp = RREG32_SOC15(GC, 0, mmMC_VM_MX_L1_TLB_CNTL);
- tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
- tmp = REG_SET_FIELD(tmp,
- MC_VM_MX_L1_TLB_CNTL,
- ENABLE_ADVANCED_DRIVER_MODEL,
- 0);
- WREG32_SOC15_RLC(GC, 0, mmMC_VM_MX_L1_TLB_CNTL, tmp);
-
- /* Setup L2 cache */
- WREG32_FIELD15(GC, 0, VM_L2_CNTL, ENABLE_L2_CACHE, 0);
- WREG32_SOC15(GC, 0, mmVM_L2_CNTL3, 0);
+ if (!amdgpu_sriov_vf(adev)) {
+ /* Setup TLB control */
+ tmp = RREG32_SOC15(GC, 0, mmMC_VM_MX_L1_TLB_CNTL);
+ tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
+ tmp = REG_SET_FIELD(tmp,
+ MC_VM_MX_L1_TLB_CNTL,
+ ENABLE_ADVANCED_DRIVER_MODEL,
+ 0);
+ WREG32_SOC15_RLC(GC, 0, mmMC_VM_MX_L1_TLB_CNTL, tmp);
+
+ /* Setup L2 cache */
+ WREG32_FIELD15(GC, 0, VM_L2_CNTL, ENABLE_L2_CACHE, 0);
+ WREG32_SOC15(GC, 0, mmVM_L2_CNTL3, 0);
+ }
}
/**
--
2.25.1
^ permalink raw reply related [flat|nested] 5+ messages in thread* Re: [PATCH] drm/amd/amdgpu: Avoid writing GMC registers under sriov in gmc9
2021-11-04 2:55 YuBiao Wang
@ 2021-11-04 7:49 ` Christian König
2021-11-04 7:58 ` Christian König
0 siblings, 1 reply; 5+ messages in thread
From: Christian König @ 2021-11-04 7:49 UTC (permalink / raw)
To: YuBiao Wang, amd-gfx
Cc: Andrey Grodzovsky, Jack Xiao, Feifei Xu, horace.chen, Kevin Wang,
Tuikov Luben, Deucher Alexander, Evan Quan, Jingwen Chen,
Monk Liu, Hawking Zhang
Am 04.11.21 um 03:55 schrieb YuBiao Wang:
> [Why]
> For Vega10, disabling gart of gfxhub and mmhub could mess up KIQ and PSP
> under sriov mode, and lead to DMAR on host side.
>
> [How]
> Skip writing GMC registers under sriov.
>
> Signed-off-by: YuBiao Wang <YuBiao.Wang@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | 26 +++++++++++++-----------
> 1 file changed, 14 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
> index bda1542ef1dd..f9a7349eb601 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
> @@ -348,18 +348,20 @@ static void gfxhub_v1_0_gart_disable(struct amdgpu_device *adev)
> WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT0_CNTL,
> i * hub->ctx_distance, 0);
>
> - /* Setup TLB control */
> - tmp = RREG32_SOC15(GC, 0, mmMC_VM_MX_L1_TLB_CNTL);
> - tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
> - tmp = REG_SET_FIELD(tmp,
> - MC_VM_MX_L1_TLB_CNTL,
> - ENABLE_ADVANCED_DRIVER_MODEL,
> - 0);
> - WREG32_SOC15_RLC(GC, 0, mmMC_VM_MX_L1_TLB_CNTL, tmp);
> -
> - /* Setup L2 cache */
> - WREG32_FIELD15(GC, 0, VM_L2_CNTL, ENABLE_L2_CACHE, 0);
> - WREG32_SOC15(GC, 0, mmVM_L2_CNTL3, 0);
> + if (!amdgpu_sriov_vf(adev)) {
Maybe make that an "if (amdgpu_sriov_vf(adev)) return", but in general
feel free to add an Acked-by: Christian König <christian.koenig@amd.com>
to the patch.
Additional to that the patch should probably be send to the public
mailing list instead.
Regards,
Christian.
> + /* Setup TLB control */
> + tmp = RREG32_SOC15(GC, 0, mmMC_VM_MX_L1_TLB_CNTL);
> + tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
> + tmp = REG_SET_FIELD(tmp,
> + MC_VM_MX_L1_TLB_CNTL,
> + ENABLE_ADVANCED_DRIVER_MODEL,
> + 0);
> + WREG32_SOC15_RLC(GC, 0, mmMC_VM_MX_L1_TLB_CNTL, tmp);
> +
> + /* Setup L2 cache */
> + WREG32_FIELD15(GC, 0, VM_L2_CNTL, ENABLE_L2_CACHE, 0);
> + WREG32_SOC15(GC, 0, mmVM_L2_CNTL3, 0);
> + }
> }
>
> /**
^ permalink raw reply [flat|nested] 5+ messages in thread* Re: [PATCH] drm/amd/amdgpu: Avoid writing GMC registers under sriov in gmc9
2021-11-04 7:49 ` Christian König
@ 2021-11-04 7:58 ` Christian König
0 siblings, 0 replies; 5+ messages in thread
From: Christian König @ 2021-11-04 7:58 UTC (permalink / raw)
To: YuBiao Wang, amd-gfx
Cc: Andrey Grodzovsky, Jack Xiao, Feifei Xu, horace.chen, Kevin Wang,
Tuikov Luben, Deucher Alexander, Evan Quan, Jingwen Chen,
Monk Liu, Hawking Zhang
Am 04.11.21 um 08:49 schrieb Christian König:
>
>
> Am 04.11.21 um 03:55 schrieb YuBiao Wang:
>> [Why]
>> For Vega10, disabling gart of gfxhub and mmhub could mess up KIQ and PSP
>> under sriov mode, and lead to DMAR on host side.
>>
>> [How]
>> Skip writing GMC registers under sriov.
>>
>> Signed-off-by: YuBiao Wang <YuBiao.Wang@amd.com>
>> ---
>> drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | 26 +++++++++++++-----------
>> 1 file changed, 14 insertions(+), 12 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
>> b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
>> index bda1542ef1dd..f9a7349eb601 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
>> @@ -348,18 +348,20 @@ static void gfxhub_v1_0_gart_disable(struct
>> amdgpu_device *adev)
>> WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT0_CNTL,
>> i * hub->ctx_distance, 0);
>> - /* Setup TLB control */
>> - tmp = RREG32_SOC15(GC, 0, mmMC_VM_MX_L1_TLB_CNTL);
>> - tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
>> - tmp = REG_SET_FIELD(tmp,
>> - MC_VM_MX_L1_TLB_CNTL,
>> - ENABLE_ADVANCED_DRIVER_MODEL,
>> - 0);
>> - WREG32_SOC15_RLC(GC, 0, mmMC_VM_MX_L1_TLB_CNTL, tmp);
>> -
>> - /* Setup L2 cache */
>> - WREG32_FIELD15(GC, 0, VM_L2_CNTL, ENABLE_L2_CACHE, 0);
>> - WREG32_SOC15(GC, 0, mmVM_L2_CNTL3, 0);
>> + if (!amdgpu_sriov_vf(adev)) {
>
> Maybe make that an "if (amdgpu_sriov_vf(adev)) return", but in general
> feel free to add an Acked-by: Christian König
> <christian.koenig@amd.com> to the patch.
>
> Additional to that the patch should probably be send to the public
> mailing list instead.
Please forget that last comment, just noticed the public list is on CC
as well.
Thanks,
Christian.
>
> Regards,
> Christian.
>
>> + /* Setup TLB control */
>> + tmp = RREG32_SOC15(GC, 0, mmMC_VM_MX_L1_TLB_CNTL);
>> + tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
>> ENABLE_L1_TLB, 0);
>> + tmp = REG_SET_FIELD(tmp,
>> + MC_VM_MX_L1_TLB_CNTL,
>> + ENABLE_ADVANCED_DRIVER_MODEL,
>> + 0);
>> + WREG32_SOC15_RLC(GC, 0, mmMC_VM_MX_L1_TLB_CNTL, tmp);
>> +
>> + /* Setup L2 cache */
>> + WREG32_FIELD15(GC, 0, VM_L2_CNTL, ENABLE_L2_CACHE, 0);
>> + WREG32_SOC15(GC, 0, mmVM_L2_CNTL3, 0);
>> + }
>> }
>> /**
>
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2021-11-04 7:58 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2021-11-02 10:25 [PATCH] drm/amd/amdgpu: Avoid writing GMC registers under sriov in gmc9 YuBiao Wang
2021-11-02 11:10 ` Christian König
-- strict thread matches above, loose matches on Subject: below --
2021-11-04 2:55 YuBiao Wang
2021-11-04 7:49 ` Christian König
2021-11-04 7:58 ` Christian König
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox