[PATCH 1/3] drm/amdgpu: convert to NBIO IP version checking

[PATCH 1/3] drm/amdgpu: convert to NBIO IP version checking

[Tim Huang]

Use IP versions rather than asic_type to differentiate IP version specific features.

Signed-off-by: Tim Huang <xiaohu.huang@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/nbio_v7_2.c | 48 ++++++++++++++++++--------
 1 file changed, 34 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_2.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_2.c
index 3444332ea110..70e341d884d5 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_2.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_2.c
@@ -59,10 +59,15 @@ static u32 nbio_v7_2_get_rev_id(struct amdgpu_device *adev)
 {
 	u32 tmp;
 
-	if (adev->asic_type == CHIP_YELLOW_CARP)
+	switch (adev->ip_versions[NBIO_HWIP][0]) {
+	case IP_VERSION(7, 2, 1):
+	case IP_VERSION(7, 5, 0):
 		tmp = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0_YC);
-	else
+		break;
+	default:
 		tmp = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0);
+		break;
+	}
 
 	tmp &= RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK;
 	tmp >>= RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT;
@@ -72,20 +77,25 @@ static u32 nbio_v7_2_get_rev_id(struct amdgpu_device *adev)
 
 static void nbio_v7_2_mc_access_enable(struct amdgpu_device *adev, bool enable)
 {
-	if (enable)
-		if (adev->asic_type == CHIP_YELLOW_CARP)
+	switch (adev->ip_versions[NBIO_HWIP][0]) {
+	case IP_VERSION(7, 2, 1):
+	case IP_VERSION(7, 5, 0):
+		if (enable)
 			WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_FB_EN_YC,
 				BIF_BX0_BIF_FB_EN__FB_READ_EN_MASK |
 				BIF_BX0_BIF_FB_EN__FB_WRITE_EN_MASK);
 		else
+			WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_FB_EN_YC, 0);
+	break;
+	default:
+		if (enable)
 			WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_FB_EN,
 				BIF_BX0_BIF_FB_EN__FB_READ_EN_MASK |
 				BIF_BX0_BIF_FB_EN__FB_WRITE_EN_MASK);
-	else
-		if (adev->asic_type == CHIP_YELLOW_CARP)
-			WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_FB_EN_YC, 0);
 		else
 			WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_FB_EN, 0);
+		break;
+	}
 }
 
 static u32 nbio_v7_2_get_memsize(struct amdgpu_device *adev)
@@ -249,8 +259,10 @@ static void nbio_v7_2_update_medium_grain_light_sleep(struct amdgpu_device *adev
 						      bool enable)
 {
 	uint32_t def, data;
-
-	if (adev->asic_type == CHIP_YELLOW_CARP) {
+	
+	switch (adev->ip_versions[NBIO_HWIP][0]) {
+	case IP_VERSION(7, 2, 1):
+	case IP_VERSION(7, 5, 0):
 		def = data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CNTL2));
 		if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS))
 			data |= PCIE_CNTL2__SLV_MEM_LS_EN_MASK;
@@ -260,8 +272,8 @@ static void nbio_v7_2_update_medium_grain_light_sleep(struct amdgpu_device *adev
 		if (def != data)
 			WREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CNTL2), data);
 
-		data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regBIF1_PCIE_TX_POWER_CTRL_1));
-		def = data;
+		def = data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, 
+			regBIF1_PCIE_TX_POWER_CTRL_1));
 		if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS))
 			data |= (BIF1_PCIE_TX_POWER_CTRL_1__MST_MEM_LS_EN_MASK |
 				BIF1_PCIE_TX_POWER_CTRL_1__REPLAY_MEM_LS_EN_MASK);
@@ -272,7 +284,8 @@ static void nbio_v7_2_update_medium_grain_light_sleep(struct amdgpu_device *adev
 		if (def != data)
 			WREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regBIF1_PCIE_TX_POWER_CTRL_1),
 				data);
-	} else {
+		break;
+	default:
 		def = data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CNTL2));
 		if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS))
 			data |= (PCIE_CNTL2__SLV_MEM_LS_EN_MASK |
@@ -285,6 +298,8 @@ static void nbio_v7_2_update_medium_grain_light_sleep(struct amdgpu_device *adev
 
 		if (def != data)
 			WREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CNTL2), data);
+
+		break;
 	}
 }
 
@@ -352,7 +367,9 @@ const struct nbio_hdp_flush_reg nbio_v7_2_hdp_flush_reg = {
 static void nbio_v7_2_init_registers(struct amdgpu_device *adev)
 {
 	uint32_t def, data;
-	if (adev->asic_type == CHIP_YELLOW_CARP) {
+	switch (adev->ip_versions[NBIO_HWIP][0]) {
+	case IP_VERSION(7, 2, 1):
+	case IP_VERSION(7, 5, 0):
 		def = data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regBIF1_PCIE_MST_CTRL_3));
 		data = REG_SET_FIELD(data, BIF1_PCIE_MST_CTRL_3,
 			CI_SWUS_MAX_READ_REQUEST_SIZE_MODE, 1);
@@ -361,7 +378,8 @@ static void nbio_v7_2_init_registers(struct amdgpu_device *adev)
 
 		if (def != data)
 			WREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regBIF1_PCIE_MST_CTRL_3), data);
-	} else {
+		break;
+	default:
 		def = data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CONFIG_CNTL));
 		data = REG_SET_FIELD(data, PCIE_CONFIG_CNTL,
 			CI_SWUS_MAX_READ_REQUEST_SIZE_MODE, 1);
@@ -370,6 +388,8 @@ static void nbio_v7_2_init_registers(struct amdgpu_device *adev)
 
 		if (def != data)
 			WREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CONFIG_CNTL), data);
+
+		break;
 	}
 
 	if (amdgpu_sriov_vf(adev))
-- 
2.25.1

[PATCH 2/3] drm/amdgpu: convert to UVD IP version checking

[Tim Huang]

Use IP versions rather than asic_type to differentiate IP version specific features.

Signed-off-by: Tim Huang <xiaohu.huang@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c | 9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c
index 01c242c5abc3..c5ffb14ba183 100644
--- a/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c
@@ -50,11 +50,16 @@ static int jpeg_v3_0_early_init(void *handle)
 {
 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
-	if (adev->asic_type != CHIP_YELLOW_CARP) {
-		u32 harvest = RREG32_SOC15(JPEG, 0, mmCC_UVD_HARVESTING);
+	u32 harvest;
 
+	switch (adev->ip_versions[UVD_HWIP][0]) {
+	case IP_VERSION(3, 1, 1): 
+		break;
+	default:
+		harvest = RREG32_SOC15(JPEG, 0, mmCC_UVD_HARVESTING);
 		if (harvest & CC_UVD_HARVESTING__UVD_DISABLE_MASK)
 			return -ENOENT;
+		break;
 	}
 
 	adev->jpeg.num_jpeg_inst = 1;
-- 
2.25.1

Re: [PATCH 2/3] drm/amdgpu: convert to UVD IP version checking

[Huang Rui]

On Mon, Jan 24, 2022 at 11:20:41AM +0800, Huang, Tim wrote:
> Use IP versions rather than asic_type to differentiate IP version specific features.
> 
> Signed-off-by: Tim Huang <xiaohu.huang@amd.com>

Reviewed-by: Huang Rui <ray.huang@amd.com>

> ---
>  drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c | 9 +++++++--
>  1 file changed, 7 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c
> index 01c242c5abc3..c5ffb14ba183 100644
> --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c
> @@ -50,11 +50,16 @@ static int jpeg_v3_0_early_init(void *handle)
>  {
>  	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>  
> -	if (adev->asic_type != CHIP_YELLOW_CARP) {
> -		u32 harvest = RREG32_SOC15(JPEG, 0, mmCC_UVD_HARVESTING);
> +	u32 harvest;
>  
> +	switch (adev->ip_versions[UVD_HWIP][0]) {
> +	case IP_VERSION(3, 1, 1): 
> +		break;
> +	default:
> +		harvest = RREG32_SOC15(JPEG, 0, mmCC_UVD_HARVESTING);
>  		if (harvest & CC_UVD_HARVESTING__UVD_DISABLE_MASK)
>  			return -ENOENT;
> +		break;
>  	}
>  
>  	adev->jpeg.num_jpeg_inst = 1;
> -- 
> 2.25.1
> 

[PATCH 3/3] drm/amd/display: convert to DCE IP version checking

[Tim Huang]

Use IP versions rather than asic_type to differentiate IP version specific features.

Signed-off-by: Tim Huang <xiaohu.huang@amd.com>
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 12 +++++-------
 1 file changed, 5 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 87299e62fe12..c967e1e344e4 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -1119,19 +1119,17 @@ static int dm_dmub_hw_init(struct amdgpu_device *adev)
 	for (i = 0; i < fb_info->num_fb; ++i)
 		hw_params.fb[i] = &fb_info->fb[i];
 
-	switch (adev->asic_type) {
-	case CHIP_YELLOW_CARP:
-		if (dc->ctx->asic_id.hw_internal_rev != YELLOW_CARP_A0) {
-			hw_params.dpia_supported = true;
+	switch (adev->ip_versions[DCE_HWIP][0]) {
+	case IP_VERSION(3, 1, 3): /* Only for this asic hw internal rev B0 */
+		hw_params.dpia_supported = true;
 #if defined(CONFIG_DRM_AMD_DC_DCN)
-			hw_params.disable_dpia = dc->debug.dpia_debug.bits.disable_dpia;
+		hw_params.disable_dpia = dc->debug.dpia_debug.bits.disable_dpia;
 #endif
-		}
 		break;
 	default:
 		break;
 	}
-
+	
 	status = dmub_srv_hw_init(dmub_srv, &hw_params);
 	if (status != DMUB_STATUS_OK) {
 		DRM_ERROR("Error initializing DMUB HW: %d\n", status);
-- 
2.25.1

RE: [PATCH 3/3] drm/amd/display: convert to DCE IP version checking

[Liu, Aaron]

[-- Attachment #1: Type: text/plain, Size: 2550 bytes --]

[AMD Official Use Only]


Tim，

Please remove TAB in the beginning of an empty line and the SPACE in the end of a line.

With this fixed, series is:
Reviewed-by: Aaron Liu aaron.liu@amd.com<mailto:aaron.liu@amd.com>



--

Best Regards

Aaron Liu



> -----Original Message-----

> From: Huang, Tim <Tim.Huang@amd.com>

> Sent: Monday, January 24, 2022 11:21 AM

> To: amd-gfx@lists.freedesktop.org

> Cc: Deucher, Alexander <Alexander.Deucher@amd.com>; Huang, Ray

> <Ray.Huang@amd.com>; Liu, Aaron <Aaron.Liu@amd.com>; Huang, Tim

> <Tim.Huang@amd.com>

> Subject: [PATCH 3/3] drm/amd/display: convert to DCE IP version checking

>

> Use IP versions rather than asic_type to differentiate IP version specific

> features.

>

> Signed-off-by: Tim Huang <xiaohu.huang@amd.com<mailto:xiaohu.huang@amd.com>>

> ---

>  drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 12 +++++-------

>  1 file changed, 5 insertions(+), 7 deletions(-)

>

> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

> b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

> index 87299e62fe12..c967e1e344e4 100644

> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

> @@ -1119,19 +1119,17 @@ static int dm_dmub_hw_init(struct

> amdgpu_device *adev)

>          for (i = 0; i < fb_info->num_fb; ++i)

>                      hw_params.fb[i] = &fb_info->fb[i];

>

> -        switch (adev->asic_type) {

> -        case CHIP_YELLOW_CARP:

> -                    if (dc->ctx->asic_id.hw_internal_rev != YELLOW_CARP_A0) {

> -                                hw_params.dpia_supported = true;

> +       switch (adev->ip_versions[DCE_HWIP][0]) {

> +       case IP_VERSION(3, 1, 3): /* Only for this asic hw internal rev B0 */

> +                   hw_params.dpia_supported = true;

>  #if defined(CONFIG_DRM_AMD_DC_DCN)

> -                                hw_params.disable_dpia = dc-

> >debug.dpia_debug.bits.disable_dpia;

> +                   hw_params.disable_dpia = dc-

> >debug.dpia_debug.bits.disable_dpia;

>  #endif

> -                    }

>                      break;

>          default:

>                      break;

>          }

> -

> +

>          status = dmub_srv_hw_init(dmub_srv, &hw_params);

>          if (status != DMUB_STATUS_OK) {

>                      DRM_ERROR("Error initializing DMUB HW: %d\n", status);

> --

> 2.25.1



[-- Attachment #2: Type: text/html, Size: 9500 bytes --]

Re: [PATCH 3/3] drm/amd/display: convert to DCE IP version checking

[Huang Rui]

On Mon, Jan 24, 2022 at 11:20:42AM +0800, Huang, Tim wrote:
> Use IP versions rather than asic_type to differentiate IP version specific features.
> 
> Signed-off-by: Tim Huang <xiaohu.huang@amd.com>
> ---
>  drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 12 +++++-------
>  1 file changed, 5 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> index 87299e62fe12..c967e1e344e4 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> @@ -1119,19 +1119,17 @@ static int dm_dmub_hw_init(struct amdgpu_device *adev)
>  	for (i = 0; i < fb_info->num_fb; ++i)
>  		hw_params.fb[i] = &fb_info->fb[i];
>  
> -	switch (adev->asic_type) {
> -	case CHIP_YELLOW_CARP:
> -		if (dc->ctx->asic_id.hw_internal_rev != YELLOW_CARP_A0) {
> -			hw_params.dpia_supported = true;
> +	switch (adev->ip_versions[DCE_HWIP][0]) {
> +	case IP_VERSION(3, 1, 3): /* Only for this asic hw internal rev B0 */

There is another way to define a APU flag on enum amd_apu_flags to
differentiate A0 and B0 for yellow carp.

But this way looks good for me as well.
Patch is Acked-by: Huang Rui <ray.huang@amd.com>

> +		hw_params.dpia_supported = true;
>  #if defined(CONFIG_DRM_AMD_DC_DCN)
> -			hw_params.disable_dpia = dc->debug.dpia_debug.bits.disable_dpia;
> +		hw_params.disable_dpia = dc->debug.dpia_debug.bits.disable_dpia;
>  #endif
> -		}
>  		break;
>  	default:
>  		break;
>  	}
> -
> +	
>  	status = dmub_srv_hw_init(dmub_srv, &hw_params);
>  	if (status != DMUB_STATUS_OK) {
>  		DRM_ERROR("Error initializing DMUB HW: %d\n", status);
> -- 
> 2.25.1
> 

Re: [PATCH 1/3] drm/amdgpu: convert to NBIO IP version checking

[Huang Rui]

On Mon, Jan 24, 2022 at 11:20:40AM +0800, Huang, Tim wrote:
> Use IP versions rather than asic_type to differentiate IP version specific features.
> 
> Signed-off-by: Tim Huang <xiaohu.huang@amd.com>

Reviewed-by: Huang Rui <ray.huang@amd.com>

> ---
>  drivers/gpu/drm/amd/amdgpu/nbio_v7_2.c | 48 ++++++++++++++++++--------
>  1 file changed, 34 insertions(+), 14 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_2.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_2.c
> index 3444332ea110..70e341d884d5 100644
> --- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_2.c
> +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_2.c
> @@ -59,10 +59,15 @@ static u32 nbio_v7_2_get_rev_id(struct amdgpu_device *adev)
>  {
>  	u32 tmp;
>  
> -	if (adev->asic_type == CHIP_YELLOW_CARP)
> +	switch (adev->ip_versions[NBIO_HWIP][0]) {
> +	case IP_VERSION(7, 2, 1):
> +	case IP_VERSION(7, 5, 0):
>  		tmp = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0_YC);
> -	else
> +		break;
> +	default:
>  		tmp = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0);
> +		break;
> +	}
>  
>  	tmp &= RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK;
>  	tmp >>= RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT;
> @@ -72,20 +77,25 @@ static u32 nbio_v7_2_get_rev_id(struct amdgpu_device *adev)
>  
>  static void nbio_v7_2_mc_access_enable(struct amdgpu_device *adev, bool enable)
>  {
> -	if (enable)
> -		if (adev->asic_type == CHIP_YELLOW_CARP)
> +	switch (adev->ip_versions[NBIO_HWIP][0]) {
> +	case IP_VERSION(7, 2, 1):
> +	case IP_VERSION(7, 5, 0):
> +		if (enable)
>  			WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_FB_EN_YC,
>  				BIF_BX0_BIF_FB_EN__FB_READ_EN_MASK |
>  				BIF_BX0_BIF_FB_EN__FB_WRITE_EN_MASK);
>  		else
> +			WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_FB_EN_YC, 0);
> +	break;
> +	default:
> +		if (enable)
>  			WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_FB_EN,
>  				BIF_BX0_BIF_FB_EN__FB_READ_EN_MASK |
>  				BIF_BX0_BIF_FB_EN__FB_WRITE_EN_MASK);
> -	else
> -		if (adev->asic_type == CHIP_YELLOW_CARP)
> -			WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_FB_EN_YC, 0);
>  		else
>  			WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_FB_EN, 0);
> +		break;
> +	}
>  }
>  
>  static u32 nbio_v7_2_get_memsize(struct amdgpu_device *adev)
> @@ -249,8 +259,10 @@ static void nbio_v7_2_update_medium_grain_light_sleep(struct amdgpu_device *adev
>  						      bool enable)
>  {
>  	uint32_t def, data;
> -
> -	if (adev->asic_type == CHIP_YELLOW_CARP) {
> +	
> +	switch (adev->ip_versions[NBIO_HWIP][0]) {
> +	case IP_VERSION(7, 2, 1):
> +	case IP_VERSION(7, 5, 0):
>  		def = data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CNTL2));
>  		if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS))
>  			data |= PCIE_CNTL2__SLV_MEM_LS_EN_MASK;
> @@ -260,8 +272,8 @@ static void nbio_v7_2_update_medium_grain_light_sleep(struct amdgpu_device *adev
>  		if (def != data)
>  			WREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CNTL2), data);
>  
> -		data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regBIF1_PCIE_TX_POWER_CTRL_1));
> -		def = data;
> +		def = data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, 
> +			regBIF1_PCIE_TX_POWER_CTRL_1));
>  		if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS))
>  			data |= (BIF1_PCIE_TX_POWER_CTRL_1__MST_MEM_LS_EN_MASK |
>  				BIF1_PCIE_TX_POWER_CTRL_1__REPLAY_MEM_LS_EN_MASK);
> @@ -272,7 +284,8 @@ static void nbio_v7_2_update_medium_grain_light_sleep(struct amdgpu_device *adev
>  		if (def != data)
>  			WREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regBIF1_PCIE_TX_POWER_CTRL_1),
>  				data);
> -	} else {
> +		break;
> +	default:
>  		def = data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CNTL2));
>  		if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS))
>  			data |= (PCIE_CNTL2__SLV_MEM_LS_EN_MASK |
> @@ -285,6 +298,8 @@ static void nbio_v7_2_update_medium_grain_light_sleep(struct amdgpu_device *adev
>  
>  		if (def != data)
>  			WREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CNTL2), data);
> +
> +		break;
>  	}
>  }
>  
> @@ -352,7 +367,9 @@ const struct nbio_hdp_flush_reg nbio_v7_2_hdp_flush_reg = {
>  static void nbio_v7_2_init_registers(struct amdgpu_device *adev)
>  {
>  	uint32_t def, data;
> -	if (adev->asic_type == CHIP_YELLOW_CARP) {
> +	switch (adev->ip_versions[NBIO_HWIP][0]) {
> +	case IP_VERSION(7, 2, 1):
> +	case IP_VERSION(7, 5, 0):
>  		def = data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regBIF1_PCIE_MST_CTRL_3));
>  		data = REG_SET_FIELD(data, BIF1_PCIE_MST_CTRL_3,
>  			CI_SWUS_MAX_READ_REQUEST_SIZE_MODE, 1);
> @@ -361,7 +378,8 @@ static void nbio_v7_2_init_registers(struct amdgpu_device *adev)
>  
>  		if (def != data)
>  			WREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regBIF1_PCIE_MST_CTRL_3), data);
> -	} else {
> +		break;
> +	default:
>  		def = data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CONFIG_CNTL));
>  		data = REG_SET_FIELD(data, PCIE_CONFIG_CNTL,
>  			CI_SWUS_MAX_READ_REQUEST_SIZE_MODE, 1);
> @@ -370,6 +388,8 @@ static void nbio_v7_2_init_registers(struct amdgpu_device *adev)
>  
>  		if (def != data)
>  			WREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CONFIG_CNTL), data);
> +
> +		break;
>  	}
>  
>  	if (amdgpu_sriov_vf(adev))
> -- 
> 2.25.1
>