[PATCH 1/2] drm/amdgpu/nv: enable gfx10.3.7 clock gating support

[PATCH 1/2] drm/amdgpu/nv: enable gfx10.3.7 clock gating support

[Prike Liang]

This will enable the following gfx clock gating.
- Fine clock gating
- Medium Grain clock gating
- 3D Coarse clock gating
- Coarse Grain clock gating
- RLC/CP light sleep clock gating

Signed-off-by: Prike Liang <Prike.Liang@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/nv.c | 10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
index 74e0550d00bd..5f375f3430e1 100644
--- a/drivers/gpu/drm/amd/amdgpu/nv.c
+++ b/drivers/gpu/drm/amd/amdgpu/nv.c
@@ -936,7 +936,15 @@ static int nv_common_early_init(void *handle)
 		adev->external_rev_id = adev->rev_id + 0x01;
 		break;
 	case IP_VERSION(10, 3, 7):
-		adev->cg_flags = 0;
+		adev->cg_flags =  AMD_CG_SUPPORT_GFX_MGCG |
+			AMD_CG_SUPPORT_GFX_MGLS |
+			AMD_CG_SUPPORT_GFX_CGCG |
+			AMD_CG_SUPPORT_GFX_CGLS |
+			AMD_CG_SUPPORT_GFX_3D_CGCG |
+			AMD_CG_SUPPORT_GFX_3D_CGLS |
+			AMD_CG_SUPPORT_GFX_RLC_LS |
+			AMD_CG_SUPPORT_GFX_CP_LS |
+			AMD_CG_SUPPORT_GFX_FGCG;
 		adev->pg_flags = AMD_PG_SUPPORT_VCN |
 			AMD_PG_SUPPORT_VCN_DPG |
 			AMD_PG_SUPPORT_JPEG;
-- 
2.17.1

[PATCH 2/2] drm/amdgpu/nv: set mode2 reset for MP1 13.0.8

[Prike Liang]

Set mode2 reset support for MP1 13.0.8.

Signed-off-by: Prike Liang <Prike.Liang@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/nv.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
index 5f375f3430e1..f414b7ca0ab7 100644
--- a/drivers/gpu/drm/amd/amdgpu/nv.c
+++ b/drivers/gpu/drm/amd/amdgpu/nv.c
@@ -454,6 +454,7 @@ nv_asic_reset_method(struct amdgpu_device *adev)
 	case IP_VERSION(11, 5, 0):
 	case IP_VERSION(13, 0, 1):
 	case IP_VERSION(13, 0, 3):
+	case IP_VERSION(13, 0, 8):
 		return AMD_RESET_METHOD_MODE2;
 	case IP_VERSION(11, 0, 7):
 	case IP_VERSION(11, 0, 11):
-- 
2.17.1

Re: [PATCH 1/2] drm/amdgpu/nv: enable gfx10.3.7 clock gating support

[Huang Rui]

On Wed, Feb 23, 2022 at 10:42:34AM +0800, Liang, Prike wrote:
> This will enable the following gfx clock gating.
> - Fine clock gating
> - Medium Grain clock gating
> - 3D Coarse clock gating
> - Coarse Grain clock gating
> - RLC/CP light sleep clock gating
> 
> Signed-off-by: Prike Liang <Prike.Liang@amd.com>

Series are Reviewed-by: Huang Rui <ray.huang@amd.com>

> ---
>  drivers/gpu/drm/amd/amdgpu/nv.c | 10 +++++++++-
>  1 file changed, 9 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
> index 74e0550d00bd..5f375f3430e1 100644
> --- a/drivers/gpu/drm/amd/amdgpu/nv.c
> +++ b/drivers/gpu/drm/amd/amdgpu/nv.c
> @@ -936,7 +936,15 @@ static int nv_common_early_init(void *handle)
>  		adev->external_rev_id = adev->rev_id + 0x01;
>  		break;
>  	case IP_VERSION(10, 3, 7):
> -		adev->cg_flags = 0;
> +		adev->cg_flags =  AMD_CG_SUPPORT_GFX_MGCG |
> +			AMD_CG_SUPPORT_GFX_MGLS |
> +			AMD_CG_SUPPORT_GFX_CGCG |
> +			AMD_CG_SUPPORT_GFX_CGLS |
> +			AMD_CG_SUPPORT_GFX_3D_CGCG |
> +			AMD_CG_SUPPORT_GFX_3D_CGLS |
> +			AMD_CG_SUPPORT_GFX_RLC_LS |
> +			AMD_CG_SUPPORT_GFX_CP_LS |
> +			AMD_CG_SUPPORT_GFX_FGCG;
>  		adev->pg_flags = AMD_PG_SUPPORT_VCN |
>  			AMD_PG_SUPPORT_VCN_DPG |
>  			AMD_PG_SUPPORT_JPEG;
> -- 
> 2.17.1
>