* [PATCH 0/6] Cleaning up some GCC warnings and other minor issues
@ 2022-06-03 18:50 Rodrigo Siqueira
2022-06-03 18:50 ` [PATCH 1/6] drm/amd/display: Remove duplicated macro Rodrigo Siqueira
` (6 more replies)
0 siblings, 7 replies; 17+ messages in thread
From: Rodrigo Siqueira @ 2022-06-03 18:50 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher
It looks like that we have some new warnings on display code and a
compilation error when using allmodconfig. This series clean up some of
the DML warnings and fix the compilation problem with allmodeconfig.
Thanks
Rodrigo Siqueira (6):
drm/amd/display: Remove duplicated macro
drm/amd/display: Reduce frame size in the bouding box for DCN20
drm/amd/display: Reduce frame size in the bouding box for DCN301
drm/amd/display: Reduce frame size in the bouding box for DCN31/316
drm/amd/display: Reduce frame size in the bouding box for DCN21
Revert "drm/amd/display: Drop unnecessary guard from DC resource"
.../gpu/drm/amd/display/dc/core/dc_resource.c | 2 +
.../drm/amd/display/dc/dml/dcn20/dcn20_fpu.c | 67 +++++++++----------
.../amd/display/dc/dml/dcn301/dcn301_fpu.c | 30 ++++-----
.../drm/amd/display/dc/dml/dcn31/dcn31_fpu.c | 58 +++++++---------
.../gpu/drm/amd/display/include/dal_asic_id.h | 6 --
5 files changed, 72 insertions(+), 91 deletions(-)
--
2.25.1
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH 1/6] drm/amd/display: Remove duplicated macro
2022-06-03 18:50 [PATCH 0/6] Cleaning up some GCC warnings and other minor issues Rodrigo Siqueira
@ 2022-06-03 18:50 ` Rodrigo Siqueira
2022-06-06 14:04 ` Harry Wentland
2022-06-03 18:50 ` [PATCH 2/6] drm/amd/display: Reduce frame size in the bouding box for DCN20 Rodrigo Siqueira
` (5 subsequent siblings)
6 siblings, 1 reply; 17+ messages in thread
From: Rodrigo Siqueira @ 2022-06-03 18:50 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher
Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
---
drivers/gpu/drm/amd/display/include/dal_asic_id.h | 6 ------
1 file changed, 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/include/dal_asic_id.h b/drivers/gpu/drm/amd/display/include/dal_asic_id.h
index 11391eead954..a0dffe30b394 100644
--- a/drivers/gpu/drm/amd/display/include/dal_asic_id.h
+++ b/drivers/gpu/drm/amd/display/include/dal_asic_id.h
@@ -221,10 +221,6 @@ enum {
#ifndef ASICREV_IS_VANGOGH
#define ASICREV_IS_VANGOGH(eChipRev) ((eChipRev >= VANGOGH_A0) && (eChipRev < VANGOGH_UNKNOWN))
#endif
-#define GREEN_SARDINE_A0 0xA1
-#ifndef ASICREV_IS_GREEN_SARDINE
-#define ASICREV_IS_GREEN_SARDINE(eChipRev) ((eChipRev >= GREEN_SARDINE_A0) && (eChipRev < 0xFF))
-#endif
#define FAMILY_YELLOW_CARP 146
#define YELLOW_CARP_A0 0x01
@@ -288,6 +284,4 @@ enum {
#define FAMILY_UNKNOWN 0xFF
-
-
#endif /* __DAL_ASIC_ID_H__ */
--
2.25.1
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH 2/6] drm/amd/display: Reduce frame size in the bouding box for DCN20
2022-06-03 18:50 [PATCH 0/6] Cleaning up some GCC warnings and other minor issues Rodrigo Siqueira
2022-06-03 18:50 ` [PATCH 1/6] drm/amd/display: Remove duplicated macro Rodrigo Siqueira
@ 2022-06-03 18:50 ` Rodrigo Siqueira
2022-06-06 14:05 ` Harry Wentland
2022-06-03 18:50 ` [PATCH 3/6] drm/amd/display: Reduce frame size in the bouding box for DCN301 Rodrigo Siqueira
` (4 subsequent siblings)
6 siblings, 1 reply; 17+ messages in thread
From: Rodrigo Siqueira @ 2022-06-03 18:50 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Stephen Rothwell, Aurabindo Pillai, Hamza Mahfooz
GCC throw warnings for the function dcn20_update_bounding_box due to its
frame size that looks like this:
error: the frame size of 1936 bytes is larger than 1024 bytes [-Werror=frame-larger-than=]
This commit fixes this issue by eliminating an intermediary variable
that creates a large array.
Cc: Stephen Rothwell <sfr@canb.auug.org.au>
Cc: Hamza Mahfooz <hamza.mahfooz@amd.com>
Cc: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
---
.../drm/amd/display/dc/dml/dcn20/dcn20_fpu.c | 38 +++++++++----------
1 file changed, 18 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
index eeec40f6fd0a..d9cc178f6980 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
@@ -1456,21 +1456,20 @@ void dcn20_calculate_wm(
void dcn20_update_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb,
struct pp_smu_nv_clock_table *max_clocks, unsigned int *uclk_states, unsigned int num_states)
{
- struct _vcs_dpi_voltage_scaling_st calculated_states[DC__VOLTAGE_STATES];
- int i;
int num_calculated_states = 0;
int min_dcfclk = 0;
+ int i;
dc_assert_fp_enabled();
if (num_states == 0)
return;
- memset(calculated_states, 0, sizeof(calculated_states));
+ memset(bb->clock_limits, 0, sizeof(bb->clock_limits));
- if (dc->bb_overrides.min_dcfclk_mhz > 0)
+ if (dc->bb_overrides.min_dcfclk_mhz > 0) {
min_dcfclk = dc->bb_overrides.min_dcfclk_mhz;
- else {
+ } else {
if (ASICREV_IS_NAVI12_P(dc->ctx->asic_id.hw_internal_rev))
min_dcfclk = 310;
else
@@ -1481,36 +1480,35 @@ void dcn20_update_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_s
for (i = 0; i < num_states; i++) {
int min_fclk_required_by_uclk;
- calculated_states[i].state = i;
- calculated_states[i].dram_speed_mts = uclk_states[i] * 16 / 1000;
+ bb->clock_limits[i].state = i;
+ bb->clock_limits[i].dram_speed_mts = uclk_states[i] * 16 / 1000;
// FCLK:UCLK ratio is 1.08
min_fclk_required_by_uclk = div_u64(((unsigned long long)uclk_states[i]) * 1080,
1000000);
- calculated_states[i].fabricclk_mhz = (min_fclk_required_by_uclk < min_dcfclk) ?
+ bb->clock_limits[i].fabricclk_mhz = (min_fclk_required_by_uclk < min_dcfclk) ?
min_dcfclk : min_fclk_required_by_uclk;
- calculated_states[i].socclk_mhz = (calculated_states[i].fabricclk_mhz > max_clocks->socClockInKhz / 1000) ?
- max_clocks->socClockInKhz / 1000 : calculated_states[i].fabricclk_mhz;
+ bb->clock_limits[i].socclk_mhz = (bb->clock_limits[i].fabricclk_mhz > max_clocks->socClockInKhz / 1000) ?
+ max_clocks->socClockInKhz / 1000 : bb->clock_limits[i].fabricclk_mhz;
- calculated_states[i].dcfclk_mhz = (calculated_states[i].fabricclk_mhz > max_clocks->dcfClockInKhz / 1000) ?
- max_clocks->dcfClockInKhz / 1000 : calculated_states[i].fabricclk_mhz;
+ bb->clock_limits[i].dcfclk_mhz = (bb->clock_limits[i].fabricclk_mhz > max_clocks->dcfClockInKhz / 1000) ?
+ max_clocks->dcfClockInKhz / 1000 : bb->clock_limits[i].fabricclk_mhz;
- calculated_states[i].dispclk_mhz = max_clocks->displayClockInKhz / 1000;
- calculated_states[i].dppclk_mhz = max_clocks->displayClockInKhz / 1000;
- calculated_states[i].dscclk_mhz = max_clocks->displayClockInKhz / (1000 * 3);
+ bb->clock_limits[i].dispclk_mhz = max_clocks->displayClockInKhz / 1000;
+ bb->clock_limits[i].dppclk_mhz = max_clocks->displayClockInKhz / 1000;
+ bb->clock_limits[i].dscclk_mhz = max_clocks->displayClockInKhz / (1000 * 3);
- calculated_states[i].phyclk_mhz = max_clocks->phyClockInKhz / 1000;
+ bb->clock_limits[i].phyclk_mhz = max_clocks->phyClockInKhz / 1000;
num_calculated_states++;
}
- calculated_states[num_calculated_states - 1].socclk_mhz = max_clocks->socClockInKhz / 1000;
- calculated_states[num_calculated_states - 1].fabricclk_mhz = max_clocks->socClockInKhz / 1000;
- calculated_states[num_calculated_states - 1].dcfclk_mhz = max_clocks->dcfClockInKhz / 1000;
+ bb->clock_limits[num_calculated_states - 1].socclk_mhz = max_clocks->socClockInKhz / 1000;
+ bb->clock_limits[num_calculated_states - 1].fabricclk_mhz = max_clocks->socClockInKhz / 1000;
+ bb->clock_limits[num_calculated_states - 1].dcfclk_mhz = max_clocks->dcfClockInKhz / 1000;
- memcpy(bb->clock_limits, calculated_states, sizeof(bb->clock_limits));
bb->num_states = num_calculated_states;
// Duplicate the last state, DML always an extra state identical to max state to work
--
2.25.1
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH 3/6] drm/amd/display: Reduce frame size in the bouding box for DCN301
2022-06-03 18:50 [PATCH 0/6] Cleaning up some GCC warnings and other minor issues Rodrigo Siqueira
2022-06-03 18:50 ` [PATCH 1/6] drm/amd/display: Remove duplicated macro Rodrigo Siqueira
2022-06-03 18:50 ` [PATCH 2/6] drm/amd/display: Reduce frame size in the bouding box for DCN20 Rodrigo Siqueira
@ 2022-06-03 18:50 ` Rodrigo Siqueira
2022-06-06 14:08 ` Harry Wentland
2022-06-03 18:50 ` [PATCH 4/6] drm/amd/display: Reduce frame size in the bouding box for DCN31/316 Rodrigo Siqueira
` (3 subsequent siblings)
6 siblings, 1 reply; 17+ messages in thread
From: Rodrigo Siqueira @ 2022-06-03 18:50 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Stephen Rothwell, Aurabindo Pillai, Hamza Mahfooz
GCC throw warnings for the function dcn301_fpu_update_bw_bounding_box
due to its frame size that looks like this:
error: the frame size of 1936 bytes is larger than 1024 bytes [-Werror=frame-larger-than=]
For fixing this issue I dropped an intermadiate variable.
Cc: Stephen Rothwell <sfr@canb.auug.org.au>
Cc: Hamza Mahfooz <hamza.mahfooz@amd.com>
Cc: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
---
.../amd/display/dc/dml/dcn301/dcn301_fpu.c | 30 ++++++++-----------
1 file changed, 13 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c
index 0a7a33864973..62cf283d9f41 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c
@@ -249,7 +249,6 @@ void dcn301_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_param
{
struct dcn301_resource_pool *pool = TO_DCN301_RES_POOL(dc->res_pool);
struct clk_limit_table *clk_table = &bw_params->clk_table;
- struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES];
unsigned int i, closest_clk_lvl;
int j;
@@ -271,24 +270,21 @@ void dcn301_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_param
}
}
- clock_limits[i].state = i;
- clock_limits[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz;
- clock_limits[i].fabricclk_mhz = clk_table->entries[i].fclk_mhz;
- clock_limits[i].socclk_mhz = clk_table->entries[i].socclk_mhz;
- clock_limits[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2;
-
- clock_limits[i].dispclk_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].dispclk_mhz;
- clock_limits[i].dppclk_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].dppclk_mhz;
- clock_limits[i].dram_bw_per_chan_gbps = dcn3_01_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan_gbps;
- clock_limits[i].dscclk_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].dscclk_mhz;
- clock_limits[i].dtbclk_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].dtbclk_mhz;
- clock_limits[i].phyclk_d18_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz;
- clock_limits[i].phyclk_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].phyclk_mhz;
+ dcn3_01_soc.clock_limits[i].state = i;
+ dcn3_01_soc.clock_limits[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz;
+ dcn3_01_soc.clock_limits[i].fabricclk_mhz = clk_table->entries[i].fclk_mhz;
+ dcn3_01_soc.clock_limits[i].socclk_mhz = clk_table->entries[i].socclk_mhz;
+ dcn3_01_soc.clock_limits[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2;
+
+ dcn3_01_soc.clock_limits[i].dispclk_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].dispclk_mhz;
+ dcn3_01_soc.clock_limits[i].dppclk_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].dppclk_mhz;
+ dcn3_01_soc.clock_limits[i].dram_bw_per_chan_gbps = dcn3_01_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan_gbps;
+ dcn3_01_soc.clock_limits[i].dscclk_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].dscclk_mhz;
+ dcn3_01_soc.clock_limits[i].dtbclk_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].dtbclk_mhz;
+ dcn3_01_soc.clock_limits[i].phyclk_d18_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz;
+ dcn3_01_soc.clock_limits[i].phyclk_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].phyclk_mhz;
}
- for (i = 0; i < clk_table->num_entries; i++)
- dcn3_01_soc.clock_limits[i] = clock_limits[i];
-
if (clk_table->num_entries) {
dcn3_01_soc.num_states = clk_table->num_entries;
/* duplicate last level */
--
2.25.1
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH 4/6] drm/amd/display: Reduce frame size in the bouding box for DCN31/316
2022-06-03 18:50 [PATCH 0/6] Cleaning up some GCC warnings and other minor issues Rodrigo Siqueira
` (2 preceding siblings ...)
2022-06-03 18:50 ` [PATCH 3/6] drm/amd/display: Reduce frame size in the bouding box for DCN301 Rodrigo Siqueira
@ 2022-06-03 18:50 ` Rodrigo Siqueira
2022-06-06 14:10 ` Harry Wentland
2022-06-03 18:50 ` [PATCH 5/6] drm/amd/display: Reduce frame size in the bouding box for DCN21 Rodrigo Siqueira
` (2 subsequent siblings)
6 siblings, 1 reply; 17+ messages in thread
From: Rodrigo Siqueira @ 2022-06-03 18:50 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Stephen Rothwell, Aurabindo Pillai, Hamza Mahfooz
GCC throw warnings for the function dcn31_update_bw_bounding_box and
dcn316_update_bw_bounding_box due to its frame size that looks like
this:
error: the frame size of 1936 bytes is larger than 1024 bytes [-Werror=frame-larger-than=]
For fixing this issue I dropped an intermadiate variable.
Cc: Stephen Rothwell <sfr@canb.auug.org.au>
Cc: Hamza Mahfooz <hamza.mahfooz@amd.com>
Cc: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
---
.../drm/amd/display/dc/dml/dcn31/dcn31_fpu.c | 58 +++++++++----------
1 file changed, 26 insertions(+), 32 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c
index 54db2eca9e6b..ee898bc93fd5 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c
@@ -574,7 +574,6 @@ void dcn31_calculate_wm_and_dlg_fp(
void dcn31_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
{
struct clk_limit_table *clk_table = &bw_params->clk_table;
- struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES];
unsigned int i, closest_clk_lvl;
int j;
@@ -607,29 +606,27 @@ void dcn31_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params
}
}
- clock_limits[i].state = i;
+ dcn3_1_soc.clock_limits[i].state = i;
/* Clocks dependent on voltage level. */
- clock_limits[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz;
- clock_limits[i].fabricclk_mhz = clk_table->entries[i].fclk_mhz;
- clock_limits[i].socclk_mhz = clk_table->entries[i].socclk_mhz;
- clock_limits[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2 * clk_table->entries[i].wck_ratio;
+ dcn3_1_soc.clock_limits[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz;
+ dcn3_1_soc.clock_limits[i].fabricclk_mhz = clk_table->entries[i].fclk_mhz;
+ dcn3_1_soc.clock_limits[i].socclk_mhz = clk_table->entries[i].socclk_mhz;
+ dcn3_1_soc.clock_limits[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2 * clk_table->entries[i].wck_ratio;
/* Clocks independent of voltage level. */
- clock_limits[i].dispclk_mhz = max_dispclk_mhz ? max_dispclk_mhz :
+ dcn3_1_soc.clock_limits[i].dispclk_mhz = max_dispclk_mhz ? max_dispclk_mhz :
dcn3_1_soc.clock_limits[closest_clk_lvl].dispclk_mhz;
- clock_limits[i].dppclk_mhz = max_dppclk_mhz ? max_dppclk_mhz :
+ dcn3_1_soc.clock_limits[i].dppclk_mhz = max_dppclk_mhz ? max_dppclk_mhz :
dcn3_1_soc.clock_limits[closest_clk_lvl].dppclk_mhz;
- clock_limits[i].dram_bw_per_chan_gbps = dcn3_1_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan_gbps;
- clock_limits[i].dscclk_mhz = dcn3_1_soc.clock_limits[closest_clk_lvl].dscclk_mhz;
- clock_limits[i].dtbclk_mhz = dcn3_1_soc.clock_limits[closest_clk_lvl].dtbclk_mhz;
- clock_limits[i].phyclk_d18_mhz = dcn3_1_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz;
- clock_limits[i].phyclk_mhz = dcn3_1_soc.clock_limits[closest_clk_lvl].phyclk_mhz;
+ dcn3_1_soc.clock_limits[i].dram_bw_per_chan_gbps = dcn3_1_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan_gbps;
+ dcn3_1_soc.clock_limits[i].dscclk_mhz = dcn3_1_soc.clock_limits[closest_clk_lvl].dscclk_mhz;
+ dcn3_1_soc.clock_limits[i].dtbclk_mhz = dcn3_1_soc.clock_limits[closest_clk_lvl].dtbclk_mhz;
+ dcn3_1_soc.clock_limits[i].phyclk_d18_mhz = dcn3_1_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz;
+ dcn3_1_soc.clock_limits[i].phyclk_mhz = dcn3_1_soc.clock_limits[closest_clk_lvl].phyclk_mhz;
}
- for (i = 0; i < clk_table->num_entries; i++)
- dcn3_1_soc.clock_limits[i] = clock_limits[i];
if (clk_table->num_entries) {
dcn3_1_soc.num_states = clk_table->num_entries;
}
@@ -701,7 +698,6 @@ void dcn315_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_param
void dcn316_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
{
struct clk_limit_table *clk_table = &bw_params->clk_table;
- struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES];
unsigned int i, closest_clk_lvl;
int max_dispclk_mhz = 0, max_dppclk_mhz = 0;
int j;
@@ -739,34 +735,32 @@ void dcn316_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_param
closest_clk_lvl = dcn3_16_soc.num_states - 1;
}
- clock_limits[i].state = i;
+ dcn3_16_soc.clock_limits[i].state = i;
/* Clocks dependent on voltage level. */
- clock_limits[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz;
+ dcn3_16_soc.clock_limits[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz;
if (clk_table->num_entries == 1 &&
- clock_limits[i].dcfclk_mhz < dcn3_16_soc.clock_limits[closest_clk_lvl].dcfclk_mhz) {
+ dcn3_16_soc.clock_limits[i].dcfclk_mhz < dcn3_16_soc.clock_limits[closest_clk_lvl].dcfclk_mhz) {
/*SMU fix not released yet*/
- clock_limits[i].dcfclk_mhz = dcn3_16_soc.clock_limits[closest_clk_lvl].dcfclk_mhz;
+ dcn3_16_soc.clock_limits[i].dcfclk_mhz = dcn3_16_soc.clock_limits[closest_clk_lvl].dcfclk_mhz;
}
- clock_limits[i].fabricclk_mhz = clk_table->entries[i].fclk_mhz;
- clock_limits[i].socclk_mhz = clk_table->entries[i].socclk_mhz;
- clock_limits[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2 * clk_table->entries[i].wck_ratio;
+ dcn3_16_soc.clock_limits[i].fabricclk_mhz = clk_table->entries[i].fclk_mhz;
+ dcn3_16_soc.clock_limits[i].socclk_mhz = clk_table->entries[i].socclk_mhz;
+ dcn3_16_soc.clock_limits[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2 * clk_table->entries[i].wck_ratio;
/* Clocks independent of voltage level. */
- clock_limits[i].dispclk_mhz = max_dispclk_mhz ? max_dispclk_mhz :
+ dcn3_16_soc.clock_limits[i].dispclk_mhz = max_dispclk_mhz ? max_dispclk_mhz :
dcn3_16_soc.clock_limits[closest_clk_lvl].dispclk_mhz;
- clock_limits[i].dppclk_mhz = max_dppclk_mhz ? max_dppclk_mhz :
+ dcn3_16_soc.clock_limits[i].dppclk_mhz = max_dppclk_mhz ? max_dppclk_mhz :
dcn3_16_soc.clock_limits[closest_clk_lvl].dppclk_mhz;
- clock_limits[i].dram_bw_per_chan_gbps = dcn3_16_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan_gbps;
- clock_limits[i].dscclk_mhz = dcn3_16_soc.clock_limits[closest_clk_lvl].dscclk_mhz;
- clock_limits[i].dtbclk_mhz = dcn3_16_soc.clock_limits[closest_clk_lvl].dtbclk_mhz;
- clock_limits[i].phyclk_d18_mhz = dcn3_16_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz;
- clock_limits[i].phyclk_mhz = dcn3_16_soc.clock_limits[closest_clk_lvl].phyclk_mhz;
+ dcn3_16_soc.clock_limits[i].dram_bw_per_chan_gbps = dcn3_16_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan_gbps;
+ dcn3_16_soc.clock_limits[i].dscclk_mhz = dcn3_16_soc.clock_limits[closest_clk_lvl].dscclk_mhz;
+ dcn3_16_soc.clock_limits[i].dtbclk_mhz = dcn3_16_soc.clock_limits[closest_clk_lvl].dtbclk_mhz;
+ dcn3_16_soc.clock_limits[i].phyclk_d18_mhz = dcn3_16_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz;
+ dcn3_16_soc.clock_limits[i].phyclk_mhz = dcn3_16_soc.clock_limits[closest_clk_lvl].phyclk_mhz;
}
- for (i = 0; i < clk_table->num_entries; i++)
- dcn3_16_soc.clock_limits[i] = clock_limits[i];
if (clk_table->num_entries) {
dcn3_16_soc.num_states = clk_table->num_entries;
}
--
2.25.1
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH 5/6] drm/amd/display: Reduce frame size in the bouding box for DCN21
2022-06-03 18:50 [PATCH 0/6] Cleaning up some GCC warnings and other minor issues Rodrigo Siqueira
` (3 preceding siblings ...)
2022-06-03 18:50 ` [PATCH 4/6] drm/amd/display: Reduce frame size in the bouding box for DCN31/316 Rodrigo Siqueira
@ 2022-06-03 18:50 ` Rodrigo Siqueira
2022-06-06 14:11 ` Harry Wentland
2022-06-03 18:50 ` [PATCH 6/6] Revert "drm/amd/display: Drop unnecessary guard from DC resource" Rodrigo Siqueira
2022-06-03 19:40 ` [PATCH 0/6] Cleaning up some GCC warnings and other minor issues Alex Deucher
6 siblings, 1 reply; 17+ messages in thread
From: Rodrigo Siqueira @ 2022-06-03 18:50 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Stephen Rothwell, Aurabindo Pillai, Hamza Mahfooz
GCC throw warnings for the function dcn21_update_bw_bounding_box and
dcn316_update_bw_bounding_box due to its frame size that looks like
this:
error: the frame size of 1936 bytes is larger than 1024 bytes [-Werror=frame-larger-than=]
For fixing this issue I dropped an intermadiate variable.
Cc: Stephen Rothwell <sfr@canb.auug.org.au>
Cc: Hamza Mahfooz <hamza.mahfooz@amd.com>
Cc: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
---
.../drm/amd/display/dc/dml/dcn20/dcn20_fpu.c | 29 +++++++++----------
1 file changed, 13 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
index d9cc178f6980..c2fec0d85da4 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
@@ -2004,7 +2004,6 @@ void dcn21_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params
{
struct dcn21_resource_pool *pool = TO_DCN21_RES_POOL(dc->res_pool);
struct clk_limit_table *clk_table = &bw_params->clk_table;
- struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES];
unsigned int i, closest_clk_lvl = 0, k = 0;
int j;
@@ -2017,7 +2016,7 @@ void dcn21_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params
ASSERT(clk_table->num_entries);
/* Copy dcn2_1_soc.clock_limits to clock_limits to avoid copying over null states later */
for (i = 0; i < dcn2_1_soc.num_states + 1; i++) {
- clock_limits[i] = dcn2_1_soc.clock_limits[i];
+ dcn2_1_soc.clock_limits[i] = dcn2_1_soc.clock_limits[i];
}
for (i = 0; i < clk_table->num_entries; i++) {
@@ -2033,24 +2032,22 @@ void dcn21_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params
if (i == 1)
k++;
- clock_limits[k].state = k;
- clock_limits[k].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz;
- clock_limits[k].fabricclk_mhz = clk_table->entries[i].fclk_mhz;
- clock_limits[k].socclk_mhz = clk_table->entries[i].socclk_mhz;
- clock_limits[k].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2;
+ dcn2_1_soc.clock_limits[k].state = k;
+ dcn2_1_soc.clock_limits[k].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz;
+ dcn2_1_soc.clock_limits[k].fabricclk_mhz = clk_table->entries[i].fclk_mhz;
+ dcn2_1_soc.clock_limits[k].socclk_mhz = clk_table->entries[i].socclk_mhz;
+ dcn2_1_soc.clock_limits[k].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2;
- clock_limits[k].dispclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dispclk_mhz;
- clock_limits[k].dppclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dppclk_mhz;
- clock_limits[k].dram_bw_per_chan_gbps = dcn2_1_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan_gbps;
- clock_limits[k].dscclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dscclk_mhz;
- clock_limits[k].dtbclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dtbclk_mhz;
- clock_limits[k].phyclk_d18_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz;
- clock_limits[k].phyclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].phyclk_mhz;
+ dcn2_1_soc.clock_limits[k].dispclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dispclk_mhz;
+ dcn2_1_soc.clock_limits[k].dppclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dppclk_mhz;
+ dcn2_1_soc.clock_limits[k].dram_bw_per_chan_gbps = dcn2_1_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan_gbps;
+ dcn2_1_soc.clock_limits[k].dscclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dscclk_mhz;
+ dcn2_1_soc.clock_limits[k].dtbclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dtbclk_mhz;
+ dcn2_1_soc.clock_limits[k].phyclk_d18_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz;
+ dcn2_1_soc.clock_limits[k].phyclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].phyclk_mhz;
k++;
}
- for (i = 0; i < clk_table->num_entries + 1; i++)
- dcn2_1_soc.clock_limits[i] = clock_limits[i];
if (clk_table->num_entries) {
dcn2_1_soc.num_states = clk_table->num_entries + 1;
/* fill in min DF PState */
--
2.25.1
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [PATCH 6/6] Revert "drm/amd/display: Drop unnecessary guard from DC resource"
2022-06-03 18:50 [PATCH 0/6] Cleaning up some GCC warnings and other minor issues Rodrigo Siqueira
` (4 preceding siblings ...)
2022-06-03 18:50 ` [PATCH 5/6] drm/amd/display: Reduce frame size in the bouding box for DCN21 Rodrigo Siqueira
@ 2022-06-03 18:50 ` Rodrigo Siqueira
2022-06-06 14:16 ` Harry Wentland
2022-06-03 19:40 ` [PATCH 0/6] Cleaning up some GCC warnings and other minor issues Alex Deucher
6 siblings, 1 reply; 17+ messages in thread
From: Rodrigo Siqueira @ 2022-06-03 18:50 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher
This reverts commit 78baa3c4dfff4375b109bc5e19663a2f7fad1190.
This commit introduced the below compilation error when using
allmodconfig:
error: implicit declaration of function ‘remove_hpo_dp_link_enc_from_ctx’; did you mean ‘add_hpo_dp_link_enc_to_ctx’? [-Werror=implicit-function-declaration]
2010 | remove_hpo_dp_link_enc_from_ctx(&new_ctx->res_ctx, del_pipe, del_pipe->stream);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
| add_hpo_dp_link_enc_to_ctx
Fixes: 78baa3c4dfff43 ("drm/amd/display: Drop unnecessary guard from DC resource")
Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
---
drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index 7357efb8b439..9bbdfcd6b3a4 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -2002,6 +2002,7 @@ enum dc_status dc_remove_stream_from_ctx(
if (dc->res_pool->funcs->link_enc_unassign)
dc->res_pool->funcs->link_enc_unassign(new_ctx, del_pipe->stream);
+#if defined(CONFIG_DRM_AMD_DC_DCN)
if (is_dp_128b_132b_signal(del_pipe)) {
update_hpo_dp_stream_engine_usage(
&new_ctx->res_ctx, dc->res_pool,
@@ -2009,6 +2010,7 @@ enum dc_status dc_remove_stream_from_ctx(
false);
remove_hpo_dp_link_enc_from_ctx(&new_ctx->res_ctx, del_pipe, del_pipe->stream);
}
+#endif
if (del_pipe->stream_res.audio)
update_audio_usage(
--
2.25.1
^ permalink raw reply related [flat|nested] 17+ messages in thread
* Re: [PATCH 0/6] Cleaning up some GCC warnings and other minor issues
2022-06-03 18:50 [PATCH 0/6] Cleaning up some GCC warnings and other minor issues Rodrigo Siqueira
` (5 preceding siblings ...)
2022-06-03 18:50 ` [PATCH 6/6] Revert "drm/amd/display: Drop unnecessary guard from DC resource" Rodrigo Siqueira
@ 2022-06-03 19:40 ` Alex Deucher
6 siblings, 0 replies; 17+ messages in thread
From: Alex Deucher @ 2022-06-03 19:40 UTC (permalink / raw)
To: Rodrigo Siqueira; +Cc: Alex Deucher, amd-gfx list
On Fri, Jun 3, 2022 at 2:51 PM Rodrigo Siqueira
<Rodrigo.Siqueira@amd.com> wrote:
>
> It looks like that we have some new warnings on display code and a
> compilation error when using allmodconfig. This series clean up some of
> the DML warnings and fix the compilation problem with allmodeconfig.
>
> Thanks
>
> Rodrigo Siqueira (6):
> drm/amd/display: Remove duplicated macro
> drm/amd/display: Reduce frame size in the bouding box for DCN20
> drm/amd/display: Reduce frame size in the bouding box for DCN301
> drm/amd/display: Reduce frame size in the bouding box for DCN31/316
> drm/amd/display: Reduce frame size in the bouding box for DCN21
> Revert "drm/amd/display: Drop unnecessary guard from DC resource"
Series is:
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
>
> .../gpu/drm/amd/display/dc/core/dc_resource.c | 2 +
> .../drm/amd/display/dc/dml/dcn20/dcn20_fpu.c | 67 +++++++++----------
> .../amd/display/dc/dml/dcn301/dcn301_fpu.c | 30 ++++-----
> .../drm/amd/display/dc/dml/dcn31/dcn31_fpu.c | 58 +++++++---------
> .../gpu/drm/amd/display/include/dal_asic_id.h | 6 --
> 5 files changed, 72 insertions(+), 91 deletions(-)
>
> --
> 2.25.1
>
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 1/6] drm/amd/display: Remove duplicated macro
2022-06-03 18:50 ` [PATCH 1/6] drm/amd/display: Remove duplicated macro Rodrigo Siqueira
@ 2022-06-06 14:04 ` Harry Wentland
0 siblings, 0 replies; 17+ messages in thread
From: Harry Wentland @ 2022-06-06 14:04 UTC (permalink / raw)
To: Rodrigo Siqueira, amd-gfx; +Cc: Alex Deucher
On 2022-06-03 14:50, Rodrigo Siqueira wrote:
> Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Harry
> ---
> drivers/gpu/drm/amd/display/include/dal_asic_id.h | 6 ------
> 1 file changed, 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/include/dal_asic_id.h b/drivers/gpu/drm/amd/display/include/dal_asic_id.h
> index 11391eead954..a0dffe30b394 100644
> --- a/drivers/gpu/drm/amd/display/include/dal_asic_id.h
> +++ b/drivers/gpu/drm/amd/display/include/dal_asic_id.h
> @@ -221,10 +221,6 @@ enum {
> #ifndef ASICREV_IS_VANGOGH
> #define ASICREV_IS_VANGOGH(eChipRev) ((eChipRev >= VANGOGH_A0) && (eChipRev < VANGOGH_UNKNOWN))
> #endif
> -#define GREEN_SARDINE_A0 0xA1
> -#ifndef ASICREV_IS_GREEN_SARDINE
> -#define ASICREV_IS_GREEN_SARDINE(eChipRev) ((eChipRev >= GREEN_SARDINE_A0) && (eChipRev < 0xFF))
> -#endif
>
> #define FAMILY_YELLOW_CARP 146
> #define YELLOW_CARP_A0 0x01
> @@ -288,6 +284,4 @@ enum {
>
> #define FAMILY_UNKNOWN 0xFF
>
> -
> -
> #endif /* __DAL_ASIC_ID_H__ */
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 2/6] drm/amd/display: Reduce frame size in the bouding box for DCN20
2022-06-03 18:50 ` [PATCH 2/6] drm/amd/display: Reduce frame size in the bouding box for DCN20 Rodrigo Siqueira
@ 2022-06-06 14:05 ` Harry Wentland
0 siblings, 0 replies; 17+ messages in thread
From: Harry Wentland @ 2022-06-06 14:05 UTC (permalink / raw)
To: Rodrigo Siqueira, amd-gfx
Cc: Alex Deucher, Stephen Rothwell, Aurabindo Pillai, Hamza Mahfooz
On 2022-06-03 14:50, Rodrigo Siqueira wrote:
> GCC throw warnings for the function dcn20_update_bounding_box due to its
> frame size that looks like this:
>
> error: the frame size of 1936 bytes is larger than 1024 bytes [-Werror=frame-larger-than=]
>
> This commit fixes this issue by eliminating an intermediary variable
> that creates a large array.
>
> Cc: Stephen Rothwell <sfr@canb.auug.org.au>
> Cc: Hamza Mahfooz <hamza.mahfooz@amd.com>
> Cc: Aurabindo Pillai <aurabindo.pillai@amd.com>
> Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Harry
> ---
> .../drm/amd/display/dc/dml/dcn20/dcn20_fpu.c | 38 +++++++++----------
> 1 file changed, 18 insertions(+), 20 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
> index eeec40f6fd0a..d9cc178f6980 100644
> --- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
> +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
> @@ -1456,21 +1456,20 @@ void dcn20_calculate_wm(
> void dcn20_update_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb,
> struct pp_smu_nv_clock_table *max_clocks, unsigned int *uclk_states, unsigned int num_states)
> {
> - struct _vcs_dpi_voltage_scaling_st calculated_states[DC__VOLTAGE_STATES];
> - int i;
> int num_calculated_states = 0;
> int min_dcfclk = 0;
> + int i;
>
> dc_assert_fp_enabled();
>
> if (num_states == 0)
> return;
>
> - memset(calculated_states, 0, sizeof(calculated_states));
> + memset(bb->clock_limits, 0, sizeof(bb->clock_limits));
>
> - if (dc->bb_overrides.min_dcfclk_mhz > 0)
> + if (dc->bb_overrides.min_dcfclk_mhz > 0) {
> min_dcfclk = dc->bb_overrides.min_dcfclk_mhz;
> - else {
> + } else {
> if (ASICREV_IS_NAVI12_P(dc->ctx->asic_id.hw_internal_rev))
> min_dcfclk = 310;
> else
> @@ -1481,36 +1480,35 @@ void dcn20_update_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_s
>
> for (i = 0; i < num_states; i++) {
> int min_fclk_required_by_uclk;
> - calculated_states[i].state = i;
> - calculated_states[i].dram_speed_mts = uclk_states[i] * 16 / 1000;
> + bb->clock_limits[i].state = i;
> + bb->clock_limits[i].dram_speed_mts = uclk_states[i] * 16 / 1000;
>
> // FCLK:UCLK ratio is 1.08
> min_fclk_required_by_uclk = div_u64(((unsigned long long)uclk_states[i]) * 1080,
> 1000000);
>
> - calculated_states[i].fabricclk_mhz = (min_fclk_required_by_uclk < min_dcfclk) ?
> + bb->clock_limits[i].fabricclk_mhz = (min_fclk_required_by_uclk < min_dcfclk) ?
> min_dcfclk : min_fclk_required_by_uclk;
>
> - calculated_states[i].socclk_mhz = (calculated_states[i].fabricclk_mhz > max_clocks->socClockInKhz / 1000) ?
> - max_clocks->socClockInKhz / 1000 : calculated_states[i].fabricclk_mhz;
> + bb->clock_limits[i].socclk_mhz = (bb->clock_limits[i].fabricclk_mhz > max_clocks->socClockInKhz / 1000) ?
> + max_clocks->socClockInKhz / 1000 : bb->clock_limits[i].fabricclk_mhz;
>
> - calculated_states[i].dcfclk_mhz = (calculated_states[i].fabricclk_mhz > max_clocks->dcfClockInKhz / 1000) ?
> - max_clocks->dcfClockInKhz / 1000 : calculated_states[i].fabricclk_mhz;
> + bb->clock_limits[i].dcfclk_mhz = (bb->clock_limits[i].fabricclk_mhz > max_clocks->dcfClockInKhz / 1000) ?
> + max_clocks->dcfClockInKhz / 1000 : bb->clock_limits[i].fabricclk_mhz;
>
> - calculated_states[i].dispclk_mhz = max_clocks->displayClockInKhz / 1000;
> - calculated_states[i].dppclk_mhz = max_clocks->displayClockInKhz / 1000;
> - calculated_states[i].dscclk_mhz = max_clocks->displayClockInKhz / (1000 * 3);
> + bb->clock_limits[i].dispclk_mhz = max_clocks->displayClockInKhz / 1000;
> + bb->clock_limits[i].dppclk_mhz = max_clocks->displayClockInKhz / 1000;
> + bb->clock_limits[i].dscclk_mhz = max_clocks->displayClockInKhz / (1000 * 3);
>
> - calculated_states[i].phyclk_mhz = max_clocks->phyClockInKhz / 1000;
> + bb->clock_limits[i].phyclk_mhz = max_clocks->phyClockInKhz / 1000;
>
> num_calculated_states++;
> }
>
> - calculated_states[num_calculated_states - 1].socclk_mhz = max_clocks->socClockInKhz / 1000;
> - calculated_states[num_calculated_states - 1].fabricclk_mhz = max_clocks->socClockInKhz / 1000;
> - calculated_states[num_calculated_states - 1].dcfclk_mhz = max_clocks->dcfClockInKhz / 1000;
> + bb->clock_limits[num_calculated_states - 1].socclk_mhz = max_clocks->socClockInKhz / 1000;
> + bb->clock_limits[num_calculated_states - 1].fabricclk_mhz = max_clocks->socClockInKhz / 1000;
> + bb->clock_limits[num_calculated_states - 1].dcfclk_mhz = max_clocks->dcfClockInKhz / 1000;
>
> - memcpy(bb->clock_limits, calculated_states, sizeof(bb->clock_limits));
> bb->num_states = num_calculated_states;
>
> // Duplicate the last state, DML always an extra state identical to max state to work
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 3/6] drm/amd/display: Reduce frame size in the bouding box for DCN301
2022-06-03 18:50 ` [PATCH 3/6] drm/amd/display: Reduce frame size in the bouding box for DCN301 Rodrigo Siqueira
@ 2022-06-06 14:08 ` Harry Wentland
0 siblings, 0 replies; 17+ messages in thread
From: Harry Wentland @ 2022-06-06 14:08 UTC (permalink / raw)
To: Rodrigo Siqueira, amd-gfx
Cc: Alex Deucher, Stephen Rothwell, Aurabindo Pillai, Hamza Mahfooz
On 2022-06-03 14:50, Rodrigo Siqueira wrote:
> GCC throw warnings for the function dcn301_fpu_update_bw_bounding_box
> due to its frame size that looks like this:
>
> error: the frame size of 1936 bytes is larger than 1024 bytes [-Werror=frame-larger-than=]
>
> For fixing this issue I dropped an intermadiate variable.
>
> Cc: Stephen Rothwell <sfr@canb.auug.org.au>
> Cc: Hamza Mahfooz <hamza.mahfooz@amd.com>
> Cc: Aurabindo Pillai <aurabindo.pillai@amd.com>
> Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Harry
> ---
> .../amd/display/dc/dml/dcn301/dcn301_fpu.c | 30 ++++++++-----------
> 1 file changed, 13 insertions(+), 17 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c
> index 0a7a33864973..62cf283d9f41 100644
> --- a/drivers/gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c
> +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c
> @@ -249,7 +249,6 @@ void dcn301_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_param
> {
> struct dcn301_resource_pool *pool = TO_DCN301_RES_POOL(dc->res_pool);
> struct clk_limit_table *clk_table = &bw_params->clk_table;
> - struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES];
> unsigned int i, closest_clk_lvl;
> int j;
>
> @@ -271,24 +270,21 @@ void dcn301_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_param
> }
> }
>
> - clock_limits[i].state = i;
> - clock_limits[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz;
> - clock_limits[i].fabricclk_mhz = clk_table->entries[i].fclk_mhz;
> - clock_limits[i].socclk_mhz = clk_table->entries[i].socclk_mhz;
> - clock_limits[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2;
> -
> - clock_limits[i].dispclk_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].dispclk_mhz;
> - clock_limits[i].dppclk_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].dppclk_mhz;
> - clock_limits[i].dram_bw_per_chan_gbps = dcn3_01_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan_gbps;
> - clock_limits[i].dscclk_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].dscclk_mhz;
> - clock_limits[i].dtbclk_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].dtbclk_mhz;
> - clock_limits[i].phyclk_d18_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz;
> - clock_limits[i].phyclk_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].phyclk_mhz;
> + dcn3_01_soc.clock_limits[i].state = i;
> + dcn3_01_soc.clock_limits[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz;
> + dcn3_01_soc.clock_limits[i].fabricclk_mhz = clk_table->entries[i].fclk_mhz;
> + dcn3_01_soc.clock_limits[i].socclk_mhz = clk_table->entries[i].socclk_mhz;
> + dcn3_01_soc.clock_limits[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2;
> +
> + dcn3_01_soc.clock_limits[i].dispclk_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].dispclk_mhz;
> + dcn3_01_soc.clock_limits[i].dppclk_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].dppclk_mhz;
> + dcn3_01_soc.clock_limits[i].dram_bw_per_chan_gbps = dcn3_01_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan_gbps;
> + dcn3_01_soc.clock_limits[i].dscclk_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].dscclk_mhz;
> + dcn3_01_soc.clock_limits[i].dtbclk_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].dtbclk_mhz;
> + dcn3_01_soc.clock_limits[i].phyclk_d18_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz;
> + dcn3_01_soc.clock_limits[i].phyclk_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].phyclk_mhz;
> }
>
> - for (i = 0; i < clk_table->num_entries; i++)
> - dcn3_01_soc.clock_limits[i] = clock_limits[i];
> -
> if (clk_table->num_entries) {
> dcn3_01_soc.num_states = clk_table->num_entries;
> /* duplicate last level */
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 4/6] drm/amd/display: Reduce frame size in the bouding box for DCN31/316
2022-06-03 18:50 ` [PATCH 4/6] drm/amd/display: Reduce frame size in the bouding box for DCN31/316 Rodrigo Siqueira
@ 2022-06-06 14:10 ` Harry Wentland
0 siblings, 0 replies; 17+ messages in thread
From: Harry Wentland @ 2022-06-06 14:10 UTC (permalink / raw)
To: Rodrigo Siqueira, amd-gfx
Cc: Alex Deucher, Stephen Rothwell, Aurabindo Pillai, Hamza Mahfooz
On 2022-06-03 14:50, Rodrigo Siqueira wrote:
> GCC throw warnings for the function dcn31_update_bw_bounding_box and
> dcn316_update_bw_bounding_box due to its frame size that looks like
> this:
>
> error: the frame size of 1936 bytes is larger than 1024 bytes [-Werror=frame-larger-than=]
>
> For fixing this issue I dropped an intermadiate variable.
>
> Cc: Stephen Rothwell <sfr@canb.auug.org.au>
> Cc: Hamza Mahfooz <hamza.mahfooz@amd.com>
> Cc: Aurabindo Pillai <aurabindo.pillai@amd.com>
> Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Harry
> ---
> .../drm/amd/display/dc/dml/dcn31/dcn31_fpu.c | 58 +++++++++----------
> 1 file changed, 26 insertions(+), 32 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c
> index 54db2eca9e6b..ee898bc93fd5 100644
> --- a/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c
> +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c
> @@ -574,7 +574,6 @@ void dcn31_calculate_wm_and_dlg_fp(
> void dcn31_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
> {
> struct clk_limit_table *clk_table = &bw_params->clk_table;
> - struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES];
> unsigned int i, closest_clk_lvl;
> int j;
>
> @@ -607,29 +606,27 @@ void dcn31_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params
> }
> }
>
> - clock_limits[i].state = i;
> + dcn3_1_soc.clock_limits[i].state = i;
>
> /* Clocks dependent on voltage level. */
> - clock_limits[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz;
> - clock_limits[i].fabricclk_mhz = clk_table->entries[i].fclk_mhz;
> - clock_limits[i].socclk_mhz = clk_table->entries[i].socclk_mhz;
> - clock_limits[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2 * clk_table->entries[i].wck_ratio;
> + dcn3_1_soc.clock_limits[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz;
> + dcn3_1_soc.clock_limits[i].fabricclk_mhz = clk_table->entries[i].fclk_mhz;
> + dcn3_1_soc.clock_limits[i].socclk_mhz = clk_table->entries[i].socclk_mhz;
> + dcn3_1_soc.clock_limits[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2 * clk_table->entries[i].wck_ratio;
>
> /* Clocks independent of voltage level. */
> - clock_limits[i].dispclk_mhz = max_dispclk_mhz ? max_dispclk_mhz :
> + dcn3_1_soc.clock_limits[i].dispclk_mhz = max_dispclk_mhz ? max_dispclk_mhz :
> dcn3_1_soc.clock_limits[closest_clk_lvl].dispclk_mhz;
>
> - clock_limits[i].dppclk_mhz = max_dppclk_mhz ? max_dppclk_mhz :
> + dcn3_1_soc.clock_limits[i].dppclk_mhz = max_dppclk_mhz ? max_dppclk_mhz :
> dcn3_1_soc.clock_limits[closest_clk_lvl].dppclk_mhz;
>
> - clock_limits[i].dram_bw_per_chan_gbps = dcn3_1_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan_gbps;
> - clock_limits[i].dscclk_mhz = dcn3_1_soc.clock_limits[closest_clk_lvl].dscclk_mhz;
> - clock_limits[i].dtbclk_mhz = dcn3_1_soc.clock_limits[closest_clk_lvl].dtbclk_mhz;
> - clock_limits[i].phyclk_d18_mhz = dcn3_1_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz;
> - clock_limits[i].phyclk_mhz = dcn3_1_soc.clock_limits[closest_clk_lvl].phyclk_mhz;
> + dcn3_1_soc.clock_limits[i].dram_bw_per_chan_gbps = dcn3_1_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan_gbps;
> + dcn3_1_soc.clock_limits[i].dscclk_mhz = dcn3_1_soc.clock_limits[closest_clk_lvl].dscclk_mhz;
> + dcn3_1_soc.clock_limits[i].dtbclk_mhz = dcn3_1_soc.clock_limits[closest_clk_lvl].dtbclk_mhz;
> + dcn3_1_soc.clock_limits[i].phyclk_d18_mhz = dcn3_1_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz;
> + dcn3_1_soc.clock_limits[i].phyclk_mhz = dcn3_1_soc.clock_limits[closest_clk_lvl].phyclk_mhz;
> }
> - for (i = 0; i < clk_table->num_entries; i++)
> - dcn3_1_soc.clock_limits[i] = clock_limits[i];
> if (clk_table->num_entries) {
> dcn3_1_soc.num_states = clk_table->num_entries;
> }
> @@ -701,7 +698,6 @@ void dcn315_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_param
> void dcn316_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
> {
> struct clk_limit_table *clk_table = &bw_params->clk_table;
> - struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES];
> unsigned int i, closest_clk_lvl;
> int max_dispclk_mhz = 0, max_dppclk_mhz = 0;
> int j;
> @@ -739,34 +735,32 @@ void dcn316_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_param
> closest_clk_lvl = dcn3_16_soc.num_states - 1;
> }
>
> - clock_limits[i].state = i;
> + dcn3_16_soc.clock_limits[i].state = i;
>
> /* Clocks dependent on voltage level. */
> - clock_limits[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz;
> + dcn3_16_soc.clock_limits[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz;
> if (clk_table->num_entries == 1 &&
> - clock_limits[i].dcfclk_mhz < dcn3_16_soc.clock_limits[closest_clk_lvl].dcfclk_mhz) {
> + dcn3_16_soc.clock_limits[i].dcfclk_mhz < dcn3_16_soc.clock_limits[closest_clk_lvl].dcfclk_mhz) {
> /*SMU fix not released yet*/
> - clock_limits[i].dcfclk_mhz = dcn3_16_soc.clock_limits[closest_clk_lvl].dcfclk_mhz;
> + dcn3_16_soc.clock_limits[i].dcfclk_mhz = dcn3_16_soc.clock_limits[closest_clk_lvl].dcfclk_mhz;
> }
> - clock_limits[i].fabricclk_mhz = clk_table->entries[i].fclk_mhz;
> - clock_limits[i].socclk_mhz = clk_table->entries[i].socclk_mhz;
> - clock_limits[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2 * clk_table->entries[i].wck_ratio;
> + dcn3_16_soc.clock_limits[i].fabricclk_mhz = clk_table->entries[i].fclk_mhz;
> + dcn3_16_soc.clock_limits[i].socclk_mhz = clk_table->entries[i].socclk_mhz;
> + dcn3_16_soc.clock_limits[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2 * clk_table->entries[i].wck_ratio;
>
> /* Clocks independent of voltage level. */
> - clock_limits[i].dispclk_mhz = max_dispclk_mhz ? max_dispclk_mhz :
> + dcn3_16_soc.clock_limits[i].dispclk_mhz = max_dispclk_mhz ? max_dispclk_mhz :
> dcn3_16_soc.clock_limits[closest_clk_lvl].dispclk_mhz;
>
> - clock_limits[i].dppclk_mhz = max_dppclk_mhz ? max_dppclk_mhz :
> + dcn3_16_soc.clock_limits[i].dppclk_mhz = max_dppclk_mhz ? max_dppclk_mhz :
> dcn3_16_soc.clock_limits[closest_clk_lvl].dppclk_mhz;
>
> - clock_limits[i].dram_bw_per_chan_gbps = dcn3_16_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan_gbps;
> - clock_limits[i].dscclk_mhz = dcn3_16_soc.clock_limits[closest_clk_lvl].dscclk_mhz;
> - clock_limits[i].dtbclk_mhz = dcn3_16_soc.clock_limits[closest_clk_lvl].dtbclk_mhz;
> - clock_limits[i].phyclk_d18_mhz = dcn3_16_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz;
> - clock_limits[i].phyclk_mhz = dcn3_16_soc.clock_limits[closest_clk_lvl].phyclk_mhz;
> + dcn3_16_soc.clock_limits[i].dram_bw_per_chan_gbps = dcn3_16_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan_gbps;
> + dcn3_16_soc.clock_limits[i].dscclk_mhz = dcn3_16_soc.clock_limits[closest_clk_lvl].dscclk_mhz;
> + dcn3_16_soc.clock_limits[i].dtbclk_mhz = dcn3_16_soc.clock_limits[closest_clk_lvl].dtbclk_mhz;
> + dcn3_16_soc.clock_limits[i].phyclk_d18_mhz = dcn3_16_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz;
> + dcn3_16_soc.clock_limits[i].phyclk_mhz = dcn3_16_soc.clock_limits[closest_clk_lvl].phyclk_mhz;
> }
> - for (i = 0; i < clk_table->num_entries; i++)
> - dcn3_16_soc.clock_limits[i] = clock_limits[i];
> if (clk_table->num_entries) {
> dcn3_16_soc.num_states = clk_table->num_entries;
> }
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 5/6] drm/amd/display: Reduce frame size in the bouding box for DCN21
2022-06-03 18:50 ` [PATCH 5/6] drm/amd/display: Reduce frame size in the bouding box for DCN21 Rodrigo Siqueira
@ 2022-06-06 14:11 ` Harry Wentland
0 siblings, 0 replies; 17+ messages in thread
From: Harry Wentland @ 2022-06-06 14:11 UTC (permalink / raw)
To: Rodrigo Siqueira, amd-gfx
Cc: Alex Deucher, Stephen Rothwell, Aurabindo Pillai, Hamza Mahfooz
On 2022-06-03 14:50, Rodrigo Siqueira wrote:
> GCC throw warnings for the function dcn21_update_bw_bounding_box and
> dcn316_update_bw_bounding_box due to its frame size that looks like
> this:
>
> error: the frame size of 1936 bytes is larger than 1024 bytes [-Werror=frame-larger-than=]
>
> For fixing this issue I dropped an intermadiate variable.
>
> Cc: Stephen Rothwell <sfr@canb.auug.org.au>
> Cc: Hamza Mahfooz <hamza.mahfooz@amd.com>
> Cc: Aurabindo Pillai <aurabindo.pillai@amd.com>
> Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Harry
> ---
> .../drm/amd/display/dc/dml/dcn20/dcn20_fpu.c | 29 +++++++++----------
> 1 file changed, 13 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
> index d9cc178f6980..c2fec0d85da4 100644
> --- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
> +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
> @@ -2004,7 +2004,6 @@ void dcn21_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params
> {
> struct dcn21_resource_pool *pool = TO_DCN21_RES_POOL(dc->res_pool);
> struct clk_limit_table *clk_table = &bw_params->clk_table;
> - struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES];
> unsigned int i, closest_clk_lvl = 0, k = 0;
> int j;
>
> @@ -2017,7 +2016,7 @@ void dcn21_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params
> ASSERT(clk_table->num_entries);
> /* Copy dcn2_1_soc.clock_limits to clock_limits to avoid copying over null states later */
> for (i = 0; i < dcn2_1_soc.num_states + 1; i++) {
> - clock_limits[i] = dcn2_1_soc.clock_limits[i];
> + dcn2_1_soc.clock_limits[i] = dcn2_1_soc.clock_limits[i];
> }
>
> for (i = 0; i < clk_table->num_entries; i++) {
> @@ -2033,24 +2032,22 @@ void dcn21_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params
> if (i == 1)
> k++;
>
> - clock_limits[k].state = k;
> - clock_limits[k].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz;
> - clock_limits[k].fabricclk_mhz = clk_table->entries[i].fclk_mhz;
> - clock_limits[k].socclk_mhz = clk_table->entries[i].socclk_mhz;
> - clock_limits[k].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2;
> + dcn2_1_soc.clock_limits[k].state = k;
> + dcn2_1_soc.clock_limits[k].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz;
> + dcn2_1_soc.clock_limits[k].fabricclk_mhz = clk_table->entries[i].fclk_mhz;
> + dcn2_1_soc.clock_limits[k].socclk_mhz = clk_table->entries[i].socclk_mhz;
> + dcn2_1_soc.clock_limits[k].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2;
>
> - clock_limits[k].dispclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dispclk_mhz;
> - clock_limits[k].dppclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dppclk_mhz;
> - clock_limits[k].dram_bw_per_chan_gbps = dcn2_1_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan_gbps;
> - clock_limits[k].dscclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dscclk_mhz;
> - clock_limits[k].dtbclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dtbclk_mhz;
> - clock_limits[k].phyclk_d18_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz;
> - clock_limits[k].phyclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].phyclk_mhz;
> + dcn2_1_soc.clock_limits[k].dispclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dispclk_mhz;
> + dcn2_1_soc.clock_limits[k].dppclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dppclk_mhz;
> + dcn2_1_soc.clock_limits[k].dram_bw_per_chan_gbps = dcn2_1_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan_gbps;
> + dcn2_1_soc.clock_limits[k].dscclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dscclk_mhz;
> + dcn2_1_soc.clock_limits[k].dtbclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dtbclk_mhz;
> + dcn2_1_soc.clock_limits[k].phyclk_d18_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz;
> + dcn2_1_soc.clock_limits[k].phyclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].phyclk_mhz;
>
> k++;
> }
> - for (i = 0; i < clk_table->num_entries + 1; i++)
> - dcn2_1_soc.clock_limits[i] = clock_limits[i];
> if (clk_table->num_entries) {
> dcn2_1_soc.num_states = clk_table->num_entries + 1;
> /* fill in min DF PState */
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 6/6] Revert "drm/amd/display: Drop unnecessary guard from DC resource"
2022-06-03 18:50 ` [PATCH 6/6] Revert "drm/amd/display: Drop unnecessary guard from DC resource" Rodrigo Siqueira
@ 2022-06-06 14:16 ` Harry Wentland
2022-06-06 16:17 ` Alex Deucher
0 siblings, 1 reply; 17+ messages in thread
From: Harry Wentland @ 2022-06-06 14:16 UTC (permalink / raw)
To: Rodrigo Siqueira, amd-gfx; +Cc: Alex Deucher
On 2022-06-03 14:50, Rodrigo Siqueira wrote:
> This reverts commit 78baa3c4dfff4375b109bc5e19663a2f7fad1190.
>
> This commit introduced the below compilation error when using
> allmodconfig:
>
> error: implicit declaration of function ‘remove_hpo_dp_link_enc_from_ctx’; did you mean ‘add_hpo_dp_link_enc_to_ctx’? [-Werror=implicit-function-declaration]
> 2010 | remove_hpo_dp_link_enc_from_ctx(&new_ctx->res_ctx, del_pipe, del_pipe->stream);
> | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> | add_hpo_dp_link_enc_to_ctx
>
> Fixes: 78baa3c4dfff43 ("drm/amd/display: Drop unnecessary guard from DC resource")
> Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
> ---
> drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
> index 7357efb8b439..9bbdfcd6b3a4 100644
> --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
> +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
> @@ -2002,6 +2002,7 @@ enum dc_status dc_remove_stream_from_ctx(
> if (dc->res_pool->funcs->link_enc_unassign)
> dc->res_pool->funcs->link_enc_unassign(new_ctx, del_pipe->stream);
>
> +#if defined(CONFIG_DRM_AMD_DC_DCN)
> if (is_dp_128b_132b_signal(del_pipe)) {
> update_hpo_dp_stream_engine_usage(
> &new_ctx->res_ctx, dc->res_pool,
> @@ -2009,6 +2010,7 @@ enum dc_status dc_remove_stream_from_ctx(
> false);
> remove_hpo_dp_link_enc_from_ctx(&new_ctx->res_ctx, del_pipe, del_pipe->stream);
Wouldn't a better solution be to drop the DCN guards around
remove_hpo_dp_link_enc_from_ctx and release_hpo_dp_link_enc?
Not sure why those were guarded in the first place.
Harry
> }
> +#endif
>
> if (del_pipe->stream_res.audio)
> update_audio_usage(
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 6/6] Revert "drm/amd/display: Drop unnecessary guard from DC resource"
2022-06-06 14:16 ` Harry Wentland
@ 2022-06-06 16:17 ` Alex Deucher
2022-06-06 18:01 ` Harry Wentland
0 siblings, 1 reply; 17+ messages in thread
From: Alex Deucher @ 2022-06-06 16:17 UTC (permalink / raw)
To: Harry Wentland; +Cc: Alex Deucher, Rodrigo Siqueira, amd-gfx list
On Mon, Jun 6, 2022 at 10:16 AM Harry Wentland <harry.wentland@amd.com> wrote:
>
> On 2022-06-03 14:50, Rodrigo Siqueira wrote:
> > This reverts commit 78baa3c4dfff4375b109bc5e19663a2f7fad1190.
> >
> > This commit introduced the below compilation error when using
> > allmodconfig:
> >
> > error: implicit declaration of function ‘remove_hpo_dp_link_enc_from_ctx’; did you mean ‘add_hpo_dp_link_enc_to_ctx’? [-Werror=implicit-function-declaration]
> > 2010 | remove_hpo_dp_link_enc_from_ctx(&new_ctx->res_ctx, del_pipe, del_pipe->stream);
> > | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> > | add_hpo_dp_link_enc_to_ctx
> >
> > Fixes: 78baa3c4dfff43 ("drm/amd/display: Drop unnecessary guard from DC resource")
> > Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
> > ---
> > drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 2 ++
> > 1 file changed, 2 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
> > index 7357efb8b439..9bbdfcd6b3a4 100644
> > --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
> > +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
> > @@ -2002,6 +2002,7 @@ enum dc_status dc_remove_stream_from_ctx(
> > if (dc->res_pool->funcs->link_enc_unassign)
> > dc->res_pool->funcs->link_enc_unassign(new_ctx, del_pipe->stream);
> >
> > +#if defined(CONFIG_DRM_AMD_DC_DCN)
> > if (is_dp_128b_132b_signal(del_pipe)) {
> > update_hpo_dp_stream_engine_usage(
> > &new_ctx->res_ctx, dc->res_pool,
> > @@ -2009,6 +2010,7 @@ enum dc_status dc_remove_stream_from_ctx(
> > false);
> > remove_hpo_dp_link_enc_from_ctx(&new_ctx->res_ctx, del_pipe, del_pipe->stream);
>
> Wouldn't a better solution be to drop the DCN guards around
> remove_hpo_dp_link_enc_from_ctx and release_hpo_dp_link_enc?
> Not sure why those were guarded in the first place.
They were added by me in:
commit d8e4fb9112e88d8d87ffbc38fa511e7118042d4f
Author: Alex Deucher <alexander.deucher@amd.com>
Date: Wed Jun 1 22:22:07 2022 -0400
drm/amdgpu/display: Protect some functions with CONFIG_DRM_AMD_DC_DCN
Protect remove_hpo_dp_link_enc_from_ctx() and release_hpo_dp_link_enc()
with CONFIG_DRM_AMD_DC_DCN as the functions are only called from code
that is protected by CONFIG_DRM_AMD_DC_DCN. Fixes build fail with
-Werror=unused-function.
Fixes: 9b0e0d433f74 ("drm/amd/display: Add dependant changes for DCN32/321")
Reported-by: Stephen Rothwell <sfr@canb.auug.org.au>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: Aurabindo Pillai <aurabindo.pillai@amd.com>
Maybe they are no longer required?
Alex
>
> Harry
>
> > }
> > +#endif
> >
> > if (del_pipe->stream_res.audio)
> > update_audio_usage(
>
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 6/6] Revert "drm/amd/display: Drop unnecessary guard from DC resource"
2022-06-06 16:17 ` Alex Deucher
@ 2022-06-06 18:01 ` Harry Wentland
2022-06-06 18:04 ` Alex Deucher
0 siblings, 1 reply; 17+ messages in thread
From: Harry Wentland @ 2022-06-06 18:01 UTC (permalink / raw)
To: Alex Deucher; +Cc: Alex Deucher, Rodrigo Siqueira, amd-gfx list
On 2022-06-06 12:17, Alex Deucher wrote:
> On Mon, Jun 6, 2022 at 10:16 AM Harry Wentland <harry.wentland@amd.com> wrote:
>>
>> On 2022-06-03 14:50, Rodrigo Siqueira wrote:
>>> This reverts commit 78baa3c4dfff4375b109bc5e19663a2f7fad1190.
>>>
>>> This commit introduced the below compilation error when using
>>> allmodconfig:
>>>
>>> error: implicit declaration of function ‘remove_hpo_dp_link_enc_from_ctx’; did you mean ‘add_hpo_dp_link_enc_to_ctx’? [-Werror=implicit-function-declaration]
>>> 2010 | remove_hpo_dp_link_enc_from_ctx(&new_ctx->res_ctx, del_pipe, del_pipe->stream);
>>> | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
>>> | add_hpo_dp_link_enc_to_ctx
>>>
>>> Fixes: 78baa3c4dfff43 ("drm/amd/display: Drop unnecessary guard from DC resource")
>>> Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
>>> ---
>>> drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 2 ++
>>> 1 file changed, 2 insertions(+)
>>>
>>> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
>>> index 7357efb8b439..9bbdfcd6b3a4 100644
>>> --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
>>> +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
>>> @@ -2002,6 +2002,7 @@ enum dc_status dc_remove_stream_from_ctx(
>>> if (dc->res_pool->funcs->link_enc_unassign)
>>> dc->res_pool->funcs->link_enc_unassign(new_ctx, del_pipe->stream);
>>>
>>> +#if defined(CONFIG_DRM_AMD_DC_DCN)
>>> if (is_dp_128b_132b_signal(del_pipe)) {
>>> update_hpo_dp_stream_engine_usage(
>>> &new_ctx->res_ctx, dc->res_pool,
>>> @@ -2009,6 +2010,7 @@ enum dc_status dc_remove_stream_from_ctx(
>>> false);
>>> remove_hpo_dp_link_enc_from_ctx(&new_ctx->res_ctx, del_pipe, del_pipe->stream);
>>
>> Wouldn't a better solution be to drop the DCN guards around
>> remove_hpo_dp_link_enc_from_ctx and release_hpo_dp_link_enc?
>> Not sure why those were guarded in the first place.
>
> They were added by me in:
>
> commit d8e4fb9112e88d8d87ffbc38fa511e7118042d4f
> Author: Alex Deucher <alexander.deucher@amd.com>
> Date: Wed Jun 1 22:22:07 2022 -0400
>
> drm/amdgpu/display: Protect some functions with CONFIG_DRM_AMD_DC_DCN
>
> Protect remove_hpo_dp_link_enc_from_ctx() and release_hpo_dp_link_enc()
> with CONFIG_DRM_AMD_DC_DCN as the functions are only called from code
> that is protected by CONFIG_DRM_AMD_DC_DCN. Fixes build fail with
> -Werror=unused-function.
>
> Fixes: 9b0e0d433f74 ("drm/amd/display: Add dependant changes for DCN32/321")
> Reported-by: Stephen Rothwell <sfr@canb.auug.org.au>
> Reviewed-by: Harry Wentland <harry.wentland@amd.com>
> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> Cc: Aurabindo Pillai <aurabindo.pillai@amd.com>
>
I remember your patch was needed but don't see it now. I wonder
if someone removed the reason the guards were needed.
Harry
> Maybe they are no longer required?
>
> Alex
>
>
>>
>> Harry
>>
>>> }
>>> +#endif
>>>
>>> if (del_pipe->stream_res.audio)
>>> update_audio_usage(
>>
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 6/6] Revert "drm/amd/display: Drop unnecessary guard from DC resource"
2022-06-06 18:01 ` Harry Wentland
@ 2022-06-06 18:04 ` Alex Deucher
0 siblings, 0 replies; 17+ messages in thread
From: Alex Deucher @ 2022-06-06 18:04 UTC (permalink / raw)
To: Harry Wentland; +Cc: Alex Deucher, Rodrigo Siqueira, amd-gfx list
On Mon, Jun 6, 2022 at 2:02 PM Harry Wentland <harry.wentland@amd.com> wrote:
>
>
>
> On 2022-06-06 12:17, Alex Deucher wrote:
> > On Mon, Jun 6, 2022 at 10:16 AM Harry Wentland <harry.wentland@amd.com> wrote:
> >>
> >> On 2022-06-03 14:50, Rodrigo Siqueira wrote:
> >>> This reverts commit 78baa3c4dfff4375b109bc5e19663a2f7fad1190.
> >>>
> >>> This commit introduced the below compilation error when using
> >>> allmodconfig:
> >>>
> >>> error: implicit declaration of function ‘remove_hpo_dp_link_enc_from_ctx’; did you mean ‘add_hpo_dp_link_enc_to_ctx’? [-Werror=implicit-function-declaration]
> >>> 2010 | remove_hpo_dp_link_enc_from_ctx(&new_ctx->res_ctx, del_pipe, del_pipe->stream);
> >>> | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> >>> | add_hpo_dp_link_enc_to_ctx
> >>>
> >>> Fixes: 78baa3c4dfff43 ("drm/amd/display: Drop unnecessary guard from DC resource")
> >>> Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
> >>> ---
> >>> drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 2 ++
> >>> 1 file changed, 2 insertions(+)
> >>>
> >>> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
> >>> index 7357efb8b439..9bbdfcd6b3a4 100644
> >>> --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
> >>> +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
> >>> @@ -2002,6 +2002,7 @@ enum dc_status dc_remove_stream_from_ctx(
> >>> if (dc->res_pool->funcs->link_enc_unassign)
> >>> dc->res_pool->funcs->link_enc_unassign(new_ctx, del_pipe->stream);
> >>>
> >>> +#if defined(CONFIG_DRM_AMD_DC_DCN)
> >>> if (is_dp_128b_132b_signal(del_pipe)) {
> >>> update_hpo_dp_stream_engine_usage(
> >>> &new_ctx->res_ctx, dc->res_pool,
> >>> @@ -2009,6 +2010,7 @@ enum dc_status dc_remove_stream_from_ctx(
> >>> false);
> >>> remove_hpo_dp_link_enc_from_ctx(&new_ctx->res_ctx, del_pipe, del_pipe->stream);
> >>
> >> Wouldn't a better solution be to drop the DCN guards around
> >> remove_hpo_dp_link_enc_from_ctx and release_hpo_dp_link_enc?
> >> Not sure why those were guarded in the first place.
> >
> > They were added by me in:
> >
> > commit d8e4fb9112e88d8d87ffbc38fa511e7118042d4f
> > Author: Alex Deucher <alexander.deucher@amd.com>
> > Date: Wed Jun 1 22:22:07 2022 -0400
> >
> > drm/amdgpu/display: Protect some functions with CONFIG_DRM_AMD_DC_DCN
> >
> > Protect remove_hpo_dp_link_enc_from_ctx() and release_hpo_dp_link_enc()
> > with CONFIG_DRM_AMD_DC_DCN as the functions are only called from code
> > that is protected by CONFIG_DRM_AMD_DC_DCN. Fixes build fail with
> > -Werror=unused-function.
> >
> > Fixes: 9b0e0d433f74 ("drm/amd/display: Add dependant changes for DCN32/321")
> > Reported-by: Stephen Rothwell <sfr@canb.auug.org.au>
> > Reviewed-by: Harry Wentland <harry.wentland@amd.com>
> > Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> > Cc: Aurabindo Pillai <aurabindo.pillai@amd.com>
> >
>
> I remember your patch was needed but don't see it now. I wonder
> if someone removed the reason the guards were needed.
It might have just been a temporary bandaid due to further patches
still waiting for CI to complete.
Alex
>
> Harry
>
> > Maybe they are no longer required?
> >
> > Alex
> >
> >
> >>
> >> Harry
> >>
> >>> }
> >>> +#endif
> >>>
> >>> if (del_pipe->stream_res.audio)
> >>> update_audio_usage(
> >>
>
^ permalink raw reply [flat|nested] 17+ messages in thread
end of thread, other threads:[~2022-06-06 18:05 UTC | newest]
Thread overview: 17+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2022-06-03 18:50 [PATCH 0/6] Cleaning up some GCC warnings and other minor issues Rodrigo Siqueira
2022-06-03 18:50 ` [PATCH 1/6] drm/amd/display: Remove duplicated macro Rodrigo Siqueira
2022-06-06 14:04 ` Harry Wentland
2022-06-03 18:50 ` [PATCH 2/6] drm/amd/display: Reduce frame size in the bouding box for DCN20 Rodrigo Siqueira
2022-06-06 14:05 ` Harry Wentland
2022-06-03 18:50 ` [PATCH 3/6] drm/amd/display: Reduce frame size in the bouding box for DCN301 Rodrigo Siqueira
2022-06-06 14:08 ` Harry Wentland
2022-06-03 18:50 ` [PATCH 4/6] drm/amd/display: Reduce frame size in the bouding box for DCN31/316 Rodrigo Siqueira
2022-06-06 14:10 ` Harry Wentland
2022-06-03 18:50 ` [PATCH 5/6] drm/amd/display: Reduce frame size in the bouding box for DCN21 Rodrigo Siqueira
2022-06-06 14:11 ` Harry Wentland
2022-06-03 18:50 ` [PATCH 6/6] Revert "drm/amd/display: Drop unnecessary guard from DC resource" Rodrigo Siqueira
2022-06-06 14:16 ` Harry Wentland
2022-06-06 16:17 ` Alex Deucher
2022-06-06 18:01 ` Harry Wentland
2022-06-06 18:04 ` Alex Deucher
2022-06-03 19:40 ` [PATCH 0/6] Cleaning up some GCC warnings and other minor issues Alex Deucher
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox