* [PATCH v2 1/3] drm/amdgpu: add engine_retains_context to amdgpu_ring_funcs @ 2025-10-30 9:11 Pierre-Eric Pelloux-Prayer 2025-10-30 9:11 ` [PATCH v2 2/3] drm/amdgpu: increment sched score on entity selection Pierre-Eric Pelloux-Prayer 2025-10-31 11:10 ` [PATCH v2 1/3] drm/amdgpu: add engine_retains_context to amdgpu_ring_funcs Tvrtko Ursulin 0 siblings, 2 replies; 4+ messages in thread From: Pierre-Eric Pelloux-Prayer @ 2025-10-30 9:11 UTC (permalink / raw) To: Alex Deucher, Christian König, David Airlie, Simona Vetter Cc: Pierre-Eric Pelloux-Prayer, amd-gfx, dri-devel, linux-kernel If true, the hw engine retains context among dependent jobs, which means load balancing between schedulers cannot be used at the job level. amdgpu_ctx_init_entity uses this information to disable load balancing, but it's best to store it as a property rather than deduce it based on hw_ip. Signed-off-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> --- drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 1 + drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c | 1 + drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c | 1 + drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c | 1 + drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 3 +++ drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c | 2 ++ drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 2 ++ drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 2 ++ drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 2 ++ drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 3 +++ drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c | 1 + drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c | 1 + drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c | 1 + drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c | 1 + drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c | 1 + 15 files changed, 23 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h index 4b46e3c26ff3..a10efac2fc54 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h @@ -211,6 +211,7 @@ struct amdgpu_ring_funcs { bool support_64bit_ptrs; bool no_user_fence; bool secure_submission_supported; + bool engine_retains_context; /** * @extra_bytes: diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c b/drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c index 2e79a3afc774..4a85b5465bb2 100644 --- a/drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c @@ -181,6 +181,7 @@ static const struct amdgpu_ring_funcs uvd_v3_1_ring_funcs = { .align_mask = 0xf, .support_64bit_ptrs = false, .no_user_fence = true, + .engine_retains_context = true, .get_rptr = uvd_v3_1_ring_get_rptr, .get_wptr = uvd_v3_1_ring_get_wptr, .set_wptr = uvd_v3_1_ring_set_wptr, diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c index 4b96fd583772..e7c1d12f0596 100644 --- a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c @@ -775,6 +775,7 @@ static const struct amdgpu_ring_funcs uvd_v4_2_ring_funcs = { .align_mask = 0xf, .support_64bit_ptrs = false, .no_user_fence = true, + .engine_retains_context = true, .get_rptr = uvd_v4_2_ring_get_rptr, .get_wptr = uvd_v4_2_ring_get_wptr, .set_wptr = uvd_v4_2_ring_set_wptr, diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c index 71409ad8b7ed..a62788e4af96 100644 --- a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c @@ -882,6 +882,7 @@ static const struct amdgpu_ring_funcs uvd_v5_0_ring_funcs = { .align_mask = 0xf, .support_64bit_ptrs = false, .no_user_fence = true, + .engine_retains_context = true, .get_rptr = uvd_v5_0_ring_get_rptr, .get_wptr = uvd_v5_0_ring_get_wptr, .set_wptr = uvd_v5_0_ring_set_wptr, diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c index ceb94bbb03a4..0435577b9b3b 100644 --- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c @@ -1552,6 +1552,7 @@ static const struct amdgpu_ring_funcs uvd_v6_0_ring_phys_funcs = { .align_mask = 0xf, .support_64bit_ptrs = false, .no_user_fence = true, + .engine_retains_context = true, .get_rptr = uvd_v6_0_ring_get_rptr, .get_wptr = uvd_v6_0_ring_get_wptr, .set_wptr = uvd_v6_0_ring_set_wptr, @@ -1578,6 +1579,7 @@ static const struct amdgpu_ring_funcs uvd_v6_0_ring_vm_funcs = { .align_mask = 0xf, .support_64bit_ptrs = false, .no_user_fence = true, + .engine_retains_context = true, .get_rptr = uvd_v6_0_ring_get_rptr, .get_wptr = uvd_v6_0_ring_get_wptr, .set_wptr = uvd_v6_0_ring_set_wptr, @@ -1607,6 +1609,7 @@ static const struct amdgpu_ring_funcs uvd_v6_0_enc_ring_vm_funcs = { .nop = HEVC_ENC_CMD_NO_OP, .support_64bit_ptrs = false, .no_user_fence = true, + .engine_retains_context = true, .get_rptr = uvd_v6_0_enc_ring_get_rptr, .get_wptr = uvd_v6_0_enc_ring_get_wptr, .set_wptr = uvd_v6_0_enc_ring_set_wptr, diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c index 1f8866f3f63c..3720d72f2c3e 100644 --- a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c @@ -1539,6 +1539,7 @@ static const struct amdgpu_ring_funcs uvd_v7_0_ring_vm_funcs = { .align_mask = 0xf, .support_64bit_ptrs = false, .no_user_fence = true, + .engine_retains_context = true, .get_rptr = uvd_v7_0_ring_get_rptr, .get_wptr = uvd_v7_0_ring_get_wptr, .set_wptr = uvd_v7_0_ring_set_wptr, @@ -1571,6 +1572,7 @@ static const struct amdgpu_ring_funcs uvd_v7_0_enc_ring_vm_funcs = { .nop = HEVC_ENC_CMD_NO_OP, .support_64bit_ptrs = false, .no_user_fence = true, + .engine_retains_context = true, .get_rptr = uvd_v7_0_enc_ring_get_rptr, .get_wptr = uvd_v7_0_enc_ring_get_wptr, .set_wptr = uvd_v7_0_enc_ring_set_wptr, diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c index a316797875a8..1691d0f955a9 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c @@ -2117,6 +2117,7 @@ static const struct amdgpu_ring_funcs vcn_v1_0_dec_ring_vm_funcs = { .support_64bit_ptrs = false, .no_user_fence = true, .secure_submission_supported = true, + .engine_retains_context = true, .get_rptr = vcn_v1_0_dec_ring_get_rptr, .get_wptr = vcn_v1_0_dec_ring_get_wptr, .set_wptr = vcn_v1_0_dec_ring_set_wptr, @@ -2150,6 +2151,7 @@ static const struct amdgpu_ring_funcs vcn_v1_0_enc_ring_vm_funcs = { .align_mask = 0x3f, .nop = VCN_ENC_CMD_NO_OP, .support_64bit_ptrs = false, + .engine_retains_context = true, .no_user_fence = true, .get_rptr = vcn_v1_0_enc_ring_get_rptr, .get_wptr = vcn_v1_0_enc_ring_get_wptr, diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c index 8897dcc9c1a0..046dd6b216e9 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c @@ -2113,6 +2113,7 @@ static const struct amdgpu_ring_funcs vcn_v2_0_dec_ring_vm_funcs = { .type = AMDGPU_RING_TYPE_VCN_DEC, .align_mask = 0xf, .secure_submission_supported = true, + .engine_retains_context = true, .get_rptr = vcn_v2_0_dec_ring_get_rptr, .get_wptr = vcn_v2_0_dec_ring_get_wptr, .set_wptr = vcn_v2_0_dec_ring_set_wptr, @@ -2144,6 +2145,7 @@ static const struct amdgpu_ring_funcs vcn_v2_0_enc_ring_vm_funcs = { .type = AMDGPU_RING_TYPE_VCN_ENC, .align_mask = 0x3f, .nop = VCN_ENC_CMD_NO_OP, + .engine_retains_context = true, .get_rptr = vcn_v2_0_enc_ring_get_rptr, .get_wptr = vcn_v2_0_enc_ring_get_wptr, .set_wptr = vcn_v2_0_enc_ring_set_wptr, diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c index cebee453871c..063f88da120b 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c @@ -1777,6 +1777,7 @@ static const struct amdgpu_ring_funcs vcn_v2_5_dec_ring_vm_funcs = { .type = AMDGPU_RING_TYPE_VCN_DEC, .align_mask = 0xf, .secure_submission_supported = true, + .engine_retains_context = true, .get_rptr = vcn_v2_5_dec_ring_get_rptr, .get_wptr = vcn_v2_5_dec_ring_get_wptr, .set_wptr = vcn_v2_5_dec_ring_set_wptr, @@ -1877,6 +1878,7 @@ static const struct amdgpu_ring_funcs vcn_v2_5_enc_ring_vm_funcs = { .type = AMDGPU_RING_TYPE_VCN_ENC, .align_mask = 0x3f, .nop = VCN_ENC_CMD_NO_OP, + .engine_retains_context = true, .get_rptr = vcn_v2_5_enc_ring_get_rptr, .get_wptr = vcn_v2_5_enc_ring_get_wptr, .set_wptr = vcn_v2_5_enc_ring_set_wptr, diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c index d9cf8f0feeb3..8dcc07b3f631 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c @@ -1857,6 +1857,7 @@ static const struct amdgpu_ring_funcs vcn_v3_0_dec_sw_ring_vm_funcs = { .align_mask = 0x3f, .nop = VCN_DEC_SW_CMD_NO_OP, .secure_submission_supported = true, + .engine_retains_context = true, .get_rptr = vcn_v3_0_dec_ring_get_rptr, .get_wptr = vcn_v3_0_dec_ring_get_wptr, .set_wptr = vcn_v3_0_dec_ring_set_wptr, @@ -2021,6 +2022,7 @@ static const struct amdgpu_ring_funcs vcn_v3_0_dec_ring_vm_funcs = { .type = AMDGPU_RING_TYPE_VCN_DEC, .align_mask = 0xf, .secure_submission_supported = true, + .engine_retains_context = true, .get_rptr = vcn_v3_0_dec_ring_get_rptr, .get_wptr = vcn_v3_0_dec_ring_get_wptr, .set_wptr = vcn_v3_0_dec_ring_set_wptr, @@ -2122,6 +2124,7 @@ static const struct amdgpu_ring_funcs vcn_v3_0_enc_ring_vm_funcs = { .type = AMDGPU_RING_TYPE_VCN_ENC, .align_mask = 0x3f, .nop = VCN_ENC_CMD_NO_OP, + .engine_retains_context = true, .get_rptr = vcn_v3_0_enc_ring_get_rptr, .get_wptr = vcn_v3_0_enc_ring_get_wptr, .set_wptr = vcn_v3_0_enc_ring_set_wptr, diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c index 3ae666522d57..f1306316dc3c 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c @@ -1977,6 +1977,7 @@ static struct amdgpu_ring_funcs vcn_v4_0_unified_ring_vm_funcs = { .type = AMDGPU_RING_TYPE_VCN_ENC, .align_mask = 0x3f, .nop = VCN_ENC_CMD_NO_OP, + .engine_retains_context = true, .extra_bytes = sizeof(struct amdgpu_vcn_rb_metadata), .get_rptr = vcn_v4_0_unified_ring_get_rptr, .get_wptr = vcn_v4_0_unified_ring_get_wptr, diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c index eacf4e93ba2f..5a935c07352a 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c @@ -1628,6 +1628,7 @@ static const struct amdgpu_ring_funcs vcn_v4_0_3_unified_ring_vm_funcs = { .type = AMDGPU_RING_TYPE_VCN_ENC, .align_mask = 0x3f, .nop = VCN_ENC_CMD_NO_OP, + .engine_retains_context = true, .get_rptr = vcn_v4_0_3_unified_ring_get_rptr, .get_wptr = vcn_v4_0_3_unified_ring_get_wptr, .set_wptr = vcn_v4_0_3_unified_ring_set_wptr, diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c index b107ee80e472..1a485f5825dd 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c @@ -1481,6 +1481,7 @@ static struct amdgpu_ring_funcs vcn_v4_0_5_unified_ring_vm_funcs = { .type = AMDGPU_RING_TYPE_VCN_ENC, .align_mask = 0x3f, .nop = VCN_ENC_CMD_NO_OP, + .engine_retains_context = true, .get_rptr = vcn_v4_0_5_unified_ring_get_rptr, .get_wptr = vcn_v4_0_5_unified_ring_get_wptr, .set_wptr = vcn_v4_0_5_unified_ring_set_wptr, diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c index 0202df5db1e1..2d8214f591f1 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c @@ -1203,6 +1203,7 @@ static const struct amdgpu_ring_funcs vcn_v5_0_0_unified_ring_vm_funcs = { .type = AMDGPU_RING_TYPE_VCN_ENC, .align_mask = 0x3f, .nop = VCN_ENC_CMD_NO_OP, + .engine_retains_context = true, .get_rptr = vcn_v5_0_0_unified_ring_get_rptr, .get_wptr = vcn_v5_0_0_unified_ring_get_wptr, .set_wptr = vcn_v5_0_0_unified_ring_set_wptr, diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c index 714350cabf2f..bd3a04f1414d 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c @@ -1328,6 +1328,7 @@ static const struct amdgpu_ring_funcs vcn_v5_0_1_unified_ring_vm_funcs = { .type = AMDGPU_RING_TYPE_VCN_ENC, .align_mask = 0x3f, .nop = VCN_ENC_CMD_NO_OP, + .engine_retains_context = true, .get_rptr = vcn_v5_0_1_unified_ring_get_rptr, .get_wptr = vcn_v5_0_1_unified_ring_get_wptr, .set_wptr = vcn_v5_0_1_unified_ring_set_wptr, -- 2.43.0 ^ permalink raw reply related [flat|nested] 4+ messages in thread
* [PATCH v2 2/3] drm/amdgpu: increment sched score on entity selection 2025-10-30 9:11 [PATCH v2 1/3] drm/amdgpu: add engine_retains_context to amdgpu_ring_funcs Pierre-Eric Pelloux-Prayer @ 2025-10-30 9:11 ` Pierre-Eric Pelloux-Prayer 2025-10-31 11:34 ` Tvrtko Ursulin 2025-10-31 11:10 ` [PATCH v2 1/3] drm/amdgpu: add engine_retains_context to amdgpu_ring_funcs Tvrtko Ursulin 1 sibling, 1 reply; 4+ messages in thread From: Pierre-Eric Pelloux-Prayer @ 2025-10-30 9:11 UTC (permalink / raw) To: Alex Deucher, Christian König, David Airlie, Simona Vetter Cc: Pierre-Eric Pelloux-Prayer, amd-gfx, dri-devel, linux-kernel For hw engines that can't load balance jobs, entities are "statically" load balanced: on their first submit, they select the best scheduler based on its score. The score is made up of 2 parts: * the job queue depth (how much jobs are executing/waiting) * the number of entities assigned The second part is only relevant for the static load balance: it's a way to consider how many entities are attached to this scheduler, knowing that if they ever submit jobs they will go to this one. For rings that can load balance jobs freely, idle entities aren't a concern and shouldn't impact the scheduler's decisions. Signed-off-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> --- drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c | 23 +++++++++++++++++------ drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h | 1 + 2 files changed, 18 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c index f5d5c45ddc0d..953c81c928c1 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c @@ -209,6 +209,7 @@ static int amdgpu_ctx_init_entity(struct amdgpu_ctx *ctx, u32 hw_ip, struct amdgpu_ctx_entity *entity; enum drm_sched_priority drm_prio; unsigned int hw_prio, num_scheds; + struct amdgpu_ring *aring; int32_t ctx_prio; int r; @@ -236,14 +237,16 @@ static int amdgpu_ctx_init_entity(struct amdgpu_ctx *ctx, u32 hw_ip, r = amdgpu_xcp_select_scheds(adev, hw_ip, hw_prio, fpriv, &num_scheds, &scheds); if (r) - goto cleanup_entity; + goto error_free_entity; } - /* disable load balance if the hw engine retains context among dependent jobs */ - if (hw_ip == AMDGPU_HW_IP_VCN_ENC || - hw_ip == AMDGPU_HW_IP_VCN_DEC || - hw_ip == AMDGPU_HW_IP_UVD_ENC || - hw_ip == AMDGPU_HW_IP_UVD) { + sched = scheds[0]; + aring = container_of(sched, struct amdgpu_ring, sched); + + if (aring->funcs->engine_retains_context) { + /* Disable load balancing between multiple schedulers if the hw + * engine retains context among dependent jobs. + */ sched = drm_sched_pick_best(scheds, num_scheds); scheds = &sched; num_scheds = 1; @@ -258,6 +261,11 @@ static int amdgpu_ctx_init_entity(struct amdgpu_ctx *ctx, u32 hw_ip, if (cmpxchg(&ctx->entities[hw_ip][ring], NULL, entity)) goto cleanup_entity; + if (aring->funcs->engine_retains_context) { + entity->sched_score = sched->score; + atomic_inc(entity->sched_score); + } + return 0; cleanup_entity: @@ -514,6 +522,9 @@ static void amdgpu_ctx_do_release(struct kref *ref) if (!ctx->entities[i][j]) continue; + if (ctx->entities[i][j]->sched_score) + atomic_dec(ctx->entities[i][j]->sched_score); + drm_sched_entity_destroy(&ctx->entities[i][j]->entity); } } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h index 090dfe86f75b..f7b44f96f374 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h @@ -39,6 +39,7 @@ struct amdgpu_ctx_entity { uint32_t hw_ip; uint64_t sequence; struct drm_sched_entity entity; + atomic_t *sched_score; struct dma_fence *fences[]; }; -- 2.43.0 ^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH v2 2/3] drm/amdgpu: increment sched score on entity selection 2025-10-30 9:11 ` [PATCH v2 2/3] drm/amdgpu: increment sched score on entity selection Pierre-Eric Pelloux-Prayer @ 2025-10-31 11:34 ` Tvrtko Ursulin 0 siblings, 0 replies; 4+ messages in thread From: Tvrtko Ursulin @ 2025-10-31 11:34 UTC (permalink / raw) To: Pierre-Eric Pelloux-Prayer, Alex Deucher, Christian König, David Airlie, Simona Vetter Cc: amd-gfx, dri-devel, linux-kernel On 30/10/2025 09:11, Pierre-Eric Pelloux-Prayer wrote: > For hw engines that can't load balance jobs, entities are > "statically" load balanced: on their first submit, they select > the best scheduler based on its score. > The score is made up of 2 parts: > * the job queue depth (how much jobs are executing/waiting) > * the number of entities assigned > > The second part is only relevant for the static load balance: > it's a way to consider how many entities are attached to this > scheduler, knowing that if they ever submit jobs they will go > to this one. > > For rings that can load balance jobs freely, idle entities > aren't a concern and shouldn't impact the scheduler's decisions. > > Signed-off-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> > --- > drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c | 23 +++++++++++++++++------ > drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h | 1 + > 2 files changed, 18 insertions(+), 6 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c > index f5d5c45ddc0d..953c81c928c1 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c > @@ -209,6 +209,7 @@ static int amdgpu_ctx_init_entity(struct amdgpu_ctx *ctx, u32 hw_ip, > struct amdgpu_ctx_entity *entity; > enum drm_sched_priority drm_prio; > unsigned int hw_prio, num_scheds; > + struct amdgpu_ring *aring; > int32_t ctx_prio; > int r; > > @@ -236,14 +237,16 @@ static int amdgpu_ctx_init_entity(struct amdgpu_ctx *ctx, u32 hw_ip, > r = amdgpu_xcp_select_scheds(adev, hw_ip, hw_prio, fpriv, > &num_scheds, &scheds); > if (r) > - goto cleanup_entity; > + goto error_free_entity; It would be best to split this out as a standalone patch. It is not a bug due kzalloc and DRM scheduler not doing anything with it in drm_sched_fini but still it would be best practice. > } > > - /* disable load balance if the hw engine retains context among dependent jobs */ > - if (hw_ip == AMDGPU_HW_IP_VCN_ENC || > - hw_ip == AMDGPU_HW_IP_VCN_DEC || > - hw_ip == AMDGPU_HW_IP_UVD_ENC || > - hw_ip == AMDGPU_HW_IP_UVD) { > + sched = scheds[0]; > + aring = container_of(sched, struct amdgpu_ring, sched); > + > + if (aring->funcs->engine_retains_context) { > + /* Disable load balancing between multiple schedulers if the hw > + * engine retains context among dependent jobs. > + */ > sched = drm_sched_pick_best(scheds, num_scheds); > scheds = &sched; > num_scheds = 1; > @@ -258,6 +261,11 @@ static int amdgpu_ctx_init_entity(struct amdgpu_ctx *ctx, u32 hw_ip, > if (cmpxchg(&ctx->entities[hw_ip][ring], NULL, entity)) > goto cleanup_entity; > > + if (aring->funcs->engine_retains_context) { > + entity->sched_score = sched->score; Here is would always be sched->score == aring->sched_score, right? If so it would probably be good to either add that assert, or even to just fetch it from there. Otherwise it can look potentially concerning to be fishing out the pointer from scheduler internals. The rest looks good to me. Regards, Tvrtko > + atomic_inc(entity->sched_score); > + } > + > return 0; > > cleanup_entity: > @@ -514,6 +522,9 @@ static void amdgpu_ctx_do_release(struct kref *ref) > if (!ctx->entities[i][j]) > continue; > > + if (ctx->entities[i][j]->sched_score) > + atomic_dec(ctx->entities[i][j]->sched_score); > + > drm_sched_entity_destroy(&ctx->entities[i][j]->entity); > } > } > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h > index 090dfe86f75b..f7b44f96f374 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h > @@ -39,6 +39,7 @@ struct amdgpu_ctx_entity { > uint32_t hw_ip; > uint64_t sequence; > struct drm_sched_entity entity; > + atomic_t *sched_score; > struct dma_fence *fences[]; > }; > ^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH v2 1/3] drm/amdgpu: add engine_retains_context to amdgpu_ring_funcs 2025-10-30 9:11 [PATCH v2 1/3] drm/amdgpu: add engine_retains_context to amdgpu_ring_funcs Pierre-Eric Pelloux-Prayer 2025-10-30 9:11 ` [PATCH v2 2/3] drm/amdgpu: increment sched score on entity selection Pierre-Eric Pelloux-Prayer @ 2025-10-31 11:10 ` Tvrtko Ursulin 1 sibling, 0 replies; 4+ messages in thread From: Tvrtko Ursulin @ 2025-10-31 11:10 UTC (permalink / raw) To: Pierre-Eric Pelloux-Prayer, Alex Deucher, Christian König, David Airlie, Simona Vetter Cc: amd-gfx, dri-devel, linux-kernel On 30/10/2025 09:11, Pierre-Eric Pelloux-Prayer wrote: > If true, the hw engine retains context among dependent jobs, which means > load balancing between schedulers cannot be used at the job level. > > amdgpu_ctx_init_entity uses this information to disable load balancing, > but it's best to store it as a property rather than deduce it based on > hw_ip. On a tangent, this patch reminded me on a series I had to remove some holes from structs. For the ring specifically: commit e89d67894fe4824d0163c8831b9bcdaabb4ae3a2 Author: Tvrtko Ursulin <tvrtko.ursulin@igalia.com> Date: Fri Feb 21 13:37:25 2025 +0000 struct amdgpu_ring { /* size: 792, cachelines: 13, members: 62 */ /* sum members: 746, holes: 13, sum holes: 46 */ /* last cacheline: 24 bytes */ /* size: 744, cachelines: 12, members: 62 */ /* sum members: 738, holes: 2, sum holes: 6 */ /* last cacheline: 40 bytes */ I tried to keep and/or improve logical grouping of fields while re-arranging to avoid holes. Only one cacheline saved is not much so not sure. Not even sure if I ever sent it. Any interest to clean it up and send? Regards, Tvrtko > Signed-off-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> > --- > drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 1 + > drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c | 1 + > drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c | 1 + > drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c | 1 + > drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 3 +++ > drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c | 2 ++ > drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 2 ++ > drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 2 ++ > drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 2 ++ > drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 3 +++ > drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c | 1 + > drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c | 1 + > drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c | 1 + > drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c | 1 + > drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c | 1 + > 15 files changed, 23 insertions(+) > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h > index 4b46e3c26ff3..a10efac2fc54 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h > @@ -211,6 +211,7 @@ struct amdgpu_ring_funcs { > bool support_64bit_ptrs; > bool no_user_fence; > bool secure_submission_supported; > + bool engine_retains_context; > > /** > * @extra_bytes: > diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c b/drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c > index 2e79a3afc774..4a85b5465bb2 100644 > --- a/drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c > +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c > @@ -181,6 +181,7 @@ static const struct amdgpu_ring_funcs uvd_v3_1_ring_funcs = { > .align_mask = 0xf, > .support_64bit_ptrs = false, > .no_user_fence = true, > + .engine_retains_context = true, > .get_rptr = uvd_v3_1_ring_get_rptr, > .get_wptr = uvd_v3_1_ring_get_wptr, > .set_wptr = uvd_v3_1_ring_set_wptr, > diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c > index 4b96fd583772..e7c1d12f0596 100644 > --- a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c > +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c > @@ -775,6 +775,7 @@ static const struct amdgpu_ring_funcs uvd_v4_2_ring_funcs = { > .align_mask = 0xf, > .support_64bit_ptrs = false, > .no_user_fence = true, > + .engine_retains_context = true, > .get_rptr = uvd_v4_2_ring_get_rptr, > .get_wptr = uvd_v4_2_ring_get_wptr, > .set_wptr = uvd_v4_2_ring_set_wptr, > diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c > index 71409ad8b7ed..a62788e4af96 100644 > --- a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c > @@ -882,6 +882,7 @@ static const struct amdgpu_ring_funcs uvd_v5_0_ring_funcs = { > .align_mask = 0xf, > .support_64bit_ptrs = false, > .no_user_fence = true, > + .engine_retains_context = true, > .get_rptr = uvd_v5_0_ring_get_rptr, > .get_wptr = uvd_v5_0_ring_get_wptr, > .set_wptr = uvd_v5_0_ring_set_wptr, > diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c > index ceb94bbb03a4..0435577b9b3b 100644 > --- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c > @@ -1552,6 +1552,7 @@ static const struct amdgpu_ring_funcs uvd_v6_0_ring_phys_funcs = { > .align_mask = 0xf, > .support_64bit_ptrs = false, > .no_user_fence = true, > + .engine_retains_context = true, > .get_rptr = uvd_v6_0_ring_get_rptr, > .get_wptr = uvd_v6_0_ring_get_wptr, > .set_wptr = uvd_v6_0_ring_set_wptr, > @@ -1578,6 +1579,7 @@ static const struct amdgpu_ring_funcs uvd_v6_0_ring_vm_funcs = { > .align_mask = 0xf, > .support_64bit_ptrs = false, > .no_user_fence = true, > + .engine_retains_context = true, > .get_rptr = uvd_v6_0_ring_get_rptr, > .get_wptr = uvd_v6_0_ring_get_wptr, > .set_wptr = uvd_v6_0_ring_set_wptr, > @@ -1607,6 +1609,7 @@ static const struct amdgpu_ring_funcs uvd_v6_0_enc_ring_vm_funcs = { > .nop = HEVC_ENC_CMD_NO_OP, > .support_64bit_ptrs = false, > .no_user_fence = true, > + .engine_retains_context = true, > .get_rptr = uvd_v6_0_enc_ring_get_rptr, > .get_wptr = uvd_v6_0_enc_ring_get_wptr, > .set_wptr = uvd_v6_0_enc_ring_set_wptr, > diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c > index 1f8866f3f63c..3720d72f2c3e 100644 > --- a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c > @@ -1539,6 +1539,7 @@ static const struct amdgpu_ring_funcs uvd_v7_0_ring_vm_funcs = { > .align_mask = 0xf, > .support_64bit_ptrs = false, > .no_user_fence = true, > + .engine_retains_context = true, > .get_rptr = uvd_v7_0_ring_get_rptr, > .get_wptr = uvd_v7_0_ring_get_wptr, > .set_wptr = uvd_v7_0_ring_set_wptr, > @@ -1571,6 +1572,7 @@ static const struct amdgpu_ring_funcs uvd_v7_0_enc_ring_vm_funcs = { > .nop = HEVC_ENC_CMD_NO_OP, > .support_64bit_ptrs = false, > .no_user_fence = true, > + .engine_retains_context = true, > .get_rptr = uvd_v7_0_enc_ring_get_rptr, > .get_wptr = uvd_v7_0_enc_ring_get_wptr, > .set_wptr = uvd_v7_0_enc_ring_set_wptr, > diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c > index a316797875a8..1691d0f955a9 100644 > --- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c > @@ -2117,6 +2117,7 @@ static const struct amdgpu_ring_funcs vcn_v1_0_dec_ring_vm_funcs = { > .support_64bit_ptrs = false, > .no_user_fence = true, > .secure_submission_supported = true, > + .engine_retains_context = true, > .get_rptr = vcn_v1_0_dec_ring_get_rptr, > .get_wptr = vcn_v1_0_dec_ring_get_wptr, > .set_wptr = vcn_v1_0_dec_ring_set_wptr, > @@ -2150,6 +2151,7 @@ static const struct amdgpu_ring_funcs vcn_v1_0_enc_ring_vm_funcs = { > .align_mask = 0x3f, > .nop = VCN_ENC_CMD_NO_OP, > .support_64bit_ptrs = false, > + .engine_retains_context = true, > .no_user_fence = true, > .get_rptr = vcn_v1_0_enc_ring_get_rptr, > .get_wptr = vcn_v1_0_enc_ring_get_wptr, > diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c > index 8897dcc9c1a0..046dd6b216e9 100644 > --- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c > @@ -2113,6 +2113,7 @@ static const struct amdgpu_ring_funcs vcn_v2_0_dec_ring_vm_funcs = { > .type = AMDGPU_RING_TYPE_VCN_DEC, > .align_mask = 0xf, > .secure_submission_supported = true, > + .engine_retains_context = true, > .get_rptr = vcn_v2_0_dec_ring_get_rptr, > .get_wptr = vcn_v2_0_dec_ring_get_wptr, > .set_wptr = vcn_v2_0_dec_ring_set_wptr, > @@ -2144,6 +2145,7 @@ static const struct amdgpu_ring_funcs vcn_v2_0_enc_ring_vm_funcs = { > .type = AMDGPU_RING_TYPE_VCN_ENC, > .align_mask = 0x3f, > .nop = VCN_ENC_CMD_NO_OP, > + .engine_retains_context = true, > .get_rptr = vcn_v2_0_enc_ring_get_rptr, > .get_wptr = vcn_v2_0_enc_ring_get_wptr, > .set_wptr = vcn_v2_0_enc_ring_set_wptr, > diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c > index cebee453871c..063f88da120b 100644 > --- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c > +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c > @@ -1777,6 +1777,7 @@ static const struct amdgpu_ring_funcs vcn_v2_5_dec_ring_vm_funcs = { > .type = AMDGPU_RING_TYPE_VCN_DEC, > .align_mask = 0xf, > .secure_submission_supported = true, > + .engine_retains_context = true, > .get_rptr = vcn_v2_5_dec_ring_get_rptr, > .get_wptr = vcn_v2_5_dec_ring_get_wptr, > .set_wptr = vcn_v2_5_dec_ring_set_wptr, > @@ -1877,6 +1878,7 @@ static const struct amdgpu_ring_funcs vcn_v2_5_enc_ring_vm_funcs = { > .type = AMDGPU_RING_TYPE_VCN_ENC, > .align_mask = 0x3f, > .nop = VCN_ENC_CMD_NO_OP, > + .engine_retains_context = true, > .get_rptr = vcn_v2_5_enc_ring_get_rptr, > .get_wptr = vcn_v2_5_enc_ring_get_wptr, > .set_wptr = vcn_v2_5_enc_ring_set_wptr, > diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c > index d9cf8f0feeb3..8dcc07b3f631 100644 > --- a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c > @@ -1857,6 +1857,7 @@ static const struct amdgpu_ring_funcs vcn_v3_0_dec_sw_ring_vm_funcs = { > .align_mask = 0x3f, > .nop = VCN_DEC_SW_CMD_NO_OP, > .secure_submission_supported = true, > + .engine_retains_context = true, > .get_rptr = vcn_v3_0_dec_ring_get_rptr, > .get_wptr = vcn_v3_0_dec_ring_get_wptr, > .set_wptr = vcn_v3_0_dec_ring_set_wptr, > @@ -2021,6 +2022,7 @@ static const struct amdgpu_ring_funcs vcn_v3_0_dec_ring_vm_funcs = { > .type = AMDGPU_RING_TYPE_VCN_DEC, > .align_mask = 0xf, > .secure_submission_supported = true, > + .engine_retains_context = true, > .get_rptr = vcn_v3_0_dec_ring_get_rptr, > .get_wptr = vcn_v3_0_dec_ring_get_wptr, > .set_wptr = vcn_v3_0_dec_ring_set_wptr, > @@ -2122,6 +2124,7 @@ static const struct amdgpu_ring_funcs vcn_v3_0_enc_ring_vm_funcs = { > .type = AMDGPU_RING_TYPE_VCN_ENC, > .align_mask = 0x3f, > .nop = VCN_ENC_CMD_NO_OP, > + .engine_retains_context = true, > .get_rptr = vcn_v3_0_enc_ring_get_rptr, > .get_wptr = vcn_v3_0_enc_ring_get_wptr, > .set_wptr = vcn_v3_0_enc_ring_set_wptr, > diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c > index 3ae666522d57..f1306316dc3c 100644 > --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c > @@ -1977,6 +1977,7 @@ static struct amdgpu_ring_funcs vcn_v4_0_unified_ring_vm_funcs = { > .type = AMDGPU_RING_TYPE_VCN_ENC, > .align_mask = 0x3f, > .nop = VCN_ENC_CMD_NO_OP, > + .engine_retains_context = true, > .extra_bytes = sizeof(struct amdgpu_vcn_rb_metadata), > .get_rptr = vcn_v4_0_unified_ring_get_rptr, > .get_wptr = vcn_v4_0_unified_ring_get_wptr, > diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c > index eacf4e93ba2f..5a935c07352a 100644 > --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c > +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c > @@ -1628,6 +1628,7 @@ static const struct amdgpu_ring_funcs vcn_v4_0_3_unified_ring_vm_funcs = { > .type = AMDGPU_RING_TYPE_VCN_ENC, > .align_mask = 0x3f, > .nop = VCN_ENC_CMD_NO_OP, > + .engine_retains_context = true, > .get_rptr = vcn_v4_0_3_unified_ring_get_rptr, > .get_wptr = vcn_v4_0_3_unified_ring_get_wptr, > .set_wptr = vcn_v4_0_3_unified_ring_set_wptr, > diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c > index b107ee80e472..1a485f5825dd 100644 > --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c > +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c > @@ -1481,6 +1481,7 @@ static struct amdgpu_ring_funcs vcn_v4_0_5_unified_ring_vm_funcs = { > .type = AMDGPU_RING_TYPE_VCN_ENC, > .align_mask = 0x3f, > .nop = VCN_ENC_CMD_NO_OP, > + .engine_retains_context = true, > .get_rptr = vcn_v4_0_5_unified_ring_get_rptr, > .get_wptr = vcn_v4_0_5_unified_ring_get_wptr, > .set_wptr = vcn_v4_0_5_unified_ring_set_wptr, > diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c > index 0202df5db1e1..2d8214f591f1 100644 > --- a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c > @@ -1203,6 +1203,7 @@ static const struct amdgpu_ring_funcs vcn_v5_0_0_unified_ring_vm_funcs = { > .type = AMDGPU_RING_TYPE_VCN_ENC, > .align_mask = 0x3f, > .nop = VCN_ENC_CMD_NO_OP, > + .engine_retains_context = true, > .get_rptr = vcn_v5_0_0_unified_ring_get_rptr, > .get_wptr = vcn_v5_0_0_unified_ring_get_wptr, > .set_wptr = vcn_v5_0_0_unified_ring_set_wptr, > diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c > index 714350cabf2f..bd3a04f1414d 100644 > --- a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c > +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c > @@ -1328,6 +1328,7 @@ static const struct amdgpu_ring_funcs vcn_v5_0_1_unified_ring_vm_funcs = { > .type = AMDGPU_RING_TYPE_VCN_ENC, > .align_mask = 0x3f, > .nop = VCN_ENC_CMD_NO_OP, > + .engine_retains_context = true, > .get_rptr = vcn_v5_0_1_unified_ring_get_rptr, > .get_wptr = vcn_v5_0_1_unified_ring_get_wptr, > .set_wptr = vcn_v5_0_1_unified_ring_set_wptr, ^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2025-10-31 11:34 UTC | newest] Thread overview: 4+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2025-10-30 9:11 [PATCH v2 1/3] drm/amdgpu: add engine_retains_context to amdgpu_ring_funcs Pierre-Eric Pelloux-Prayer 2025-10-30 9:11 ` [PATCH v2 2/3] drm/amdgpu: increment sched score on entity selection Pierre-Eric Pelloux-Prayer 2025-10-31 11:34 ` Tvrtko Ursulin 2025-10-31 11:10 ` [PATCH v2 1/3] drm/amdgpu: add engine_retains_context to amdgpu_ring_funcs Tvrtko Ursulin
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