AMD-GFX Archive on lore.kernel.org
 help / color / mirror / Atom feed
* [PATCH] drm/amd/display: Update dmub code
@ 2020-11-13 20:27 Bhawanpreet Lakha
  2020-11-13 21:55 ` Kazlauskas, Nicholas
  0 siblings, 1 reply; 2+ messages in thread
From: Bhawanpreet Lakha @ 2020-11-13 20:27 UTC (permalink / raw)
  To: nicholas.kazlauskas, alexander.deucher; +Cc: Bhawanpreet Lakha, amd-gfx

There is a delta in the dmub code
- add boot options
- add boot status
- remove unused auto_load_is_done func pointer

Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
---
 drivers/gpu/drm/amd/display/dmub/dmub_srv.h   | 20 +++++++++++++-
 .../gpu/drm/amd/display/dmub/inc/dmub_cmd.h   |  3 ++-
 .../gpu/drm/amd/display/dmub/src/dmub_dcn20.c | 23 ++++++++++++++++
 .../gpu/drm/amd/display/dmub/src/dmub_dcn20.h |  6 +++++
 .../gpu/drm/amd/display/dmub/src/dmub_dcn21.c |  5 ----
 .../gpu/drm/amd/display/dmub/src/dmub_dcn21.h |  2 --
 .../gpu/drm/amd/display/dmub/src/dmub_dcn30.c |  5 ----
 .../gpu/drm/amd/display/dmub/src/dmub_dcn30.h |  1 -
 .../gpu/drm/amd/display/dmub/src/dmub_srv.c   | 26 ++++++++++++++-----
 9 files changed, 70 insertions(+), 21 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dmub/dmub_srv.h b/drivers/gpu/drm/amd/display/dmub/dmub_srv.h
index ac41ae2d261b..b82a46890846 100644
--- a/drivers/gpu/drm/amd/display/dmub/dmub_srv.h
+++ b/drivers/gpu/drm/amd/display/dmub/dmub_srv.h
@@ -265,8 +265,12 @@ struct dmub_srv_hw_funcs {
 	bool (*is_hw_init)(struct dmub_srv *dmub);
 
 	bool (*is_phy_init)(struct dmub_srv *dmub);
+	void (*enable_dmub_boot_options)(struct dmub_srv *dmub);
+
+	void (*skip_dmub_panel_power_sequence)(struct dmub_srv *dmub, bool skip);
+
+	union dmub_fw_boot_status (*get_fw_status)(struct dmub_srv *dmub);
 
-	bool (*is_auto_load_done)(struct dmub_srv *dmub);
 
 	void (*set_gpint)(struct dmub_srv *dmub,
 			  union dmub_gpint_data_register reg);
@@ -309,6 +313,7 @@ struct dmub_srv_hw_params {
 	uint64_t fb_offset;
 	uint32_t psp_version;
 	bool load_inst_const;
+	bool skip_panel_power_sequence;
 };
 
 /**
@@ -590,6 +595,19 @@ enum dmub_status dmub_srv_get_gpint_response(struct dmub_srv *dmub,
  */
 void dmub_flush_buffer_mem(const struct dmub_fb *fb);
 
+/**
+ * dmub_srv_get_fw_boot_status() - Returns the DMUB boot status bits.
+ *
+ * @dmub: the dmub service
+ * @status: out pointer for firmware status
+ *
+ * Return:
+ *   DMUB_STATUS_OK - success
+ *   DMUB_STATUS_INVALID - unspecified error, unsupported
+ */
+enum dmub_status dmub_srv_get_fw_boot_status(struct dmub_srv *dmub,
+					     union dmub_fw_boot_status *status);
+
 #if defined(__cplusplus)
 }
 #endif
diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
index b0d1347d13f0..9fd24f93a216 100644
--- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
+++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
@@ -191,7 +191,8 @@ union dmub_fw_boot_options {
 		uint32_t optimized_init : 1;
 		uint32_t skip_phy_access : 1;
 		uint32_t disable_clk_gate: 1;
-		uint32_t reserved : 27;
+		uint32_t skip_phy_init_panel_sequence: 1;
+		uint32_t reserved : 26;
 	} bits;
 	uint32_t all;
 };
diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c
index 2c4a2fe9311d..cafba1d23c6a 100644
--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c
+++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c
@@ -312,3 +312,26 @@ uint32_t dmub_dcn20_get_gpint_response(struct dmub_srv *dmub)
 {
 	return REG_READ(DMCUB_SCRATCH7);
 }
+
+union dmub_fw_boot_status dmub_dcn20_get_fw_boot_status(struct dmub_srv *dmub)
+{
+	union dmub_fw_boot_status status;
+
+	status.all = REG_READ(DMCUB_SCRATCH0);
+	return status;
+}
+
+void dmub_dcn20_enable_dmub_boot_options(struct dmub_srv *dmub)
+{
+	union dmub_fw_boot_options boot_options = {0};
+
+	REG_WRITE(DMCUB_SCRATCH14, boot_options.all);
+}
+
+void dmub_dcn20_skip_dmub_panel_power_sequence(struct dmub_srv *dmub, bool skip)
+{
+	union dmub_fw_boot_options boot_options;
+	boot_options.all = REG_READ(DMCUB_SCRATCH14);
+	boot_options.bits.skip_phy_init_panel_sequence = skip;
+	REG_WRITE(DMCUB_SCRATCH14, boot_options.all);
+}
diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h
index a316f260f6ac..d438f365cbb0 100644
--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h
+++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h
@@ -192,4 +192,10 @@ bool dmub_dcn20_is_gpint_acked(struct dmub_srv *dmub,
 
 uint32_t dmub_dcn20_get_gpint_response(struct dmub_srv *dmub);
 
+void dmub_dcn20_enable_dmub_boot_options(struct dmub_srv *dmub);
+
+void dmub_dcn20_skip_dmub_panel_power_sequence(struct dmub_srv *dmub, bool skip);
+
+union dmub_fw_boot_status dmub_dcn20_get_fw_boot_status(struct dmub_srv *dmub);
+
 #endif /* _DMUB_DCN20_H_ */
diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn21.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn21.c
index e8f488232e34..1cf67b3e4771 100644
--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn21.c
+++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn21.c
@@ -53,11 +53,6 @@ const struct dmub_srv_common_regs dmub_srv_dcn21_regs = {
 
 /* Shared functions. */
 
-bool dmub_dcn21_is_auto_load_done(struct dmub_srv *dmub)
-{
-	return (REG_READ(DMCUB_SCRATCH0) == 3);
-}
-
 bool dmub_dcn21_is_phy_init(struct dmub_srv *dmub)
 {
 	return REG_READ(DMCUB_SCRATCH10) == 0;
diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn21.h b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn21.h
index 2bbea237137b..6fd5b0cd4ef3 100644
--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn21.h
+++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn21.h
@@ -34,8 +34,6 @@ extern const struct dmub_srv_common_regs dmub_srv_dcn21_regs;
 
 /* Hardware functions. */
 
-bool dmub_dcn21_is_auto_load_done(struct dmub_srv *dmub);
-
 bool dmub_dcn21_is_phy_init(struct dmub_srv *dmub);
 
 #endif /* _DMUB_DCN21_H_ */
diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn30.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn30.c
index 215178b8d415..f00df02ded81 100644
--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn30.c
+++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn30.c
@@ -188,8 +188,3 @@ void dmub_dcn30_setup_windows(struct dmub_srv *dmub,
 		  DMCUB_REGION3_CW6_TOP_ADDRESS, cw6->region.top,
 		  DMCUB_REGION3_CW6_ENABLE, 1);
 }
-
-bool dmub_dcn30_is_auto_load_done(struct dmub_srv *dmub)
-{
-	return (REG_READ(DMCUB_SCRATCH0) > 0);
-}
diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn30.h b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn30.h
index 4d8f52b8f12c..9a3afffd9b0f 100644
--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn30.h
+++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn30.h
@@ -45,6 +45,5 @@ void dmub_dcn30_setup_windows(struct dmub_srv *dmub,
 			      const struct dmub_window *cw5,
 			      const struct dmub_window *cw6);
 
-bool dmub_dcn30_is_auto_load_done(struct dmub_srv *dmub);
 
 #endif /* _DMUB_DCN30_H_ */
diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
index d11b96d132ad..ba8494cf005f 100644
--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
+++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
@@ -153,17 +153,18 @@ static bool dmub_srv_hw_setup(struct dmub_srv *dmub, enum dmub_asic asic)
 		funcs->set_gpint = dmub_dcn20_set_gpint;
 		funcs->is_gpint_acked = dmub_dcn20_is_gpint_acked;
 		funcs->get_gpint_response = dmub_dcn20_get_gpint_response;
+		funcs->get_fw_status = dmub_dcn20_get_fw_boot_status;
+		funcs->enable_dmub_boot_options = dmub_dcn20_enable_dmub_boot_options;
+		funcs->skip_dmub_panel_power_sequence = dmub_dcn20_skip_dmub_panel_power_sequence;
 
 		if (asic == DMUB_ASIC_DCN21) {
 			dmub->regs = &dmub_srv_dcn21_regs;
 
-			funcs->is_auto_load_done = dmub_dcn21_is_auto_load_done;
 			funcs->is_phy_init = dmub_dcn21_is_phy_init;
 		}
 		if (asic == DMUB_ASIC_DCN30) {
 			dmub->regs = &dmub_srv_dcn30_regs;
 
-			funcs->is_auto_load_done = dmub_dcn30_is_auto_load_done;
 			funcs->backdoor_load = dmub_dcn30_backdoor_load;
 			funcs->setup_windows = dmub_dcn30_setup_windows;
 		}
@@ -535,11 +536,10 @@ enum dmub_status dmub_srv_wait_for_auto_load(struct dmub_srv *dmub,
 	if (!dmub->hw_init)
 		return DMUB_STATUS_INVALID;
 
-	if (!dmub->hw_funcs.is_auto_load_done)
-		return DMUB_STATUS_OK;
-
 	for (i = 0; i <= timeout_us; i += 100) {
-		if (dmub->hw_funcs.is_auto_load_done(dmub))
+		union dmub_fw_boot_status status = dmub->hw_funcs.get_fw_status(dmub);
+
+		if (status.bits.dal_fw && status.bits.mailbox_rdy)
 			return DMUB_STATUS_OK;
 
 		udelay(100);
@@ -634,3 +634,17 @@ enum dmub_status dmub_srv_get_gpint_response(struct dmub_srv *dmub,
 
 	return DMUB_STATUS_OK;
 }
+
+enum dmub_status dmub_srv_get_fw_boot_status(struct dmub_srv *dmub,
+					     union dmub_fw_boot_status *status)
+{
+	status->all = 0;
+
+	if (!dmub->sw_init)
+		return DMUB_STATUS_INVALID;
+
+	if (dmub->hw_funcs.get_fw_status)
+		*status = dmub->hw_funcs.get_fw_status(dmub);
+
+	return DMUB_STATUS_OK;
+}
-- 
2.25.1

_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply related	[flat|nested] 2+ messages in thread
* Re: [PATCH] drm/amd/display: Update dmub code
  2020-11-13 20:27 [PATCH] drm/amd/display: Update dmub code Bhawanpreet Lakha
@ 2020-11-13 21:55 ` Kazlauskas, Nicholas
  0 siblings, 0 replies; 2+ messages in thread
From: Kazlauskas, Nicholas @ 2020-11-13 21:55 UTC (permalink / raw)
  To: Bhawanpreet Lakha, alexander.deucher; +Cc: amd-gfx

On 2020-11-13 3:27 p.m., Bhawanpreet Lakha wrote:
> There is a delta in the dmub code
> - add boot options
> - add boot status
> - remove unused auto_load_is_done func pointer
> 
> Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>

Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>

Regards,
Nicholas Kazlauskas

> ---
>   drivers/gpu/drm/amd/display/dmub/dmub_srv.h   | 20 +++++++++++++-
>   .../gpu/drm/amd/display/dmub/inc/dmub_cmd.h   |  3 ++-
>   .../gpu/drm/amd/display/dmub/src/dmub_dcn20.c | 23 ++++++++++++++++
>   .../gpu/drm/amd/display/dmub/src/dmub_dcn20.h |  6 +++++
>   .../gpu/drm/amd/display/dmub/src/dmub_dcn21.c |  5 ----
>   .../gpu/drm/amd/display/dmub/src/dmub_dcn21.h |  2 --
>   .../gpu/drm/amd/display/dmub/src/dmub_dcn30.c |  5 ----
>   .../gpu/drm/amd/display/dmub/src/dmub_dcn30.h |  1 -
>   .../gpu/drm/amd/display/dmub/src/dmub_srv.c   | 26 ++++++++++++++-----
>   9 files changed, 70 insertions(+), 21 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/display/dmub/dmub_srv.h b/drivers/gpu/drm/amd/display/dmub/dmub_srv.h
> index ac41ae2d261b..b82a46890846 100644
> --- a/drivers/gpu/drm/amd/display/dmub/dmub_srv.h
> +++ b/drivers/gpu/drm/amd/display/dmub/dmub_srv.h
> @@ -265,8 +265,12 @@ struct dmub_srv_hw_funcs {
>   	bool (*is_hw_init)(struct dmub_srv *dmub);
>   
>   	bool (*is_phy_init)(struct dmub_srv *dmub);
> +	void (*enable_dmub_boot_options)(struct dmub_srv *dmub);
> +
> +	void (*skip_dmub_panel_power_sequence)(struct dmub_srv *dmub, bool skip);
> +
> +	union dmub_fw_boot_status (*get_fw_status)(struct dmub_srv *dmub);
>   
> -	bool (*is_auto_load_done)(struct dmub_srv *dmub);
>   
>   	void (*set_gpint)(struct dmub_srv *dmub,
>   			  union dmub_gpint_data_register reg);
> @@ -309,6 +313,7 @@ struct dmub_srv_hw_params {
>   	uint64_t fb_offset;
>   	uint32_t psp_version;
>   	bool load_inst_const;
> +	bool skip_panel_power_sequence;
>   };
>   
>   /**
> @@ -590,6 +595,19 @@ enum dmub_status dmub_srv_get_gpint_response(struct dmub_srv *dmub,
>    */
>   void dmub_flush_buffer_mem(const struct dmub_fb *fb);
>   
> +/**
> + * dmub_srv_get_fw_boot_status() - Returns the DMUB boot status bits.
> + *
> + * @dmub: the dmub service
> + * @status: out pointer for firmware status
> + *
> + * Return:
> + *   DMUB_STATUS_OK - success
> + *   DMUB_STATUS_INVALID - unspecified error, unsupported
> + */
> +enum dmub_status dmub_srv_get_fw_boot_status(struct dmub_srv *dmub,
> +					     union dmub_fw_boot_status *status);
> +
>   #if defined(__cplusplus)
>   }
>   #endif
> diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
> index b0d1347d13f0..9fd24f93a216 100644
> --- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
> +++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
> @@ -191,7 +191,8 @@ union dmub_fw_boot_options {
>   		uint32_t optimized_init : 1;
>   		uint32_t skip_phy_access : 1;
>   		uint32_t disable_clk_gate: 1;
> -		uint32_t reserved : 27;
> +		uint32_t skip_phy_init_panel_sequence: 1;
> +		uint32_t reserved : 26;
>   	} bits;
>   	uint32_t all;
>   };
> diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c
> index 2c4a2fe9311d..cafba1d23c6a 100644
> --- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c
> +++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c
> @@ -312,3 +312,26 @@ uint32_t dmub_dcn20_get_gpint_response(struct dmub_srv *dmub)
>   {
>   	return REG_READ(DMCUB_SCRATCH7);
>   }
> +
> +union dmub_fw_boot_status dmub_dcn20_get_fw_boot_status(struct dmub_srv *dmub)
> +{
> +	union dmub_fw_boot_status status;
> +
> +	status.all = REG_READ(DMCUB_SCRATCH0);
> +	return status;
> +}
> +
> +void dmub_dcn20_enable_dmub_boot_options(struct dmub_srv *dmub)
> +{
> +	union dmub_fw_boot_options boot_options = {0};
> +
> +	REG_WRITE(DMCUB_SCRATCH14, boot_options.all);
> +}
> +
> +void dmub_dcn20_skip_dmub_panel_power_sequence(struct dmub_srv *dmub, bool skip)
> +{
> +	union dmub_fw_boot_options boot_options;
> +	boot_options.all = REG_READ(DMCUB_SCRATCH14);
> +	boot_options.bits.skip_phy_init_panel_sequence = skip;
> +	REG_WRITE(DMCUB_SCRATCH14, boot_options.all);
> +}
> diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h
> index a316f260f6ac..d438f365cbb0 100644
> --- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h
> +++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h
> @@ -192,4 +192,10 @@ bool dmub_dcn20_is_gpint_acked(struct dmub_srv *dmub,
>   
>   uint32_t dmub_dcn20_get_gpint_response(struct dmub_srv *dmub);
>   
> +void dmub_dcn20_enable_dmub_boot_options(struct dmub_srv *dmub);
> +
> +void dmub_dcn20_skip_dmub_panel_power_sequence(struct dmub_srv *dmub, bool skip);
> +
> +union dmub_fw_boot_status dmub_dcn20_get_fw_boot_status(struct dmub_srv *dmub);
> +
>   #endif /* _DMUB_DCN20_H_ */
> diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn21.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn21.c
> index e8f488232e34..1cf67b3e4771 100644
> --- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn21.c
> +++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn21.c
> @@ -53,11 +53,6 @@ const struct dmub_srv_common_regs dmub_srv_dcn21_regs = {
>   
>   /* Shared functions. */
>   
> -bool dmub_dcn21_is_auto_load_done(struct dmub_srv *dmub)
> -{
> -	return (REG_READ(DMCUB_SCRATCH0) == 3);
> -}
> -
>   bool dmub_dcn21_is_phy_init(struct dmub_srv *dmub)
>   {
>   	return REG_READ(DMCUB_SCRATCH10) == 0;
> diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn21.h b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn21.h
> index 2bbea237137b..6fd5b0cd4ef3 100644
> --- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn21.h
> +++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn21.h
> @@ -34,8 +34,6 @@ extern const struct dmub_srv_common_regs dmub_srv_dcn21_regs;
>   
>   /* Hardware functions. */
>   
> -bool dmub_dcn21_is_auto_load_done(struct dmub_srv *dmub);
> -
>   bool dmub_dcn21_is_phy_init(struct dmub_srv *dmub);
>   
>   #endif /* _DMUB_DCN21_H_ */
> diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn30.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn30.c
> index 215178b8d415..f00df02ded81 100644
> --- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn30.c
> +++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn30.c
> @@ -188,8 +188,3 @@ void dmub_dcn30_setup_windows(struct dmub_srv *dmub,
>   		  DMCUB_REGION3_CW6_TOP_ADDRESS, cw6->region.top,
>   		  DMCUB_REGION3_CW6_ENABLE, 1);
>   }
> -
> -bool dmub_dcn30_is_auto_load_done(struct dmub_srv *dmub)
> -{
> -	return (REG_READ(DMCUB_SCRATCH0) > 0);
> -}
> diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn30.h b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn30.h
> index 4d8f52b8f12c..9a3afffd9b0f 100644
> --- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn30.h
> +++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn30.h
> @@ -45,6 +45,5 @@ void dmub_dcn30_setup_windows(struct dmub_srv *dmub,
>   			      const struct dmub_window *cw5,
>   			      const struct dmub_window *cw6);
>   
> -bool dmub_dcn30_is_auto_load_done(struct dmub_srv *dmub);
>   
>   #endif /* _DMUB_DCN30_H_ */
> diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
> index d11b96d132ad..ba8494cf005f 100644
> --- a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
> +++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
> @@ -153,17 +153,18 @@ static bool dmub_srv_hw_setup(struct dmub_srv *dmub, enum dmub_asic asic)
>   		funcs->set_gpint = dmub_dcn20_set_gpint;
>   		funcs->is_gpint_acked = dmub_dcn20_is_gpint_acked;
>   		funcs->get_gpint_response = dmub_dcn20_get_gpint_response;
> +		funcs->get_fw_status = dmub_dcn20_get_fw_boot_status;
> +		funcs->enable_dmub_boot_options = dmub_dcn20_enable_dmub_boot_options;
> +		funcs->skip_dmub_panel_power_sequence = dmub_dcn20_skip_dmub_panel_power_sequence;
>   
>   		if (asic == DMUB_ASIC_DCN21) {
>   			dmub->regs = &dmub_srv_dcn21_regs;
>   
> -			funcs->is_auto_load_done = dmub_dcn21_is_auto_load_done;
>   			funcs->is_phy_init = dmub_dcn21_is_phy_init;
>   		}
>   		if (asic == DMUB_ASIC_DCN30) {
>   			dmub->regs = &dmub_srv_dcn30_regs;
>   
> -			funcs->is_auto_load_done = dmub_dcn30_is_auto_load_done;
>   			funcs->backdoor_load = dmub_dcn30_backdoor_load;
>   			funcs->setup_windows = dmub_dcn30_setup_windows;
>   		}
> @@ -535,11 +536,10 @@ enum dmub_status dmub_srv_wait_for_auto_load(struct dmub_srv *dmub,
>   	if (!dmub->hw_init)
>   		return DMUB_STATUS_INVALID;
>   
> -	if (!dmub->hw_funcs.is_auto_load_done)
> -		return DMUB_STATUS_OK;
> -
>   	for (i = 0; i <= timeout_us; i += 100) {
> -		if (dmub->hw_funcs.is_auto_load_done(dmub))
> +		union dmub_fw_boot_status status = dmub->hw_funcs.get_fw_status(dmub);
> +
> +		if (status.bits.dal_fw && status.bits.mailbox_rdy)
>   			return DMUB_STATUS_OK;
>   
>   		udelay(100);
> @@ -634,3 +634,17 @@ enum dmub_status dmub_srv_get_gpint_response(struct dmub_srv *dmub,
>   
>   	return DMUB_STATUS_OK;
>   }
> +
> +enum dmub_status dmub_srv_get_fw_boot_status(struct dmub_srv *dmub,
> +					     union dmub_fw_boot_status *status)
> +{
> +	status->all = 0;
> +
> +	if (!dmub->sw_init)
> +		return DMUB_STATUS_INVALID;
> +
> +	if (dmub->hw_funcs.get_fw_status)
> +		*status = dmub->hw_funcs.get_fw_status(dmub);
> +
> +	return DMUB_STATUS_OK;
> +}
> 

_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply	[flat|nested] 2+ messages in thread
end of thread, other threads:[~2020-11-13 21:55 UTC | newest]

Thread overview: 2+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2020-11-13 20:27 [PATCH] drm/amd/display: Update dmub code Bhawanpreet Lakha
2020-11-13 21:55 ` Kazlauskas, Nicholas

This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox