* [PATCH v3] drm/dp: Add Additional DP2 Headers
@ 2021-09-27 19:23 Fangzhi Zuo
2021-09-28 15:19 ` Harry Wentland
2022-02-03 11:58 ` binary constants (was: Re: [PATCH v3] drm/dp: Add Additional DP2 Headers) Jani Nikula
0 siblings, 2 replies; 7+ messages in thread
From: Fangzhi Zuo @ 2021-09-27 19:23 UTC (permalink / raw)
To: dri-devel, amd-gfx, intel-gfx, harry.wentland, jani.nikula
Cc: Nicholas.Kazlauskas, wayne.lin, Fangzhi Zuo
Include FEC, DSC, Link Training related headers.
Change since v2
- Align with the spec for DP_DSC_SUPPORT_AND_DSC_DECODER_COUNT
Signed-off-by: Fangzhi Zuo <Jerry.Zuo@amd.com>
---
This patch is based on top of the other DP2.0 work in
"drm/dp: add LTTPR DP 2.0 DPCD addresses"
---
include/drm/drm_dp_helper.h | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 1d5b3dbb6e56..a1df35aa6e68 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -453,6 +453,7 @@ struct drm_panel;
# define DP_FEC_UNCORR_BLK_ERROR_COUNT_CAP (1 << 1)
# define DP_FEC_CORR_BLK_ERROR_COUNT_CAP (1 << 2)
# define DP_FEC_BIT_ERROR_COUNT_CAP (1 << 3)
+#define DP_FEC_CAPABILITY_1 0x091 /* 2.0 */
/* DP-HDMI2.1 PCON DSC ENCODER SUPPORT */
#define DP_PCON_DSC_ENCODER_CAP_SIZE 0xC /* 0x9E - 0x92 */
@@ -537,6 +538,9 @@ struct drm_panel;
#define DP_DSC_BRANCH_OVERALL_THROUGHPUT_1 0x0a1
#define DP_DSC_BRANCH_MAX_LINE_WIDTH 0x0a2
+/* DFP Capability Extension */
+#define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+
/* Link Configuration */
#define DP_LINK_BW_SET 0x100
# define DP_LINK_RATE_TABLE 0x00 /* eDP 1.4 */
@@ -688,6 +692,7 @@ struct drm_panel;
#define DP_DSC_ENABLE 0x160 /* DP 1.4 */
# define DP_DECOMPRESSION_EN (1 << 0)
+#define DP_DSC_CONFIGURATION 0x161 /* DP 2.0 */
#define DP_PSR_EN_CFG 0x170 /* XXX 1.2? */
# define DP_PSR_ENABLE BIT(0)
@@ -743,6 +748,7 @@ struct drm_panel;
# define DP_RECEIVE_PORT_0_STATUS (1 << 0)
# define DP_RECEIVE_PORT_1_STATUS (1 << 1)
# define DP_STREAM_REGENERATION_STATUS (1 << 2) /* 2.0 */
+# define DP_INTRA_HOP_AUX_REPLY_INDICATION (1 << 3) /* 2.0 */
#define DP_ADJUST_REQUEST_LANE0_1 0x206
#define DP_ADJUST_REQUEST_LANE2_3 0x207
@@ -865,6 +871,8 @@ struct drm_panel;
# define DP_PHY_TEST_PATTERN_80BIT_CUSTOM 0x4
# define DP_PHY_TEST_PATTERN_CP2520 0x5
+#define DP_PHY_SQUARE_PATTERN 0x249
+
#define DP_TEST_HBR2_SCRAMBLER_RESET 0x24A
#define DP_TEST_80BIT_CUSTOM_PATTERN_7_0 0x250
#define DP_TEST_80BIT_CUSTOM_PATTERN_15_8 0x251
@@ -1109,6 +1117,18 @@ struct drm_panel;
#define DP_128B132B_TRAINING_AUX_RD_INTERVAL 0x2216 /* 2.0 */
# define DP_128B132B_TRAINING_AUX_RD_INTERVAL_MASK 0x7f
+#define DP_TEST_264BIT_CUSTOM_PATTERN_7_0 0x2230
+#define DP_TEST_264BIT_CUSTOM_PATTERN_263_256 0x2250
+
+/* DSC Extended Capability Branch Total DSC Resources */
+#define DP_DSC_SUPPORT_AND_DSC_DECODER_COUNT 0x2260 /* 2.0 */
+# define DP_DSC_DECODER_COUNT_MASK (0b111 << 5)
+# define DP_DSC_DECODER_COUNT_SHIFT 5
+#define DP_DSC_MAX_SLICE_COUNT_AND_AGGREGATION_0 0x2270 /* 2.0 */
+# define DP_DSC_DECODER_0_MAXIMUM_SLICE_COUNT_MASK (1 << 0)
+# define DP_DSC_DECODER_0_AGGREGATION_SUPPORT_MASK (0b111 << 1)
+# define DP_DSC_DECODER_0_AGGREGATION_SUPPORT_SHIFT 1
+
/* Protocol Converter Extension */
/* HDMI CEC tunneling over AUX DP 1.3 section 5.3.3.3.1 DPCD 1.4+ */
#define DP_CEC_TUNNELING_CAPABILITY 0x3000
--
2.25.1
^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH v3] drm/dp: Add Additional DP2 Headers
2021-09-27 19:23 [PATCH v3] drm/dp: Add Additional DP2 Headers Fangzhi Zuo
@ 2021-09-28 15:19 ` Harry Wentland
2021-09-30 21:21 ` Rodrigo Siqueira
2022-02-03 11:58 ` binary constants (was: Re: [PATCH v3] drm/dp: Add Additional DP2 Headers) Jani Nikula
1 sibling, 1 reply; 7+ messages in thread
From: Harry Wentland @ 2021-09-28 15:19 UTC (permalink / raw)
To: Fangzhi Zuo, dri-devel, amd-gfx, intel-gfx, jani.nikula
Cc: Nicholas.Kazlauskas, wayne.lin
On 2021-09-27 15:23, Fangzhi Zuo wrote:
> Include FEC, DSC, Link Training related headers.
>
> Change since v2
> - Align with the spec for DP_DSC_SUPPORT_AND_DSC_DECODER_COUNT
>
> Signed-off-by: Fangzhi Zuo <Jerry.Zuo@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Harry
> ---
> This patch is based on top of the other DP2.0 work in
> "drm/dp: add LTTPR DP 2.0 DPCD addresses"
> ---
> include/drm/drm_dp_helper.h | 20 ++++++++++++++++++++
> 1 file changed, 20 insertions(+)
>
> diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
> index 1d5b3dbb6e56..a1df35aa6e68 100644
> --- a/include/drm/drm_dp_helper.h
> +++ b/include/drm/drm_dp_helper.h
> @@ -453,6 +453,7 @@ struct drm_panel;
> # define DP_FEC_UNCORR_BLK_ERROR_COUNT_CAP (1 << 1)
> # define DP_FEC_CORR_BLK_ERROR_COUNT_CAP (1 << 2)
> # define DP_FEC_BIT_ERROR_COUNT_CAP (1 << 3)
> +#define DP_FEC_CAPABILITY_1 0x091 /* 2.0 */
>
> /* DP-HDMI2.1 PCON DSC ENCODER SUPPORT */
> #define DP_PCON_DSC_ENCODER_CAP_SIZE 0xC /* 0x9E - 0x92 */
> @@ -537,6 +538,9 @@ struct drm_panel;
> #define DP_DSC_BRANCH_OVERALL_THROUGHPUT_1 0x0a1
> #define DP_DSC_BRANCH_MAX_LINE_WIDTH 0x0a2
>
> +/* DFP Capability Extension */
> +#define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> +
> /* Link Configuration */
> #define DP_LINK_BW_SET 0x100
> # define DP_LINK_RATE_TABLE 0x00 /* eDP 1.4 */
> @@ -688,6 +692,7 @@ struct drm_panel;
>
> #define DP_DSC_ENABLE 0x160 /* DP 1.4 */
> # define DP_DECOMPRESSION_EN (1 << 0)
> +#define DP_DSC_CONFIGURATION 0x161 /* DP 2.0 */
>
> #define DP_PSR_EN_CFG 0x170 /* XXX 1.2? */
> # define DP_PSR_ENABLE BIT(0)
> @@ -743,6 +748,7 @@ struct drm_panel;
> # define DP_RECEIVE_PORT_0_STATUS (1 << 0)
> # define DP_RECEIVE_PORT_1_STATUS (1 << 1)
> # define DP_STREAM_REGENERATION_STATUS (1 << 2) /* 2.0 */
> +# define DP_INTRA_HOP_AUX_REPLY_INDICATION (1 << 3) /* 2.0 */
>
> #define DP_ADJUST_REQUEST_LANE0_1 0x206
> #define DP_ADJUST_REQUEST_LANE2_3 0x207
> @@ -865,6 +871,8 @@ struct drm_panel;
> # define DP_PHY_TEST_PATTERN_80BIT_CUSTOM 0x4
> # define DP_PHY_TEST_PATTERN_CP2520 0x5
>
> +#define DP_PHY_SQUARE_PATTERN 0x249
> +
> #define DP_TEST_HBR2_SCRAMBLER_RESET 0x24A
> #define DP_TEST_80BIT_CUSTOM_PATTERN_7_0 0x250
> #define DP_TEST_80BIT_CUSTOM_PATTERN_15_8 0x251
> @@ -1109,6 +1117,18 @@ struct drm_panel;
> #define DP_128B132B_TRAINING_AUX_RD_INTERVAL 0x2216 /* 2.0 */
> # define DP_128B132B_TRAINING_AUX_RD_INTERVAL_MASK 0x7f
>
> +#define DP_TEST_264BIT_CUSTOM_PATTERN_7_0 0x2230
> +#define DP_TEST_264BIT_CUSTOM_PATTERN_263_256 0x2250
> +
> +/* DSC Extended Capability Branch Total DSC Resources */
> +#define DP_DSC_SUPPORT_AND_DSC_DECODER_COUNT 0x2260 /* 2.0 */
> +# define DP_DSC_DECODER_COUNT_MASK (0b111 << 5)
> +# define DP_DSC_DECODER_COUNT_SHIFT 5
> +#define DP_DSC_MAX_SLICE_COUNT_AND_AGGREGATION_0 0x2270 /* 2.0 */
> +# define DP_DSC_DECODER_0_MAXIMUM_SLICE_COUNT_MASK (1 << 0)
> +# define DP_DSC_DECODER_0_AGGREGATION_SUPPORT_MASK (0b111 << 1)
> +# define DP_DSC_DECODER_0_AGGREGATION_SUPPORT_SHIFT 1
> +
> /* Protocol Converter Extension */
> /* HDMI CEC tunneling over AUX DP 1.3 section 5.3.3.3.1 DPCD 1.4+ */
> #define DP_CEC_TUNNELING_CAPABILITY 0x3000
>
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v3] drm/dp: Add Additional DP2 Headers
2021-09-28 15:19 ` Harry Wentland
@ 2021-09-30 21:21 ` Rodrigo Siqueira
2021-10-08 8:36 ` Tvrtko Ursulin
0 siblings, 1 reply; 7+ messages in thread
From: Rodrigo Siqueira @ 2021-09-30 21:21 UTC (permalink / raw)
To: Harry Wentland
Cc: Fangzhi Zuo, dri-devel, amd-gfx, intel-gfx, jani.nikula,
Nicholas.Kazlauskas, wayne.lin
Applied to drm-misc-next.
Thanks
On 09/28, Harry Wentland wrote:
> On 2021-09-27 15:23, Fangzhi Zuo wrote:
> > Include FEC, DSC, Link Training related headers.
> >
> > Change since v2
> > - Align with the spec for DP_DSC_SUPPORT_AND_DSC_DECODER_COUNT
> >
> > Signed-off-by: Fangzhi Zuo <Jerry.Zuo@amd.com>
>
> Reviewed-by: Harry Wentland <harry.wentland@amd.com>
>
> Harry
>
> > ---
> > This patch is based on top of the other DP2.0 work in
> > "drm/dp: add LTTPR DP 2.0 DPCD addresses"
> > ---
> > include/drm/drm_dp_helper.h | 20 ++++++++++++++++++++
> > 1 file changed, 20 insertions(+)
> >
> > diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
> > index 1d5b3dbb6e56..a1df35aa6e68 100644
> > --- a/include/drm/drm_dp_helper.h
> > +++ b/include/drm/drm_dp_helper.h
> > @@ -453,6 +453,7 @@ struct drm_panel;
> > # define DP_FEC_UNCORR_BLK_ERROR_COUNT_CAP (1 << 1)
> > # define DP_FEC_CORR_BLK_ERROR_COUNT_CAP (1 << 2)
> > # define DP_FEC_BIT_ERROR_COUNT_CAP (1 << 3)
> > +#define DP_FEC_CAPABILITY_1 0x091 /* 2.0 */
> >
> > /* DP-HDMI2.1 PCON DSC ENCODER SUPPORT */
> > #define DP_PCON_DSC_ENCODER_CAP_SIZE 0xC /* 0x9E - 0x92 */
> > @@ -537,6 +538,9 @@ struct drm_panel;
> > #define DP_DSC_BRANCH_OVERALL_THROUGHPUT_1 0x0a1
> > #define DP_DSC_BRANCH_MAX_LINE_WIDTH 0x0a2
> >
> > +/* DFP Capability Extension */
> > +#define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> > +
> > /* Link Configuration */
> > #define DP_LINK_BW_SET 0x100
> > # define DP_LINK_RATE_TABLE 0x00 /* eDP 1.4 */
> > @@ -688,6 +692,7 @@ struct drm_panel;
> >
> > #define DP_DSC_ENABLE 0x160 /* DP 1.4 */
> > # define DP_DECOMPRESSION_EN (1 << 0)
> > +#define DP_DSC_CONFIGURATION 0x161 /* DP 2.0 */
> >
> > #define DP_PSR_EN_CFG 0x170 /* XXX 1.2? */
> > # define DP_PSR_ENABLE BIT(0)
> > @@ -743,6 +748,7 @@ struct drm_panel;
> > # define DP_RECEIVE_PORT_0_STATUS (1 << 0)
> > # define DP_RECEIVE_PORT_1_STATUS (1 << 1)
> > # define DP_STREAM_REGENERATION_STATUS (1 << 2) /* 2.0 */
> > +# define DP_INTRA_HOP_AUX_REPLY_INDICATION (1 << 3) /* 2.0 */
> >
> > #define DP_ADJUST_REQUEST_LANE0_1 0x206
> > #define DP_ADJUST_REQUEST_LANE2_3 0x207
> > @@ -865,6 +871,8 @@ struct drm_panel;
> > # define DP_PHY_TEST_PATTERN_80BIT_CUSTOM 0x4
> > # define DP_PHY_TEST_PATTERN_CP2520 0x5
> >
> > +#define DP_PHY_SQUARE_PATTERN 0x249
> > +
> > #define DP_TEST_HBR2_SCRAMBLER_RESET 0x24A
> > #define DP_TEST_80BIT_CUSTOM_PATTERN_7_0 0x250
> > #define DP_TEST_80BIT_CUSTOM_PATTERN_15_8 0x251
> > @@ -1109,6 +1117,18 @@ struct drm_panel;
> > #define DP_128B132B_TRAINING_AUX_RD_INTERVAL 0x2216 /* 2.0 */
> > # define DP_128B132B_TRAINING_AUX_RD_INTERVAL_MASK 0x7f
> >
> > +#define DP_TEST_264BIT_CUSTOM_PATTERN_7_0 0x2230
> > +#define DP_TEST_264BIT_CUSTOM_PATTERN_263_256 0x2250
> > +
> > +/* DSC Extended Capability Branch Total DSC Resources */
> > +#define DP_DSC_SUPPORT_AND_DSC_DECODER_COUNT 0x2260 /* 2.0 */
> > +# define DP_DSC_DECODER_COUNT_MASK (0b111 << 5)
> > +# define DP_DSC_DECODER_COUNT_SHIFT 5
> > +#define DP_DSC_MAX_SLICE_COUNT_AND_AGGREGATION_0 0x2270 /* 2.0 */
> > +# define DP_DSC_DECODER_0_MAXIMUM_SLICE_COUNT_MASK (1 << 0)
> > +# define DP_DSC_DECODER_0_AGGREGATION_SUPPORT_MASK (0b111 << 1)
> > +# define DP_DSC_DECODER_0_AGGREGATION_SUPPORT_SHIFT 1
> > +
> > /* Protocol Converter Extension */
> > /* HDMI CEC tunneling over AUX DP 1.3 section 5.3.3.3.1 DPCD 1.4+ */
> > #define DP_CEC_TUNNELING_CAPABILITY 0x3000
> >
>
--
Rodrigo Siqueira
https://siqueira.tech
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v3] drm/dp: Add Additional DP2 Headers
2021-09-30 21:21 ` Rodrigo Siqueira
@ 2021-10-08 8:36 ` Tvrtko Ursulin
2021-10-08 21:03 ` Harry Wentland
0 siblings, 1 reply; 7+ messages in thread
From: Tvrtko Ursulin @ 2021-10-08 8:36 UTC (permalink / raw)
To: Rodrigo Siqueira, Harry Wentland
Cc: Fangzhi Zuo, dri-devel, amd-gfx, intel-gfx, jani.nikula,
Nicholas.Kazlauskas, wayne.lin
Hi,
Is it my checkout only or this causes a lot of build warnings for everyone?
./include/drm/drm_dp_helper.h:1120: warning: "DP_TEST_264BIT_CUSTOM_PATTERN_7_0" redefined
1120 | #define DP_TEST_264BIT_CUSTOM_PATTERN_7_0 0x2230
|
In file included from ./drivers/gpu/drm/amd/amdgpu/../display/dc/dc_types.h:35,
from ./drivers/gpu/drm/amd/amdgpu/../display/dc/dm_services_types.h:30,
from ./drivers/gpu/drm/amd/amdgpu/../include/dm_pp_interface.h:26,
from drivers/gpu/drm/amd/amdgpu/amdgpu.h:66,
from drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:40:
./drivers/gpu/drm/amd/amdgpu/../display/dc/dc_dp_types.h:871: note: this is the location of the previous definition
Etc..
Regards,
Tvrtko
On 30/09/2021 22:21, Rodrigo Siqueira wrote:
> Applied to drm-misc-next.
>
> Thanks
>
> On 09/28, Harry Wentland wrote:
>> On 2021-09-27 15:23, Fangzhi Zuo wrote:
>>> Include FEC, DSC, Link Training related headers.
>>>
>>> Change since v2
>>> - Align with the spec for DP_DSC_SUPPORT_AND_DSC_DECODER_COUNT
>>>
>>> Signed-off-by: Fangzhi Zuo <Jerry.Zuo@amd.com>
>>
>> Reviewed-by: Harry Wentland <harry.wentland@amd.com>
>>
>> Harry
>>
>>> ---
>>> This patch is based on top of the other DP2.0 work in
>>> "drm/dp: add LTTPR DP 2.0 DPCD addresses"
>>> ---
>>> include/drm/drm_dp_helper.h | 20 ++++++++++++++++++++
>>> 1 file changed, 20 insertions(+)
>>>
>>> diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
>>> index 1d5b3dbb6e56..a1df35aa6e68 100644
>>> --- a/include/drm/drm_dp_helper.h
>>> +++ b/include/drm/drm_dp_helper.h
>>> @@ -453,6 +453,7 @@ struct drm_panel;
>>> # define DP_FEC_UNCORR_BLK_ERROR_COUNT_CAP (1 << 1)
>>> # define DP_FEC_CORR_BLK_ERROR_COUNT_CAP (1 << 2)
>>> # define DP_FEC_BIT_ERROR_COUNT_CAP (1 << 3)
>>> +#define DP_FEC_CAPABILITY_1 0x091 /* 2.0 */
>>>
>>> /* DP-HDMI2.1 PCON DSC ENCODER SUPPORT */
>>> #define DP_PCON_DSC_ENCODER_CAP_SIZE 0xC /* 0x9E - 0x92 */
>>> @@ -537,6 +538,9 @@ struct drm_panel;
>>> #define DP_DSC_BRANCH_OVERALL_THROUGHPUT_1 0x0a1
>>> #define DP_DSC_BRANCH_MAX_LINE_WIDTH 0x0a2
>>>
>>> +/* DFP Capability Extension */
>>> +#define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
>>> +
>>> /* Link Configuration */
>>> #define DP_LINK_BW_SET 0x100
>>> # define DP_LINK_RATE_TABLE 0x00 /* eDP 1.4 */
>>> @@ -688,6 +692,7 @@ struct drm_panel;
>>>
>>> #define DP_DSC_ENABLE 0x160 /* DP 1.4 */
>>> # define DP_DECOMPRESSION_EN (1 << 0)
>>> +#define DP_DSC_CONFIGURATION 0x161 /* DP 2.0 */
>>>
>>> #define DP_PSR_EN_CFG 0x170 /* XXX 1.2? */
>>> # define DP_PSR_ENABLE BIT(0)
>>> @@ -743,6 +748,7 @@ struct drm_panel;
>>> # define DP_RECEIVE_PORT_0_STATUS (1 << 0)
>>> # define DP_RECEIVE_PORT_1_STATUS (1 << 1)
>>> # define DP_STREAM_REGENERATION_STATUS (1 << 2) /* 2.0 */
>>> +# define DP_INTRA_HOP_AUX_REPLY_INDICATION (1 << 3) /* 2.0 */
>>>
>>> #define DP_ADJUST_REQUEST_LANE0_1 0x206
>>> #define DP_ADJUST_REQUEST_LANE2_3 0x207
>>> @@ -865,6 +871,8 @@ struct drm_panel;
>>> # define DP_PHY_TEST_PATTERN_80BIT_CUSTOM 0x4
>>> # define DP_PHY_TEST_PATTERN_CP2520 0x5
>>>
>>> +#define DP_PHY_SQUARE_PATTERN 0x249
>>> +
>>> #define DP_TEST_HBR2_SCRAMBLER_RESET 0x24A
>>> #define DP_TEST_80BIT_CUSTOM_PATTERN_7_0 0x250
>>> #define DP_TEST_80BIT_CUSTOM_PATTERN_15_8 0x251
>>> @@ -1109,6 +1117,18 @@ struct drm_panel;
>>> #define DP_128B132B_TRAINING_AUX_RD_INTERVAL 0x2216 /* 2.0 */
>>> # define DP_128B132B_TRAINING_AUX_RD_INTERVAL_MASK 0x7f
>>>
>>> +#define DP_TEST_264BIT_CUSTOM_PATTERN_7_0 0x2230
>>> +#define DP_TEST_264BIT_CUSTOM_PATTERN_263_256 0x2250
>>> +
>>> +/* DSC Extended Capability Branch Total DSC Resources */
>>> +#define DP_DSC_SUPPORT_AND_DSC_DECODER_COUNT 0x2260 /* 2.0 */
>>> +# define DP_DSC_DECODER_COUNT_MASK (0b111 << 5)
>>> +# define DP_DSC_DECODER_COUNT_SHIFT 5
>>> +#define DP_DSC_MAX_SLICE_COUNT_AND_AGGREGATION_0 0x2270 /* 2.0 */
>>> +# define DP_DSC_DECODER_0_MAXIMUM_SLICE_COUNT_MASK (1 << 0)
>>> +# define DP_DSC_DECODER_0_AGGREGATION_SUPPORT_MASK (0b111 << 1)
>>> +# define DP_DSC_DECODER_0_AGGREGATION_SUPPORT_SHIFT 1
>>> +
>>> /* Protocol Converter Extension */
>>> /* HDMI CEC tunneling over AUX DP 1.3 section 5.3.3.3.1 DPCD 1.4+ */
>>> #define DP_CEC_TUNNELING_CAPABILITY 0x3000
>>>
>>
>
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v3] drm/dp: Add Additional DP2 Headers
2021-10-08 8:36 ` Tvrtko Ursulin
@ 2021-10-08 21:03 ` Harry Wentland
0 siblings, 0 replies; 7+ messages in thread
From: Harry Wentland @ 2021-10-08 21:03 UTC (permalink / raw)
To: Tvrtko Ursulin, Rodrigo Siqueira
Cc: Fangzhi Zuo, dri-devel, amd-gfx, intel-gfx, jani.nikula,
Nicholas.Kazlauskas, wayne.lin
On 2021-10-08 04:36, Tvrtko Ursulin wrote:
>
> Hi,
>
> Is it my checkout only or this causes a lot of build warnings for everyone?
>
> ./include/drm/drm_dp_helper.h:1120: warning: "DP_TEST_264BIT_CUSTOM_PATTERN_7_0" redefined
> 1120 | #define DP_TEST_264BIT_CUSTOM_PATTERN_7_0 0x2230
> |
> In file included from ./drivers/gpu/drm/amd/amdgpu/../display/dc/dc_types.h:35,
> from ./drivers/gpu/drm/amd/amdgpu/../display/dc/dm_services_types.h:30,
> from ./drivers/gpu/drm/amd/amdgpu/../include/dm_pp_interface.h:26,
> from drivers/gpu/drm/amd/amdgpu/amdgpu.h:66,
> from drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:40:
> ./drivers/gpu/drm/amd/amdgpu/../display/dc/dc_dp_types.h:871: note: this is the location of the previous definition
>
> Etc..
>
Fixed by https://patchwork.freedesktop.org/patch/456190/?series=95166&rev=2 but looks like it's not in drm-misc-next.
Siqueira, do you have bandwidth to pull that patch into drm-misc-next?
Harry
> Regards,
>
> Tvrtko
>
>
> On 30/09/2021 22:21, Rodrigo Siqueira wrote:
>> Applied to drm-misc-next.
>>
>> Thanks
>>
>> On 09/28, Harry Wentland wrote:
>>> On 2021-09-27 15:23, Fangzhi Zuo wrote:
>>>> Include FEC, DSC, Link Training related headers.
>>>>
>>>> Change since v2
>>>> - Align with the spec for DP_DSC_SUPPORT_AND_DSC_DECODER_COUNT
>>>>
>>>> Signed-off-by: Fangzhi Zuo <Jerry.Zuo@amd.com>
>>>
>>> Reviewed-by: Harry Wentland <harry.wentland@amd.com>
>>>
>>> Harry
>>>
>>>> ---
>>>> This patch is based on top of the other DP2.0 work in
>>>> "drm/dp: add LTTPR DP 2.0 DPCD addresses"
>>>> ---
>>>> include/drm/drm_dp_helper.h | 20 ++++++++++++++++++++
>>>> 1 file changed, 20 insertions(+)
>>>>
>>>> diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
>>>> index 1d5b3dbb6e56..a1df35aa6e68 100644
>>>> --- a/include/drm/drm_dp_helper.h
>>>> +++ b/include/drm/drm_dp_helper.h
>>>> @@ -453,6 +453,7 @@ struct drm_panel;
>>>> # define DP_FEC_UNCORR_BLK_ERROR_COUNT_CAP (1 << 1)
>>>> # define DP_FEC_CORR_BLK_ERROR_COUNT_CAP (1 << 2)
>>>> # define DP_FEC_BIT_ERROR_COUNT_CAP (1 << 3)
>>>> +#define DP_FEC_CAPABILITY_1 0x091 /* 2.0 */
>>>> /* DP-HDMI2.1 PCON DSC ENCODER SUPPORT */
>>>> #define DP_PCON_DSC_ENCODER_CAP_SIZE 0xC /* 0x9E - 0x92 */
>>>> @@ -537,6 +538,9 @@ struct drm_panel;
>>>> #define DP_DSC_BRANCH_OVERALL_THROUGHPUT_1 0x0a1
>>>> #define DP_DSC_BRANCH_MAX_LINE_WIDTH 0x0a2
>>>> +/* DFP Capability Extension */
>>>> +#define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
>>>> +
>>>> /* Link Configuration */
>>>> #define DP_LINK_BW_SET 0x100
>>>> # define DP_LINK_RATE_TABLE 0x00 /* eDP 1.4 */
>>>> @@ -688,6 +692,7 @@ struct drm_panel;
>>>> #define DP_DSC_ENABLE 0x160 /* DP 1.4 */
>>>> # define DP_DECOMPRESSION_EN (1 << 0)
>>>> +#define DP_DSC_CONFIGURATION 0x161 /* DP 2.0 */
>>>> #define DP_PSR_EN_CFG 0x170 /* XXX 1.2? */
>>>> # define DP_PSR_ENABLE BIT(0)
>>>> @@ -743,6 +748,7 @@ struct drm_panel;
>>>> # define DP_RECEIVE_PORT_0_STATUS (1 << 0)
>>>> # define DP_RECEIVE_PORT_1_STATUS (1 << 1)
>>>> # define DP_STREAM_REGENERATION_STATUS (1 << 2) /* 2.0 */
>>>> +# define DP_INTRA_HOP_AUX_REPLY_INDICATION (1 << 3) /* 2.0 */
>>>> #define DP_ADJUST_REQUEST_LANE0_1 0x206
>>>> #define DP_ADJUST_REQUEST_LANE2_3 0x207
>>>> @@ -865,6 +871,8 @@ struct drm_panel;
>>>> # define DP_PHY_TEST_PATTERN_80BIT_CUSTOM 0x4
>>>> # define DP_PHY_TEST_PATTERN_CP2520 0x5
>>>> +#define DP_PHY_SQUARE_PATTERN 0x249
>>>> +
>>>> #define DP_TEST_HBR2_SCRAMBLER_RESET 0x24A
>>>> #define DP_TEST_80BIT_CUSTOM_PATTERN_7_0 0x250
>>>> #define DP_TEST_80BIT_CUSTOM_PATTERN_15_8 0x251
>>>> @@ -1109,6 +1117,18 @@ struct drm_panel;
>>>> #define DP_128B132B_TRAINING_AUX_RD_INTERVAL 0x2216 /* 2.0 */
>>>> # define DP_128B132B_TRAINING_AUX_RD_INTERVAL_MASK 0x7f
>>>> +#define DP_TEST_264BIT_CUSTOM_PATTERN_7_0 0x2230
>>>> +#define DP_TEST_264BIT_CUSTOM_PATTERN_263_256 0x2250
>>>> +
>>>> +/* DSC Extended Capability Branch Total DSC Resources */
>>>> +#define DP_DSC_SUPPORT_AND_DSC_DECODER_COUNT 0x2260 /* 2.0 */
>>>> +# define DP_DSC_DECODER_COUNT_MASK (0b111 << 5)
>>>> +# define DP_DSC_DECODER_COUNT_SHIFT 5
>>>> +#define DP_DSC_MAX_SLICE_COUNT_AND_AGGREGATION_0 0x2270 /* 2.0 */
>>>> +# define DP_DSC_DECODER_0_MAXIMUM_SLICE_COUNT_MASK (1 << 0)
>>>> +# define DP_DSC_DECODER_0_AGGREGATION_SUPPORT_MASK (0b111 << 1)
>>>> +# define DP_DSC_DECODER_0_AGGREGATION_SUPPORT_SHIFT 1
>>>> +
>>>> /* Protocol Converter Extension */
>>>> /* HDMI CEC tunneling over AUX DP 1.3 section 5.3.3.3.1 DPCD 1.4+ */
>>>> #define DP_CEC_TUNNELING_CAPABILITY 0x3000
>>>>
>>>
>>
^ permalink raw reply [flat|nested] 7+ messages in thread
* binary constants (was: Re: [PATCH v3] drm/dp: Add Additional DP2 Headers)
2021-09-27 19:23 [PATCH v3] drm/dp: Add Additional DP2 Headers Fangzhi Zuo
2021-09-28 15:19 ` Harry Wentland
@ 2022-02-03 11:58 ` Jani Nikula
2022-02-03 12:57 ` Daniel Vetter
1 sibling, 1 reply; 7+ messages in thread
From: Jani Nikula @ 2022-02-03 11:58 UTC (permalink / raw)
To: Fangzhi Zuo, dri-devel, amd-gfx, intel-gfx, harry.wentland
Cc: Daniel Vetter, Fangzhi Zuo, Dave Airlie, Nicholas.Kazlauskas,
wayne.lin
On Mon, 27 Sep 2021, Fangzhi Zuo <Jerry.Zuo@amd.com> wrote:
> +/* DSC Extended Capability Branch Total DSC Resources */
> +#define DP_DSC_SUPPORT_AND_DSC_DECODER_COUNT 0x2260 /* 2.0 */
> +# define DP_DSC_DECODER_COUNT_MASK (0b111 << 5)
> +# define DP_DSC_DECODER_COUNT_SHIFT 5
> +#define DP_DSC_MAX_SLICE_COUNT_AND_AGGREGATION_0 0x2270 /* 2.0 */
> +# define DP_DSC_DECODER_0_MAXIMUM_SLICE_COUNT_MASK (1 << 0)
> +# define DP_DSC_DECODER_0_AGGREGATION_SUPPORT_MASK (0b111 << 1)
> +# define DP_DSC_DECODER_0_AGGREGATION_SUPPORT_SHIFT 1
The patch was merged a while back, but only now I noticed the use of
binary constants, which in C is a GCC and Clang extension [1][2]. There
are some instances in the kernel, but not a whole lot.
Do we want to avoid or embrace them going forward? Or meh?
BR,
Jani.
[1] https://gcc.gnu.org/onlinedocs/gcc/Binary-constants.html
[2] https://clang.llvm.org/docs/LanguageExtensions.html#c-14-binary-literals
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: binary constants (was: Re: [PATCH v3] drm/dp: Add Additional DP2 Headers)
2022-02-03 11:58 ` binary constants (was: Re: [PATCH v3] drm/dp: Add Additional DP2 Headers) Jani Nikula
@ 2022-02-03 12:57 ` Daniel Vetter
0 siblings, 0 replies; 7+ messages in thread
From: Daniel Vetter @ 2022-02-03 12:57 UTC (permalink / raw)
To: Jani Nikula
Cc: Dave Airlie, intel-gfx, amd-gfx, Fangzhi Zuo, dri-devel,
Wayne.Lin, harry.wentland, nicholas.kazlauskas
On Thu, Feb 3, 2022 at 12:58 PM Jani Nikula <jani.nikula@intel.com> wrote:
>
> On Mon, 27 Sep 2021, Fangzhi Zuo <Jerry.Zuo@amd.com> wrote:
> > +/* DSC Extended Capability Branch Total DSC Resources */
> > +#define DP_DSC_SUPPORT_AND_DSC_DECODER_COUNT 0x2260 /* 2.0 */
> > +# define DP_DSC_DECODER_COUNT_MASK (0b111 << 5)
> > +# define DP_DSC_DECODER_COUNT_SHIFT 5
> > +#define DP_DSC_MAX_SLICE_COUNT_AND_AGGREGATION_0 0x2270 /* 2.0 */
> > +# define DP_DSC_DECODER_0_MAXIMUM_SLICE_COUNT_MASK (1 << 0)
> > +# define DP_DSC_DECODER_0_AGGREGATION_SUPPORT_MASK (0b111 << 1)
> > +# define DP_DSC_DECODER_0_AGGREGATION_SUPPORT_SHIFT 1
>
> The patch was merged a while back, but only now I noticed the use of
> binary constants, which in C is a GCC and Clang extension [1][2]. There
> are some instances in the kernel, but not a whole lot.
>
> Do we want to avoid or embrace them going forward? Or meh?
$ git grep '\<0b[01]*\>'
Gives me almost exclusive hits in
- .rst files
- .S assembler files
- comments and strings
So I think probably not? I mean there's also BIT() and BIT_MASK()
macros and stuff like that, and reading small masks is pretty simple.
-Daniel
>
>
> BR,
> Jani.
>
>
> [1] https://gcc.gnu.org/onlinedocs/gcc/Binary-constants.html
> [2] https://clang.llvm.org/docs/LanguageExtensions.html#c-14-binary-literals
>
> --
> Jani Nikula, Intel Open Source Graphics Center
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2022-02-03 13:58 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2021-09-27 19:23 [PATCH v3] drm/dp: Add Additional DP2 Headers Fangzhi Zuo
2021-09-28 15:19 ` Harry Wentland
2021-09-30 21:21 ` Rodrigo Siqueira
2021-10-08 8:36 ` Tvrtko Ursulin
2021-10-08 21:03 ` Harry Wentland
2022-02-03 11:58 ` binary constants (was: Re: [PATCH v3] drm/dp: Add Additional DP2 Headers) Jani Nikula
2022-02-03 12:57 ` Daniel Vetter
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