[PATCH 0/4] Documentation/amdgpu/display: describe color and blend mode properties mapping

[PATCH 0/4] Documentation/amdgpu/display: describe color and blend mode properties mapping

[Melissa Wen]

Patches 1 and 2 describe DM mapping of DRM color correction properties
to DC interface and where detached from 3D LUT RFC series [1]. Patches 3
and 4 describe MPC block programming that matches the three DRM blend
modes and came from previous work [2][3] and discussions on AMD issue
tracker. Let me know any misleading information.

[1] https://lore.kernel.org/amd-gfx/20220619223104.667413-1-mwen@igalia.com/
[2] https://lore.kernel.org/amd-gfx/20220329201835.2393141-1-mwen@igalia.com/
[3] https://lore.kernel.org/amd-gfx/7a95d6a4-bc2f-b0e8-83f8-8cc5b75599f2@amd.com/

Melissa Wen (4):
  Documentation/amdgpu_dm: Add DM color correction documentation
  Documentation/amdgpu/display: add DC color caps info
  drm/amd/display: add doc entries for MPC blending configuration
  Documentation/gpu/amdgpu/amdgpu_dm: add DM docs for pixel blend mode

 .../amdgpu/display/dcn2_cm_drm_current.svg    | 1370 +++++++++++++++
 .../amdgpu/display/dcn3_cm_drm_current.svg    | 1529 +++++++++++++++++
 .../gpu/amdgpu/display/display-manager.rst    |  142 ++
 Documentation/gpu/drm-kms.rst                 |    2 +
 .../amd/display/amdgpu_dm/amdgpu_dm_color.c   |  121 +-
 drivers/gpu/drm/amd/display/dc/dc.h           |   74 +-
 drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h   |   91 +-
 7 files changed, 3270 insertions(+), 59 deletions(-)
 create mode 100644 Documentation/gpu/amdgpu/display/dcn2_cm_drm_current.svg
 create mode 100644 Documentation/gpu/amdgpu/display/dcn3_cm_drm_current.svg

-- 
2.35.1

[PATCH 1/4] Documentation/amdgpu_dm: Add DM color correction documentation

[Melissa Wen]

AMDGPU DM maps DRM color management properties (degamma, ctm and gamma)
to DC color correction entities. Part of this mapping is already
documented as code comments and can be converted as kernel docs.

v2:
- rebase to amd-staging-drm-next

Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Melissa Wen <mwen@igalia.com>
---
 .../gpu/amdgpu/display/display-manager.rst    |   9 ++
 .../amd/display/amdgpu_dm/amdgpu_dm_color.c   | 121 +++++++++++++-----
 2 files changed, 98 insertions(+), 32 deletions(-)

diff --git a/Documentation/gpu/amdgpu/display/display-manager.rst b/Documentation/gpu/amdgpu/display/display-manager.rst
index 7ce31f89d9a0..b1b0f11aed83 100644
--- a/Documentation/gpu/amdgpu/display/display-manager.rst
+++ b/Documentation/gpu/amdgpu/display/display-manager.rst
@@ -40,3 +40,12 @@ Atomic Implementation
 
 .. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
    :functions: amdgpu_dm_atomic_check amdgpu_dm_atomic_commit_tail
+
+Color Management Properties
+===========================
+
+.. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
+   :doc: overview
+
+.. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
+   :internal:
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
index a71177305bcd..93c813089bff 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
@@ -29,7 +29,9 @@
 #include "modules/color/color_gamma.h"
 #include "basics/conversion.h"
 
-/*
+/**
+ * DOC: overview
+ *
  * The DC interface to HW gives us the following color management blocks
  * per pipe (surface):
  *
@@ -71,8 +73,8 @@
 
 #define MAX_DRM_LUT_VALUE 0xFFFF
 
-/*
- * Initialize the color module.
+/**
+ * amdgpu_dm_init_color_mod - Initialize the color module.
  *
  * We're not using the full color module, only certain components.
  * Only call setup functions for components that we need.
@@ -82,7 +84,14 @@ void amdgpu_dm_init_color_mod(void)
 	setup_x_points_distribution();
 }
 
-/* Extracts the DRM lut and lut size from a blob. */
+/**
+ * __extract_blob_lut - Extracts the DRM lut and lut size from a blob.
+ * @blob: DRM color mgmt property blob
+ * @size: lut size
+ *
+ * Returns:
+ * DRM LUT or NULL
+ */
 static const struct drm_color_lut *
 __extract_blob_lut(const struct drm_property_blob *blob, uint32_t *size)
 {
@@ -90,13 +99,18 @@ __extract_blob_lut(const struct drm_property_blob *blob, uint32_t *size)
 	return blob ? (struct drm_color_lut *)blob->data : NULL;
 }
 
-/*
- * Return true if the given lut is a linear mapping of values, i.e. it acts
- * like a bypass LUT.
+/**
+ * __is_lut_linear - check if the given lut is a linear mapping of values
+ * @lut: given lut to check values
+ * @size: lut size
  *
  * It is considered linear if the lut represents:
- * f(a) = (0xFF00/MAX_COLOR_LUT_ENTRIES-1)a; for integer a in
- *                                           [0, MAX_COLOR_LUT_ENTRIES)
+ * f(a) = (0xFF00/MAX_COLOR_LUT_ENTRIES-1)a; for integer a in [0,
+ * MAX_COLOR_LUT_ENTRIES)
+ *
+ * Returns:
+ * True if the given lut is a linear mapping of values, i.e. it acts like a
+ * bypass LUT. Otherwise, false.
  */
 static bool __is_lut_linear(const struct drm_color_lut *lut, uint32_t size)
 {
@@ -119,9 +133,13 @@ static bool __is_lut_linear(const struct drm_color_lut *lut, uint32_t size)
 	return true;
 }
 
-/*
- * Convert the drm_color_lut to dc_gamma. The conversion depends on the size
- * of the lut - whether or not it's legacy.
+/**
+ * __drm_lut_to_dc_gamma - convert the drm_color_lut to dc_gamma.
+ * @lut: DRM lookup table for color conversion
+ * @gamma: DC gamma to set entries
+ * @is_legacy: legacy or atomic gamma
+ *
+ * The conversion depends on the size of the lut - whether or not it's legacy.
  */
 static void __drm_lut_to_dc_gamma(const struct drm_color_lut *lut,
 				  struct dc_gamma *gamma, bool is_legacy)
@@ -154,8 +172,11 @@ static void __drm_lut_to_dc_gamma(const struct drm_color_lut *lut,
 	}
 }
 
-/*
- * Converts a DRM CTM to a DC CSC float matrix.
+/**
+ * __drm_ctm_to_dc_matrix - converts a DRM CTM to a DC CSC float matrix
+ * @ctm: DRM color transformation matrix
+ * @matrix: DC CSC float matrix
+ *
  * The matrix needs to be a 3x4 (12 entry) matrix.
  */
 static void __drm_ctm_to_dc_matrix(const struct drm_color_ctm *ctm,
@@ -189,7 +210,18 @@ static void __drm_ctm_to_dc_matrix(const struct drm_color_ctm *ctm,
 	}
 }
 
-/* Calculates the legacy transfer function - only for sRGB input space. */
+/**
+ * __set_legacy_tf - Calculates the legacy transfer function
+ * @func: transfer function
+ * @lut: lookup table that defines the color space
+ * @lut_size: size of respective lut
+ * @has_rom: if ROM can be used for hardcoded curve
+ *
+ * Only for sRGB input space
+ *
+ * Returns:
+ * 0 in case of sucess, -ENOMEM if fails
+ */
 static int __set_legacy_tf(struct dc_transfer_func *func,
 			   const struct drm_color_lut *lut, uint32_t lut_size,
 			   bool has_rom)
@@ -218,7 +250,16 @@ static int __set_legacy_tf(struct dc_transfer_func *func,
 	return res ? 0 : -ENOMEM;
 }
 
-/* Calculates the output transfer function based on expected input space. */
+/**
+ * __set_output_tf - calculates the output transfer function based on expected input space.
+ * @func: transfer function
+ * @lut: lookup table that defines the color space
+ * @lut_size: size of respective lut
+ * @has_rom: if ROM can be used for hardcoded curve
+ *
+ * Returns:
+ * 0 in case of success. -ENOMEM if fails.
+ */
 static int __set_output_tf(struct dc_transfer_func *func,
 			   const struct drm_color_lut *lut, uint32_t lut_size,
 			   bool has_rom)
@@ -239,7 +280,7 @@ static int __set_output_tf(struct dc_transfer_func *func,
 	__drm_lut_to_dc_gamma(lut, gamma, false);
 
 	if (func->tf == TRANSFER_FUNCTION_LINEAR) {
-		/*
+		/**
 		 * Color module doesn't like calculating regamma params
 		 * on top of a linear input. But degamma params can be used
 		 * instead to simulate this.
@@ -262,7 +303,16 @@ static int __set_output_tf(struct dc_transfer_func *func,
 	return res ? 0 : -ENOMEM;
 }
 
-/* Caculates the input transfer function based on expected input space. */
+/**
+ * __set_input_tf - calculates the input transfer function based on expected
+ * input space.
+ * @func: transfer function
+ * @lut: lookup table that defines the color space
+ * @lut_size: size of respective lut.
+ *
+ * Returns:
+ * 0 in case of success. -ENOMEM if fails.
+ */
 static int __set_input_tf(struct dc_transfer_func *func,
 			  const struct drm_color_lut *lut, uint32_t lut_size)
 {
@@ -285,13 +335,15 @@ static int __set_input_tf(struct dc_transfer_func *func,
 }
 
 /**
- * amdgpu_dm_verify_lut_sizes
+ * amdgpu_dm_verify_lut_sizes - verifies if DRM luts match the hw supported sizes
  * @crtc_state: the DRM CRTC state
  *
- * Verifies that the Degamma and Gamma LUTs attached to the |crtc_state| are of
- * the expected size.
+ * Verifies that the Degamma and Gamma LUTs attached to the &crtc_state
+ * are of the expected size.
  *
- * Returns 0 on success.
+ * Returns:
+ * 0 on success.
+ * -EINVAL if any lut sizes are invalid.
  */
 int amdgpu_dm_verify_lut_sizes(const struct drm_crtc_state *crtc_state)
 {
@@ -327,9 +379,9 @@ int amdgpu_dm_verify_lut_sizes(const struct drm_crtc_state *crtc_state)
  * of the HW blocks as long as the CRTC CTM always comes before the
  * CRTC RGM and after the CRTC DGM.
  *
- * The CRTC RGM block will be placed in the RGM LUT block if it is non-linear.
- * The CRTC DGM block will be placed in the DGM LUT block if it is non-linear.
- * The CRTC CTM will be placed in the gamut remap block if it is non-linear.
+ * * The CRTC RGM block will be placed in the RGM LUT block if it is non-linear.
+ * * The CRTC DGM block will be placed in the DGM LUT block if it is non-linear.
+ * * The CRTC CTM will be placed in the gamut remap block if it is non-linear.
  *
  * The RGM block is typically more fully featured and accurate across
  * all ASICs - DCE can't support a custom non-linear CRTC DGM.
@@ -338,7 +390,9 @@ int amdgpu_dm_verify_lut_sizes(const struct drm_crtc_state *crtc_state)
  * management at once we have to either restrict the usage of CRTC properties
  * or blend adjustments together.
  *
- * Returns 0 on success.
+ * Returns:
+ * 0 on success.
+ * Error code if setup fails.
  */
 int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc)
 {
@@ -373,7 +427,7 @@ int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc)
 
 	/* Setup regamma and degamma. */
 	if (is_legacy) {
-		/*
+		/**
 		 * Legacy regamma forces us to use the sRGB RGM as a base.
 		 * This also means we can't use linear DGM since DGM needs
 		 * to use sRGB as a base as well, resulting in incorrect CRTC
@@ -393,7 +447,8 @@ int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc)
 		if (r)
 			return r;
 	} else if (has_regamma) {
-		/* CRTC RGM goes into RGM LUT. */
+		/**
+		 * If atomic regamma, CRTC RGM goes into RGM LUT. */
 		stream->out_transfer_func->type = TF_TYPE_DISTRIBUTED_POINTS;
 		stream->out_transfer_func->tf = TRANSFER_FUNCTION_LINEAR;
 
@@ -402,7 +457,7 @@ int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc)
 		if (r)
 			return r;
 	} else {
-		/*
+		/**
 		 * No CRTC RGM means we can just put the block into bypass
 		 * since we don't have any plane level adjustments using it.
 		 */
@@ -410,7 +465,7 @@ int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc)
 		stream->out_transfer_func->tf = TRANSFER_FUNCTION_LINEAR;
 	}
 
-	/*
+	/**
 	 * CRTC DGM goes into DGM LUT. It would be nice to place it
 	 * into the RGM since it's a more featured block but we'd
 	 * have to place the CTM in the OCSC in that case.
@@ -421,7 +476,7 @@ int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc)
 	if (crtc->base.ctm) {
 		ctm = (struct drm_color_ctm *)crtc->base.ctm->data;
 
-		/*
+		/**
 		 * Gamut remapping must be used for gamma correction
 		 * since it comes before the regamma correction.
 		 *
@@ -452,7 +507,9 @@ int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc)
  * preparation for hardware commit. The transfer function used depends on
  * the prepartion done on the stream for color management.
  *
- * Returns 0 on success.
+ * Returns:
+ * 0 on success.
+ * ENOMEM if mem allocation fails.
  */
 int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state *crtc,
 				      struct dc_plane_state *dc_plane_state)
-- 
2.35.1

Re: [PATCH 1/4] Documentation/amdgpu_dm: Add DM color correction documentation

[Tales Lelo da Aparecida]

On 16/07/2022 19:25, Melissa Wen wrote:
> AMDGPU DM maps DRM color management properties (degamma, ctm and gamma)
> to DC color correction entities. Part of this mapping is already
> documented as code comments and can be converted as kernel docs.
> 
> v2:
> - rebase to amd-staging-drm-next
> 
> Reviewed-by: Harry Wentland <harry.wentland@amd.com>
> Signed-off-by: Melissa Wen <mwen@igalia.com>
> ---
>   .../gpu/amdgpu/display/display-manager.rst    |   9 ++
>   .../amd/display/amdgpu_dm/amdgpu_dm_color.c   | 121 +++++++++++++-----
>   2 files changed, 98 insertions(+), 32 deletions(-)
> 
> diff --git a/Documentation/gpu/amdgpu/display/display-manager.rst b/Documentation/gpu/amdgpu/display/display-manager.rst
> index 7ce31f89d9a0..b1b0f11aed83 100644
> --- a/Documentation/gpu/amdgpu/display/display-manager.rst
> +++ b/Documentation/gpu/amdgpu/display/display-manager.rst
> @@ -40,3 +40,12 @@ Atomic Implementation
>   
>   .. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
>      :functions: amdgpu_dm_atomic_check amdgpu_dm_atomic_commit_tail
> +
> +Color Management Properties
> +===========================
> +
> +.. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
> +   :doc: overview
> +
> +.. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
> +   :internal:
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
> index a71177305bcd..93c813089bff 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
> @@ -29,7 +29,9 @@
>   #include "modules/color/color_gamma.h"
>   #include "basics/conversion.h"
>   
> -/*
> +/**
> + * DOC: overview
> + *
>    * The DC interface to HW gives us the following color management blocks
>    * per pipe (surface):
>    *
> @@ -71,8 +73,8 @@
>   
>   #define MAX_DRM_LUT_VALUE 0xFFFF
>   
> -/*
> - * Initialize the color module.
> +/**
> + * amdgpu_dm_init_color_mod - Initialize the color module.
>    *
>    * We're not using the full color module, only certain components.
>    * Only call setup functions for components that we need.
> @@ -82,7 +84,14 @@ void amdgpu_dm_init_color_mod(void)
>   	setup_x_points_distribution();
>   }
>   
> -/* Extracts the DRM lut and lut size from a blob. */
> +/**
> + * __extract_blob_lut - Extracts the DRM lut and lut size from a blob.
> + * @blob: DRM color mgmt property blob
> + * @size: lut size
> + *
> + * Returns:
> + * DRM LUT or NULL
> + */
>   static const struct drm_color_lut *
>   __extract_blob_lut(const struct drm_property_blob *blob, uint32_t *size)
>   {
> @@ -90,13 +99,18 @@ __extract_blob_lut(const struct drm_property_blob *blob, uint32_t *size)
>   	return blob ? (struct drm_color_lut *)blob->data : NULL;
>   }

I don't think everyone would approve using actual kernel-doc for these 
static functions, but I can appreciate they being formatted as such.
Consider replacing /** with /*.

> -/*
> - * Return true if the given lut is a linear mapping of values, i.e. it acts
> - * like a bypass LUT.
> +/**
> + * __is_lut_linear - check if the given lut is a linear mapping of values
> + * @lut: given lut to check values
> + * @size: lut size
>    *
>    * It is considered linear if the lut represents:
> - * f(a) = (0xFF00/MAX_COLOR_LUT_ENTRIES-1)a; for integer a in
> - *                                           [0, MAX_COLOR_LUT_ENTRIES)
> + * f(a) = (0xFF00/MAX_COLOR_LUT_ENTRIES-1)a; for integer a in [0,
> + * MAX_COLOR_LUT_ENTRIES)
> + *
> + * Returns:
> + * True if the given lut is a linear mapping of values, i.e. it acts like a
> + * bypass LUT. Otherwise, false.
>    */
>   static bool __is_lut_linear(const struct drm_color_lut *lut, uint32_t size)
>   {
> @@ -119,9 +133,13 @@ static bool __is_lut_linear(const struct drm_color_lut *lut, uint32_t size)
>   	return true;
>   }
>   
> -/*
> - * Convert the drm_color_lut to dc_gamma. The conversion depends on the size
> - * of the lut - whether or not it's legacy.
> +/**
> + * __drm_lut_to_dc_gamma - convert the drm_color_lut to dc_gamma.
> + * @lut: DRM lookup table for color conversion
> + * @gamma: DC gamma to set entries
> + * @is_legacy: legacy or atomic gamma
> + *
> + * The conversion depends on the size of the lut - whether or not it's legacy.
>    */
>   static void __drm_lut_to_dc_gamma(const struct drm_color_lut *lut,
>   				  struct dc_gamma *gamma, bool is_legacy)
> @@ -154,8 +172,11 @@ static void __drm_lut_to_dc_gamma(const struct drm_color_lut *lut,
>   	}
>   }
>   
> -/*
> - * Converts a DRM CTM to a DC CSC float matrix.
> +/**
> + * __drm_ctm_to_dc_matrix - converts a DRM CTM to a DC CSC float matrix
> + * @ctm: DRM color transformation matrix
> + * @matrix: DC CSC float matrix
> + *
>    * The matrix needs to be a 3x4 (12 entry) matrix.
>    */
>   static void __drm_ctm_to_dc_matrix(const struct drm_color_ctm *ctm,
> @@ -189,7 +210,18 @@ static void __drm_ctm_to_dc_matrix(const struct drm_color_ctm *ctm,
>   	}
>   }
>   
> -/* Calculates the legacy transfer function - only for sRGB input space. */
> +/**
> + * __set_legacy_tf - Calculates the legacy transfer function
> + * @func: transfer function
> + * @lut: lookup table that defines the color space
> + * @lut_size: size of respective lut
> + * @has_rom: if ROM can be used for hardcoded curve
> + *
> + * Only for sRGB input space
> + *
> + * Returns:
> + * 0 in case of sucess, -ENOMEM if fails

Typo sucess -> success

> + */
>   static int __set_legacy_tf(struct dc_transfer_func *func,
>   			   const struct drm_color_lut *lut, uint32_t lut_size,
>   			   bool has_rom)
> @@ -218,7 +250,16 @@ static int __set_legacy_tf(struct dc_transfer_func *func,
>   	return res ? 0 : -ENOMEM;
>   }
>   
> -/* Calculates the output transfer function based on expected input space. */
> +/**
> + * __set_output_tf - calculates the output transfer function based on expected input space.
> + * @func: transfer function
> + * @lut: lookup table that defines the color space
> + * @lut_size: size of respective lut
> + * @has_rom: if ROM can be used for hardcoded curve
> + *
> + * Returns:
> + * 0 in case of success. -ENOMEM if fails.
> + */
>   static int __set_output_tf(struct dc_transfer_func *func,
>   			   const struct drm_color_lut *lut, uint32_t lut_size,
>   			   bool has_rom)
> @@ -239,7 +280,7 @@ static int __set_output_tf(struct dc_transfer_func *func,
>   	__drm_lut_to_dc_gamma(lut, gamma, false);
>   
>   	if (func->tf == TRANSFER_FUNCTION_LINEAR) {
> -		/*
> +		/**

I don't think kernel-doc should be used inside functions, as well,
maybe keep the "/*" from before. This occurs in more places in this 
patch, remember to replace them as well, if you concur.

>   		 * Color module doesn't like calculating regamma params
>   		 * on top of a linear input. But degamma params can be used
>   		 * instead to simulate this.
> @@ -262,7 +303,16 @@ static int __set_output_tf(struct dc_transfer_func *func,
>   	return res ? 0 : -ENOMEM;
>   }
>   
> -/* Caculates the input transfer function based on expected input space. */
> +/**
> + * __set_input_tf - calculates the input transfer function based on expected
> + * input space.
> + * @func: transfer function
> + * @lut: lookup table that defines the color space
> + * @lut_size: size of respective lut.
> + *
> + * Returns:
> + * 0 in case of success. -ENOMEM if fails.
> + */
>   static int __set_input_tf(struct dc_transfer_func *func,
>   			  const struct drm_color_lut *lut, uint32_t lut_size)
>   {
> @@ -285,13 +335,15 @@ static int __set_input_tf(struct dc_transfer_func *func,
>   }
>   
>   /**
> - * amdgpu_dm_verify_lut_sizes
> + * amdgpu_dm_verify_lut_sizes - verifies if DRM luts match the hw supported sizes
>    * @crtc_state: the DRM CRTC state
>    *
> - * Verifies that the Degamma and Gamma LUTs attached to the |crtc_state| are of
> - * the expected size.
> + * Verifies that the Degamma and Gamma LUTs attached to the &crtc_state
> + * are of the expected size.
>    *
> - * Returns 0 on success.
> + * Returns:
> + * 0 on success.
> + * -EINVAL if any lut sizes are invalid.

I don't know if you expect this to be rendered in two lines, given that 
you wrote something equivalent in a single line in other docstrings 
above, but if you do, use instead:
```
* * 0 on success.
* * -EINVAL if any lut sizes are invalid.
```
As described at: 
https://www.kernel.org/doc/html/latest/doc-guide/kernel-doc.html#return-values

>    */
>   int amdgpu_dm_verify_lut_sizes(const struct drm_crtc_state *crtc_state)
>   {
> @@ -327,9 +379,9 @@ int amdgpu_dm_verify_lut_sizes(const struct drm_crtc_state *crtc_state)
>    * of the HW blocks as long as the CRTC CTM always comes before the
>    * CRTC RGM and after the CRTC DGM.
>    *
> - * The CRTC RGM block will be placed in the RGM LUT block if it is non-linear.
> - * The CRTC DGM block will be placed in the DGM LUT block if it is non-linear.
> - * The CRTC CTM will be placed in the gamut remap block if it is non-linear.
> + * * The CRTC RGM block will be placed in the RGM LUT block if it is non-linear.
> + * * The CRTC DGM block will be placed in the DGM LUT block if it is non-linear.
> + * * The CRTC CTM will be placed in the gamut remap block if it is non-linear.
>    *
>    * The RGM block is typically more fully featured and accurate across
>    * all ASICs - DCE can't support a custom non-linear CRTC DGM.
> @@ -338,7 +390,9 @@ int amdgpu_dm_verify_lut_sizes(const struct drm_crtc_state *crtc_state)
>    * management at once we have to either restrict the usage of CRTC properties
>    * or blend adjustments together.
>    *
> - * Returns 0 on success.
> + * Returns:
> + * 0 on success.
> + * Error code if setup fails.
>    */
>   int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc)
>   {
> @@ -373,7 +427,7 @@ int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc)
>   
>   	/* Setup regamma and degamma. */
>   	if (is_legacy) {
> -		/*
> +		/**
>   		 * Legacy regamma forces us to use the sRGB RGM as a base.
>   		 * This also means we can't use linear DGM since DGM needs
>   		 * to use sRGB as a base as well, resulting in incorrect CRTC
> @@ -393,7 +447,8 @@ int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc)
>   		if (r)
>   			return r;
>   	} else if (has_regamma) {
> -		/* CRTC RGM goes into RGM LUT. */
> +		/**
> +		 * If atomic regamma, CRTC RGM goes into RGM LUT. */
>   		stream->out_transfer_func->type = TF_TYPE_DISTRIBUTED_POINTS;
>   		stream->out_transfer_func->tf = TRANSFER_FUNCTION_LINEAR;
>   
> @@ -402,7 +457,7 @@ int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc)
>   		if (r)
>   			return r;
>   	} else {
> -		/*
> +		/**
>   		 * No CRTC RGM means we can just put the block into bypass
>   		 * since we don't have any plane level adjustments using it.
>   		 */
> @@ -410,7 +465,7 @@ int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc)
>   		stream->out_transfer_func->tf = TRANSFER_FUNCTION_LINEAR;
>   	}
>   
> -	/*
> +	/**
>   	 * CRTC DGM goes into DGM LUT. It would be nice to place it
>   	 * into the RGM since it's a more featured block but we'd
>   	 * have to place the CTM in the OCSC in that case.
> @@ -421,7 +476,7 @@ int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc)
>   	if (crtc->base.ctm) {
>   		ctm = (struct drm_color_ctm *)crtc->base.ctm->data;
>   
> -		/*
> +		/**
>   		 * Gamut remapping must be used for gamma correction
>   		 * since it comes before the regamma correction.
>   		 *
> @@ -452,7 +507,9 @@ int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc)
>    * preparation for hardware commit. The transfer function used depends on
>    * the prepartion done on the stream for color management.

Could you fix this typo while you are here? prepartion -> preparation

>    *
> - * Returns 0 on success.
> + * Returns:
> + * 0 on success.
> + * ENOMEM if mem allocation fails.
>    */
>   int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state *crtc,
>   				      struct dc_plane_state *dc_plane_state)

Thanks for creating more documentation!

Kind regards,
Tales

Re: [PATCH 1/4] Documentation/amdgpu_dm: Add DM color correction documentation

[Melissa Wen]

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On 07/17, Tales Lelo da Aparecida wrote:
> On 16/07/2022 19:25, Melissa Wen wrote:
> > AMDGPU DM maps DRM color management properties (degamma, ctm and gamma)
> > to DC color correction entities. Part of this mapping is already
> > documented as code comments and can be converted as kernel docs.
> > 
> > v2:
> > - rebase to amd-staging-drm-next
> > 
> > Reviewed-by: Harry Wentland <harry.wentland@amd.com>
> > Signed-off-by: Melissa Wen <mwen@igalia.com>
> > ---
> >   .../gpu/amdgpu/display/display-manager.rst    |   9 ++
> >   .../amd/display/amdgpu_dm/amdgpu_dm_color.c   | 121 +++++++++++++-----
> >   2 files changed, 98 insertions(+), 32 deletions(-)
> > 
> > diff --git a/Documentation/gpu/amdgpu/display/display-manager.rst b/Documentation/gpu/amdgpu/display/display-manager.rst
> > index 7ce31f89d9a0..b1b0f11aed83 100644
> > --- a/Documentation/gpu/amdgpu/display/display-manager.rst
> > +++ b/Documentation/gpu/amdgpu/display/display-manager.rst
> > @@ -40,3 +40,12 @@ Atomic Implementation
> >   .. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> >      :functions: amdgpu_dm_atomic_check amdgpu_dm_atomic_commit_tail
> > +
> > +Color Management Properties
> > +===========================
> > +
> > +.. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
> > +   :doc: overview
> > +
> > +.. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
> > +   :internal:
> > diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
> > index a71177305bcd..93c813089bff 100644
> > --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
> > +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
> > @@ -29,7 +29,9 @@
> >   #include "modules/color/color_gamma.h"
> >   #include "basics/conversion.h"
> > -/*
> > +/**
> > + * DOC: overview
> > + *
> >    * The DC interface to HW gives us the following color management blocks
> >    * per pipe (surface):
> >    *
> > @@ -71,8 +73,8 @@
> >   #define MAX_DRM_LUT_VALUE 0xFFFF
> > -/*
> > - * Initialize the color module.
> > +/**
> > + * amdgpu_dm_init_color_mod - Initialize the color module.
> >    *
> >    * We're not using the full color module, only certain components.
> >    * Only call setup functions for components that we need.
> > @@ -82,7 +84,14 @@ void amdgpu_dm_init_color_mod(void)
> >   	setup_x_points_distribution();
> >   }
> > -/* Extracts the DRM lut and lut size from a blob. */
> > +/**
> > + * __extract_blob_lut - Extracts the DRM lut and lut size from a blob.
> > + * @blob: DRM color mgmt property blob
> > + * @size: lut size
> > + *
> > + * Returns:
> > + * DRM LUT or NULL
> > + */
> >   static const struct drm_color_lut *
> >   __extract_blob_lut(const struct drm_property_blob *blob, uint32_t *size)
> >   {
> > @@ -90,13 +99,18 @@ __extract_blob_lut(const struct drm_property_blob *blob, uint32_t *size)
> >   	return blob ? (struct drm_color_lut *)blob->data : NULL;
> >   }
> 
> I don't think everyone would approve using actual kernel-doc for these
> static functions, but I can appreciate they being formatted as such.
> Consider replacing /** with /*.

IMHO, although they are static, they provide info to understand the AMD
DM programming of DRM color correction properties. I see the value for
external contributors, but I'm not sure about kernel-doc rules about it.

> 
> > -/*
> > - * Return true if the given lut is a linear mapping of values, i.e. it acts
> > - * like a bypass LUT.
> > +/**
> > + * __is_lut_linear - check if the given lut is a linear mapping of values
> > + * @lut: given lut to check values
> > + * @size: lut size
> >    *
> >    * It is considered linear if the lut represents:
> > - * f(a) = (0xFF00/MAX_COLOR_LUT_ENTRIES-1)a; for integer a in
> > - *                                           [0, MAX_COLOR_LUT_ENTRIES)
> > + * f(a) = (0xFF00/MAX_COLOR_LUT_ENTRIES-1)a; for integer a in [0,
> > + * MAX_COLOR_LUT_ENTRIES)
> > + *
> > + * Returns:
> > + * True if the given lut is a linear mapping of values, i.e. it acts like a
> > + * bypass LUT. Otherwise, false.
> >    */
> >   static bool __is_lut_linear(const struct drm_color_lut *lut, uint32_t size)
> >   {
> > @@ -119,9 +133,13 @@ static bool __is_lut_linear(const struct drm_color_lut *lut, uint32_t size)
> >   	return true;
> >   }
> > -/*
> > - * Convert the drm_color_lut to dc_gamma. The conversion depends on the size
> > - * of the lut - whether or not it's legacy.
> > +/**
> > + * __drm_lut_to_dc_gamma - convert the drm_color_lut to dc_gamma.
> > + * @lut: DRM lookup table for color conversion
> > + * @gamma: DC gamma to set entries
> > + * @is_legacy: legacy or atomic gamma
> > + *
> > + * The conversion depends on the size of the lut - whether or not it's legacy.
> >    */
> >   static void __drm_lut_to_dc_gamma(const struct drm_color_lut *lut,
> >   				  struct dc_gamma *gamma, bool is_legacy)
> > @@ -154,8 +172,11 @@ static void __drm_lut_to_dc_gamma(const struct drm_color_lut *lut,
> >   	}
> >   }
> > -/*
> > - * Converts a DRM CTM to a DC CSC float matrix.
> > +/**
> > + * __drm_ctm_to_dc_matrix - converts a DRM CTM to a DC CSC float matrix
> > + * @ctm: DRM color transformation matrix
> > + * @matrix: DC CSC float matrix
> > + *
> >    * The matrix needs to be a 3x4 (12 entry) matrix.
> >    */
> >   static void __drm_ctm_to_dc_matrix(const struct drm_color_ctm *ctm,
> > @@ -189,7 +210,18 @@ static void __drm_ctm_to_dc_matrix(const struct drm_color_ctm *ctm,
> >   	}
> >   }
> > -/* Calculates the legacy transfer function - only for sRGB input space. */
> > +/**
> > + * __set_legacy_tf - Calculates the legacy transfer function
> > + * @func: transfer function
> > + * @lut: lookup table that defines the color space
> > + * @lut_size: size of respective lut
> > + * @has_rom: if ROM can be used for hardcoded curve
> > + *
> > + * Only for sRGB input space
> > + *
> > + * Returns:
> > + * 0 in case of sucess, -ENOMEM if fails
> 
> Typo sucess -> success
> 
> > + */
> >   static int __set_legacy_tf(struct dc_transfer_func *func,
> >   			   const struct drm_color_lut *lut, uint32_t lut_size,
> >   			   bool has_rom)
> > @@ -218,7 +250,16 @@ static int __set_legacy_tf(struct dc_transfer_func *func,
> >   	return res ? 0 : -ENOMEM;
> >   }
> > -/* Calculates the output transfer function based on expected input space. */
> > +/**
> > + * __set_output_tf - calculates the output transfer function based on expected input space.
> > + * @func: transfer function
> > + * @lut: lookup table that defines the color space
> > + * @lut_size: size of respective lut
> > + * @has_rom: if ROM can be used for hardcoded curve
> > + *
> > + * Returns:
> > + * 0 in case of success. -ENOMEM if fails.
> > + */
> >   static int __set_output_tf(struct dc_transfer_func *func,
> >   			   const struct drm_color_lut *lut, uint32_t lut_size,
> >   			   bool has_rom)
> > @@ -239,7 +280,7 @@ static int __set_output_tf(struct dc_transfer_func *func,
> >   	__drm_lut_to_dc_gamma(lut, gamma, false);
> >   	if (func->tf == TRANSFER_FUNCTION_LINEAR) {
> > -		/*
> > +		/**
> 
> I don't think kernel-doc should be used inside functions, as well,
> maybe keep the "/*" from before. This occurs in more places in this patch,
> remember to replace them as well, if you concur.

hmm.. I think inline doc is good to avoid repetitions, at the same time we
expose this info and keep it near its context in the code. This is why I
chose this path.. I'll think about it.

> 
> >   		 * Color module doesn't like calculating regamma params
> >   		 * on top of a linear input. But degamma params can be used
> >   		 * instead to simulate this.
> > @@ -262,7 +303,16 @@ static int __set_output_tf(struct dc_transfer_func *func,
> >   	return res ? 0 : -ENOMEM;
> >   }
> > -/* Caculates the input transfer function based on expected input space. */
> > +/**
> > + * __set_input_tf - calculates the input transfer function based on expected
> > + * input space.
> > + * @func: transfer function
> > + * @lut: lookup table that defines the color space
> > + * @lut_size: size of respective lut.
> > + *
> > + * Returns:
> > + * 0 in case of success. -ENOMEM if fails.
> > + */
> >   static int __set_input_tf(struct dc_transfer_func *func,
> >   			  const struct drm_color_lut *lut, uint32_t lut_size)
> >   {
> > @@ -285,13 +335,15 @@ static int __set_input_tf(struct dc_transfer_func *func,
> >   }
> >   /**
> > - * amdgpu_dm_verify_lut_sizes
> > + * amdgpu_dm_verify_lut_sizes - verifies if DRM luts match the hw supported sizes
> >    * @crtc_state: the DRM CRTC state
> >    *
> > - * Verifies that the Degamma and Gamma LUTs attached to the |crtc_state| are of
> > - * the expected size.
> > + * Verifies that the Degamma and Gamma LUTs attached to the &crtc_state
> > + * are of the expected size.
> >    *
> > - * Returns 0 on success.
> > + * Returns:
> > + * 0 on success.
> > + * -EINVAL if any lut sizes are invalid.
> 
> I don't know if you expect this to be rendered in two lines, given that you
> wrote something equivalent in a single line in other docstrings above, but
> if you do, use instead:
> ```
> * * 0 on success.
> * * -EINVAL if any lut sizes are invalid.
> ```
> As described at: https://www.kernel.org/doc/html/latest/doc-guide/kernel-doc.html#return-values

I expected they are in the same line, separated by dot. I'll put the
together for clarity.

Thanks,

Melissa
> 
> >    */
> >   int amdgpu_dm_verify_lut_sizes(const struct drm_crtc_state *crtc_state)
> >   {
> > @@ -327,9 +379,9 @@ int amdgpu_dm_verify_lut_sizes(const struct drm_crtc_state *crtc_state)
> >    * of the HW blocks as long as the CRTC CTM always comes before the
> >    * CRTC RGM and after the CRTC DGM.
> >    *
> > - * The CRTC RGM block will be placed in the RGM LUT block if it is non-linear.
> > - * The CRTC DGM block will be placed in the DGM LUT block if it is non-linear.
> > - * The CRTC CTM will be placed in the gamut remap block if it is non-linear.
> > + * * The CRTC RGM block will be placed in the RGM LUT block if it is non-linear.
> > + * * The CRTC DGM block will be placed in the DGM LUT block if it is non-linear.
> > + * * The CRTC CTM will be placed in the gamut remap block if it is non-linear.
> >    *
> >    * The RGM block is typically more fully featured and accurate across
> >    * all ASICs - DCE can't support a custom non-linear CRTC DGM.
> > @@ -338,7 +390,9 @@ int amdgpu_dm_verify_lut_sizes(const struct drm_crtc_state *crtc_state)
> >    * management at once we have to either restrict the usage of CRTC properties
> >    * or blend adjustments together.
> >    *
> > - * Returns 0 on success.
> > + * Returns:
> > + * 0 on success.
> > + * Error code if setup fails.
> >    */
> >   int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc)
> >   {
> > @@ -373,7 +427,7 @@ int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc)
> >   	/* Setup regamma and degamma. */
> >   	if (is_legacy) {
> > -		/*
> > +		/**
> >   		 * Legacy regamma forces us to use the sRGB RGM as a base.
> >   		 * This also means we can't use linear DGM since DGM needs
> >   		 * to use sRGB as a base as well, resulting in incorrect CRTC
> > @@ -393,7 +447,8 @@ int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc)
> >   		if (r)
> >   			return r;
> >   	} else if (has_regamma) {
> > -		/* CRTC RGM goes into RGM LUT. */
> > +		/**
> > +		 * If atomic regamma, CRTC RGM goes into RGM LUT. */
> >   		stream->out_transfer_func->type = TF_TYPE_DISTRIBUTED_POINTS;
> >   		stream->out_transfer_func->tf = TRANSFER_FUNCTION_LINEAR;
> > @@ -402,7 +457,7 @@ int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc)
> >   		if (r)
> >   			return r;
> >   	} else {
> > -		/*
> > +		/**
> >   		 * No CRTC RGM means we can just put the block into bypass
> >   		 * since we don't have any plane level adjustments using it.
> >   		 */
> > @@ -410,7 +465,7 @@ int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc)
> >   		stream->out_transfer_func->tf = TRANSFER_FUNCTION_LINEAR;
> >   	}
> > -	/*
> > +	/**
> >   	 * CRTC DGM goes into DGM LUT. It would be nice to place it
> >   	 * into the RGM since it's a more featured block but we'd
> >   	 * have to place the CTM in the OCSC in that case.
> > @@ -421,7 +476,7 @@ int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc)
> >   	if (crtc->base.ctm) {
> >   		ctm = (struct drm_color_ctm *)crtc->base.ctm->data;
> > -		/*
> > +		/**
> >   		 * Gamut remapping must be used for gamma correction
> >   		 * since it comes before the regamma correction.
> >   		 *
> > @@ -452,7 +507,9 @@ int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc)
> >    * preparation for hardware commit. The transfer function used depends on
> >    * the prepartion done on the stream for color management.
> 
> Could you fix this typo while you are here? prepartion -> preparation
> 
> >    *
> > - * Returns 0 on success.
> > + * Returns:
> > + * 0 on success.
> > + * ENOMEM if mem allocation fails.
> >    */
> >   int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state *crtc,
> >   				      struct dc_plane_state *dc_plane_state)
> 
> Thanks for creating more documentation!
> 
> Kind regards,
> Tales

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Re: [PATCH 1/4] Documentation/amdgpu_dm: Add DM color correction documentation

[Rodrigo Siqueira Jordao]

On 2022-07-20 18:54, Melissa Wen wrote:
> On 07/17, Tales Lelo da Aparecida wrote:
>> On 16/07/2022 19:25, Melissa Wen wrote:
>>> AMDGPU DM maps DRM color management properties (degamma, ctm and gamma)
>>> to DC color correction entities. Part of this mapping is already
>>> documented as code comments and can be converted as kernel docs.
>>>
>>> v2:
>>> - rebase to amd-staging-drm-next
>>>
>>> Reviewed-by: Harry Wentland <harry.wentland@amd.com>
>>> Signed-off-by: Melissa Wen <mwen@igalia.com>
>>> ---
>>>    .../gpu/amdgpu/display/display-manager.rst    |   9 ++
>>>    .../amd/display/amdgpu_dm/amdgpu_dm_color.c   | 121 +++++++++++++-----
>>>    2 files changed, 98 insertions(+), 32 deletions(-)
>>>
>>> diff --git a/Documentation/gpu/amdgpu/display/display-manager.rst b/Documentation/gpu/amdgpu/display/display-manager.rst
>>> index 7ce31f89d9a0..b1b0f11aed83 100644
>>> --- a/Documentation/gpu/amdgpu/display/display-manager.rst
>>> +++ b/Documentation/gpu/amdgpu/display/display-manager.rst
>>> @@ -40,3 +40,12 @@ Atomic Implementation
>>>    .. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
>>>       :functions: amdgpu_dm_atomic_check amdgpu_dm_atomic_commit_tail
>>> +
>>> +Color Management Properties
>>> +===========================
>>> +
>>> +.. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
>>> +   :doc: overview
>>> +
>>> +.. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
>>> +   :internal:
>>> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
>>> index a71177305bcd..93c813089bff 100644
>>> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
>>> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
>>> @@ -29,7 +29,9 @@
>>>    #include "modules/color/color_gamma.h"
>>>    #include "basics/conversion.h"
>>> -/*
>>> +/**
>>> + * DOC: overview
>>> + *
>>>     * The DC interface to HW gives us the following color management blocks
>>>     * per pipe (surface):
>>>     *
>>> @@ -71,8 +73,8 @@
>>>    #define MAX_DRM_LUT_VALUE 0xFFFF
>>> -/*
>>> - * Initialize the color module.
>>> +/**
>>> + * amdgpu_dm_init_color_mod - Initialize the color module.
>>>     *
>>>     * We're not using the full color module, only certain components.
>>>     * Only call setup functions for components that we need.
>>> @@ -82,7 +84,14 @@ void amdgpu_dm_init_color_mod(void)
>>>    	setup_x_points_distribution();
>>>    }
>>> -/* Extracts the DRM lut and lut size from a blob. */
>>> +/**
>>> + * __extract_blob_lut - Extracts the DRM lut and lut size from a blob.
>>> + * @blob: DRM color mgmt property blob
>>> + * @size: lut size
>>> + *
>>> + * Returns:
>>> + * DRM LUT or NULL
>>> + */
>>>    static const struct drm_color_lut *
>>>    __extract_blob_lut(const struct drm_property_blob *blob, uint32_t *size)
>>>    {
>>> @@ -90,13 +99,18 @@ __extract_blob_lut(const struct drm_property_blob *blob, uint32_t *size)
>>>    	return blob ? (struct drm_color_lut *)blob->data : NULL;
>>>    }
>>
>> I don't think everyone would approve using actual kernel-doc for these
>> static functions, but I can appreciate they being formatted as such.
>> Consider replacing /** with /*.
> 
> IMHO, although they are static, they provide info to understand the AMD
> DM programming of DRM color correction properties. I see the value for
> external contributors, but I'm not sure about kernel-doc rules about it.

Yeah... I agree, I don't mind seeing kernel-doc for some static 
functions. Iirc, DRM documentation also documents some static functions.

>>
>>> -/*
>>> - * Return true if the given lut is a linear mapping of values, i.e. it acts
>>> - * like a bypass LUT.
>>> +/**
>>> + * __is_lut_linear - check if the given lut is a linear mapping of values
>>> + * @lut: given lut to check values
>>> + * @size: lut size
>>>     *
>>>     * It is considered linear if the lut represents:
>>> - * f(a) = (0xFF00/MAX_COLOR_LUT_ENTRIES-1)a; for integer a in
>>> - *                                           [0, MAX_COLOR_LUT_ENTRIES)
>>> + * f(a) = (0xFF00/MAX_COLOR_LUT_ENTRIES-1)a; for integer a in [0,
>>> + * MAX_COLOR_LUT_ENTRIES)
>>> + *
>>> + * Returns:
>>> + * True if the given lut is a linear mapping of values, i.e. it acts like a
>>> + * bypass LUT. Otherwise, false.
>>>     */
>>>    static bool __is_lut_linear(const struct drm_color_lut *lut, uint32_t size)
>>>    {
>>> @@ -119,9 +133,13 @@ static bool __is_lut_linear(const struct drm_color_lut *lut, uint32_t size)
>>>    	return true;
>>>    }
>>> -/*
>>> - * Convert the drm_color_lut to dc_gamma. The conversion depends on the size
>>> - * of the lut - whether or not it's legacy.
>>> +/**
>>> + * __drm_lut_to_dc_gamma - convert the drm_color_lut to dc_gamma.
>>> + * @lut: DRM lookup table for color conversion
>>> + * @gamma: DC gamma to set entries
>>> + * @is_legacy: legacy or atomic gamma
>>> + *
>>> + * The conversion depends on the size of the lut - whether or not it's legacy.
>>>     */
>>>    static void __drm_lut_to_dc_gamma(const struct drm_color_lut *lut,
>>>    				  struct dc_gamma *gamma, bool is_legacy)
>>> @@ -154,8 +172,11 @@ static void __drm_lut_to_dc_gamma(const struct drm_color_lut *lut,
>>>    	}
>>>    }
>>> -/*
>>> - * Converts a DRM CTM to a DC CSC float matrix.
>>> +/**
>>> + * __drm_ctm_to_dc_matrix - converts a DRM CTM to a DC CSC float matrix
>>> + * @ctm: DRM color transformation matrix
>>> + * @matrix: DC CSC float matrix
>>> + *
>>>     * The matrix needs to be a 3x4 (12 entry) matrix.
>>>     */
>>>    static void __drm_ctm_to_dc_matrix(const struct drm_color_ctm *ctm,
>>> @@ -189,7 +210,18 @@ static void __drm_ctm_to_dc_matrix(const struct drm_color_ctm *ctm,
>>>    	}
>>>    }
>>> -/* Calculates the legacy transfer function - only for sRGB input space. */
>>> +/**
>>> + * __set_legacy_tf - Calculates the legacy transfer function
>>> + * @func: transfer function
>>> + * @lut: lookup table that defines the color space
>>> + * @lut_size: size of respective lut
>>> + * @has_rom: if ROM can be used for hardcoded curve
>>> + *
>>> + * Only for sRGB input space
>>> + *
>>> + * Returns:
>>> + * 0 in case of sucess, -ENOMEM if fails
>>
>> Typo sucess -> success
>>
>>> + */
>>>    static int __set_legacy_tf(struct dc_transfer_func *func,
>>>    			   const struct drm_color_lut *lut, uint32_t lut_size,
>>>    			   bool has_rom)
>>> @@ -218,7 +250,16 @@ static int __set_legacy_tf(struct dc_transfer_func *func,
>>>    	return res ? 0 : -ENOMEM;
>>>    }
>>> -/* Calculates the output transfer function based on expected input space. */
>>> +/**
>>> + * __set_output_tf - calculates the output transfer function based on expected input space.
>>> + * @func: transfer function
>>> + * @lut: lookup table that defines the color space
>>> + * @lut_size: size of respective lut
>>> + * @has_rom: if ROM can be used for hardcoded curve
>>> + *
>>> + * Returns:
>>> + * 0 in case of success. -ENOMEM if fails.
>>> + */
>>>    static int __set_output_tf(struct dc_transfer_func *func,
>>>    			   const struct drm_color_lut *lut, uint32_t lut_size,
>>>    			   bool has_rom)
>>> @@ -239,7 +280,7 @@ static int __set_output_tf(struct dc_transfer_func *func,
>>>    	__drm_lut_to_dc_gamma(lut, gamma, false);
>>>    	if (func->tf == TRANSFER_FUNCTION_LINEAR) {
>>> -		/*
>>> +		/**
>>
>> I don't think kernel-doc should be used inside functions, as well,
>> maybe keep the "/*" from before. This occurs in more places in this patch,
>> remember to replace them as well, if you concur.
> 
> hmm.. I think inline doc is good to avoid repetitions, at the same time we
> expose this info and keep it near its context in the code. This is why I
> chose this path.. I'll think about it

I'm not sure, but I think that kernel-doc inside a function is ignored. 
In that case, I would follow the kernel guideline for code comments. 
Maybe you can move part of this documentation to the function description?

Btw, nice patch!

Thanks
Siqueira

>>
>>>    		 * Color module doesn't like calculating regamma params
>>>    		 * on top of a linear input. But degamma params can be used
>>>    		 * instead to simulate this.
>>> @@ -262,7 +303,16 @@ static int __set_output_tf(struct dc_transfer_func *func,
>>>    	return res ? 0 : -ENOMEM;
>>>    }
>>> -/* Caculates the input transfer function based on expected input space. */
>>> +/**
>>> + * __set_input_tf - calculates the input transfer function based on expected
>>> + * input space.
>>> + * @func: transfer function
>>> + * @lut: lookup table that defines the color space
>>> + * @lut_size: size of respective lut.
>>> + *
>>> + * Returns:
>>> + * 0 in case of success. -ENOMEM if fails.
>>> + */
>>>    static int __set_input_tf(struct dc_transfer_func *func,
>>>    			  const struct drm_color_lut *lut, uint32_t lut_size)
>>>    {
>>> @@ -285,13 +335,15 @@ static int __set_input_tf(struct dc_transfer_func *func,
>>>    }
>>>    /**
>>> - * amdgpu_dm_verify_lut_sizes
>>> + * amdgpu_dm_verify_lut_sizes - verifies if DRM luts match the hw supported sizes
>>>     * @crtc_state: the DRM CRTC state
>>>     *
>>> - * Verifies that the Degamma and Gamma LUTs attached to the |crtc_state| are of
>>> - * the expected size.
>>> + * Verifies that the Degamma and Gamma LUTs attached to the &crtc_state
>>> + * are of the expected size.
>>>     *
>>> - * Returns 0 on success.
>>> + * Returns:
>>> + * 0 on success.
>>> + * -EINVAL if any lut sizes are invalid.
>>
>> I don't know if you expect this to be rendered in two lines, given that you
>> wrote something equivalent in a single line in other docstrings above, but
>> if you do, use instead:
>> ```
>> * * 0 on success.
>> * * -EINVAL if any lut sizes are invalid.
>> ```
>> As described at: https://www.kernel.org/doc/html/latest/doc-guide/kernel-doc.html#return-values
> 
> I expected they are in the same line, separated by dot. I'll put the
> together for clarity.
> 
> Thanks,
> 
> Melissa
>>
>>>     */
>>>    int amdgpu_dm_verify_lut_sizes(const struct drm_crtc_state *crtc_state)
>>>    {
>>> @@ -327,9 +379,9 @@ int amdgpu_dm_verify_lut_sizes(const struct drm_crtc_state *crtc_state)
>>>     * of the HW blocks as long as the CRTC CTM always comes before the
>>>     * CRTC RGM and after the CRTC DGM.
>>>     *
>>> - * The CRTC RGM block will be placed in the RGM LUT block if it is non-linear.
>>> - * The CRTC DGM block will be placed in the DGM LUT block if it is non-linear.
>>> - * The CRTC CTM will be placed in the gamut remap block if it is non-linear.
>>> + * * The CRTC RGM block will be placed in the RGM LUT block if it is non-linear.
>>> + * * The CRTC DGM block will be placed in the DGM LUT block if it is non-linear.
>>> + * * The CRTC CTM will be placed in the gamut remap block if it is non-linear.
>>>     *
>>>     * The RGM block is typically more fully featured and accurate across
>>>     * all ASICs - DCE can't support a custom non-linear CRTC DGM.
>>> @@ -338,7 +390,9 @@ int amdgpu_dm_verify_lut_sizes(const struct drm_crtc_state *crtc_state)
>>>     * management at once we have to either restrict the usage of CRTC properties
>>>     * or blend adjustments together.
>>>     *
>>> - * Returns 0 on success.
>>> + * Returns:
>>> + * 0 on success.
>>> + * Error code if setup fails.
>>>     */
>>>    int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc)
>>>    {
>>> @@ -373,7 +427,7 @@ int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc)
>>>    	/* Setup regamma and degamma. */
>>>    	if (is_legacy) {
>>> -		/*
>>> +		/**
>>>    		 * Legacy regamma forces us to use the sRGB RGM as a base.
>>>    		 * This also means we can't use linear DGM since DGM needs
>>>    		 * to use sRGB as a base as well, resulting in incorrect CRTC
>>> @@ -393,7 +447,8 @@ int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc)
>>>    		if (r)
>>>    			return r;
>>>    	} else if (has_regamma) {
>>> -		/* CRTC RGM goes into RGM LUT. */
>>> +		/**
>>> +		 * If atomic regamma, CRTC RGM goes into RGM LUT. */
>>>    		stream->out_transfer_func->type = TF_TYPE_DISTRIBUTED_POINTS;
>>>    		stream->out_transfer_func->tf = TRANSFER_FUNCTION_LINEAR;
>>> @@ -402,7 +457,7 @@ int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc)
>>>    		if (r)
>>>    			return r;
>>>    	} else {
>>> -		/*
>>> +		/**
>>>    		 * No CRTC RGM means we can just put the block into bypass
>>>    		 * since we don't have any plane level adjustments using it.
>>>    		 */
>>> @@ -410,7 +465,7 @@ int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc)
>>>    		stream->out_transfer_func->tf = TRANSFER_FUNCTION_LINEAR;
>>>    	}
>>> -	/*
>>> +	/**
>>>    	 * CRTC DGM goes into DGM LUT. It would be nice to place it
>>>    	 * into the RGM since it's a more featured block but we'd
>>>    	 * have to place the CTM in the OCSC in that case.
>>> @@ -421,7 +476,7 @@ int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc)
>>>    	if (crtc->base.ctm) {
>>>    		ctm = (struct drm_color_ctm *)crtc->base.ctm->data;
>>> -		/*
>>> +		/**
>>>    		 * Gamut remapping must be used for gamma correction
>>>    		 * since it comes before the regamma correction.
>>>    		 *
>>> @@ -452,7 +507,9 @@ int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc)
>>>     * preparation for hardware commit. The transfer function used depends on
>>>     * the prepartion done on the stream for color management.
>>
>> Could you fix this typo while you are here? prepartion -> preparation
>>
>>>     *
>>> - * Returns 0 on success.
>>> + * Returns:
>>> + * 0 on success.
>>> + * ENOMEM if mem allocation fails.
>>>     */
>>>    int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state *crtc,
>>>    				      struct dc_plane_state *dc_plane_state)
>>
>> Thanks for creating more documentation!
>>
>> Kind regards,
>> Tales

[PATCH 2/4] Documentation/amdgpu/display: add DC color caps info

[Melissa Wen]

Add details about color correction capabilities and explain a bit about
differences between DC hw generations and also how they are mapped
between DRM and DC interface. Two schemas for DCN 2.0 and 3.0 (converted
to svg from the original png) is included to illustrate it. They were
obtained from a discussion[1] in the amd-gfx mailing list.

[1] https://lore.kernel.org/amd-gfx/20220422142811.dm6vtk6v64jcwydk@mail.igalia.com/

v2:

- remove redundant comments (Harry)
- fix typo (Harry)

Signed-off-by: Melissa Wen <mwen@igalia.com>
---
 .../amdgpu/display/dcn2_cm_drm_current.svg    | 1370 +++++++++++++++
 .../amdgpu/display/dcn3_cm_drm_current.svg    | 1529 +++++++++++++++++
 .../gpu/amdgpu/display/display-manager.rst    |   35 +
 drivers/gpu/drm/amd/display/dc/dc.h           |   74 +-
 4 files changed, 2995 insertions(+), 13 deletions(-)
 create mode 100644 Documentation/gpu/amdgpu/display/dcn2_cm_drm_current.svg
 create mode 100644 Documentation/gpu/amdgpu/display/dcn3_cm_drm_current.svg

diff --git a/Documentation/gpu/amdgpu/display/dcn2_cm_drm_current.svg b/Documentation/gpu/amdgpu/display/dcn2_cm_drm_current.svg
new file mode 100644
index 000000000000..315ffc5a1a4b
--- /dev/null
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diff --git a/Documentation/gpu/amdgpu/display/display-manager.rst b/Documentation/gpu/amdgpu/display/display-manager.rst
index b1b0f11aed83..8960a5f1fa66 100644
--- a/Documentation/gpu/amdgpu/display/display-manager.rst
+++ b/Documentation/gpu/amdgpu/display/display-manager.rst
@@ -49,3 +49,38 @@ Color Management Properties
 
 .. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
    :internal:
+
+
+DC Color Capabilities between DCN generations
+---------------------------------------------
+
+DRM/KMS framework defines three CRTC color correction properties: degamma,
+color transformation matrix (ctm) and gamma, and two properties for degamma and
+gamma lut sizes. AMD DC programs some of the color correction features
+pre-blending but DRM/KMS has not per-plane color correction properties.
+
+What's possible to do before and after blending has changed quite a bit between
+DCN generations as it depends on hardware color capabilities. DPP and MPC color
+correction caps are described below.
+
+.. kernel-doc:: drivers/gpu/drm/amd/display/dc/dc.h
+   :doc: color-management-caps
+
+.. kernel-doc:: drivers/gpu/drm/amd/display/dc/dc.h
+   :internal:
+
+In general, the DRM three properties are programed to DC, as follows: CRTC
+gamma after blending, and CRTC degamma pre-blending. Although CTM is programmed
+after blending, it is mapped to DPP hw blocks (pre-blending). Other color caps
+available in the hw is not currently exposed by DRM interface and are by
+passed.  To illustrate DCN generation capabilities and differences between
+them, you can compare the color management schemas for DCN 2.0 and DCN 3.0
+families below.
+
+**DCN 2.0 family color caps and mapping**
+
+.. kernel-figure:: dcn2_cm_drm_current.svg
+
+**DCN 3.0 family color caps and mapping**
+
+.. kernel-figure:: dcn3_cm_drm_current.svg
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index 7c42377f0aae..84275f3974c1 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -118,7 +118,26 @@ struct dc_plane_cap {
 	uint32_t min_height;
 };
 
-// Color management caps (DPP and MPC)
+/**
+ * DOC: color-management-caps
+ *
+ * **Color management caps (DPP and MPC)**
+ *
+ * Modules/color calculates various colour operations which are translated to
+ * abstracted HW. DCE 5-12 had almost no important changes, but starting with
+ * DCN1, every new generation comes with fairly major differences in color
+ * pipeline. Therefore, we abstract color pipe capabilities so modules/DM can
+ * decide mapping to HW block based on logical capabilities.
+ */
+
+/**
+ * struct rom_curve_caps - predefined transfer function caps for degamma and regamma
+ * @srgb: RGB color space transfer func
+ * @bt2020: BT.2020 transfer func
+ * @gamma2_2: standard gamma
+ * @pq: perceptual quantizer transfer function
+ * @hlg: hybrid log–gamma transfer function
+ */
 struct rom_curve_caps {
 	uint16_t srgb : 1;
 	uint16_t bt2020 : 1;
@@ -127,36 +146,65 @@ struct rom_curve_caps {
 	uint16_t hlg : 1;
 };
 
+/**
+ * struct dpp_color_caps - color pipeline capabilities for display pipe and
+ * plane blocks
+ *
+ * @dcn_arch: all DCE generations treated the same
+ * @input_lut_shared: shared with DGAM. Input lut is different than most LUTs,
+ * just plain 256-entry lookup
+ * @icsc: input color space conversion
+ * @post_csc: post color space conversion, before gamut remap
+ * @gamma_corr: degamma correction
+ * @hw_3d_lut: 3d lut support. It implies a shaper LUT before, it may be shared
+ * with MPC by setting mpc:shared_3d_lut flag
+ * @ogam_ram: blend gamma
+ * @ocsc: output color space conversion
+ * @dgam_rom_caps: caps for degamma
+ * @ogam_rom_caps: caps for regamma 1D lut
+ *
+ * Note: hdr_mult and gamut remap (ctm) are always available in DPP (in that order)
+ */
 struct dpp_color_caps {
-	uint16_t dcn_arch : 1; // all DCE generations treated the same
-	// input lut is different than most LUTs, just plain 256-entry lookup
-	uint16_t input_lut_shared : 1; // shared with DGAM
+	uint16_t dcn_arch : 1;
+	uint16_t input_lut_shared : 1;
 	uint16_t icsc : 1;
 	uint16_t dgam_ram : 1;
-	uint16_t post_csc : 1; // before gamut remap
+	uint16_t post_csc : 1;
 	uint16_t gamma_corr : 1;
-
-	// hdr_mult and gamut remap always available in DPP (in that order)
-	// 3d lut implies shaper LUT,
-	// it may be shared with MPC - check MPC:shared_3d_lut flag
 	uint16_t hw_3d_lut : 1;
-	uint16_t ogam_ram : 1; // blnd gam
+	uint16_t ogam_ram : 1;
 	uint16_t ocsc : 1;
 	uint16_t dgam_rom_for_yuv : 1;
 	struct rom_curve_caps dgam_rom_caps;
 	struct rom_curve_caps ogam_rom_caps;
 };
 
+/**
+ * struct mpc_color_caps - color pipeline capabilities for multiple pipe and
+ * plane combined blocks
+ *
+ * @gamut_remap: color transformation matrix
+ * @ocsc: output color space conversion matrix
+ * @num_3dluts: 3d lut, always assumes a preceding shaper LUT
+ * @shared_3d_lut: shared 3d lut flag, can be either DPP or MPC, but single
+ * instance
+ * @ogam_rom_caps: caps for regama 1d lut
+ */
 struct mpc_color_caps {
 	uint16_t gamut_remap : 1;
 	uint16_t ogam_ram : 1;
 	uint16_t ocsc : 1;
-	uint16_t num_3dluts : 3; //3d lut always assumes a preceding shaper LUT
-	uint16_t shared_3d_lut:1; //can be in either DPP or MPC, but single instance
-
+	uint16_t num_3dluts : 3;
+	uint16_t shared_3d_lut:1;
 	struct rom_curve_caps ogam_rom_caps;
 };
 
+/**
+ * struct dc_color_caps - color pipes capabilities for DPP and MPC hw blocks
+ * @dpp: color pipes caps for DPP
+ * @mpc: color pipes caps for MPC
+ */
 struct dc_color_caps {
 	struct dpp_color_caps dpp;
 	struct mpc_color_caps mpc;
-- 
2.35.1

Re: [PATCH 2/4] Documentation/amdgpu/display: add DC color caps info

[Tales Lelo da Aparecida]

On 16/07/2022 19:25, Melissa Wen wrote:
> Add details about color correction capabilities and explain a bit about
> differences between DC hw generations and also how they are mapped
> between DRM and DC interface. Two schemas for DCN 2.0 and 3.0 (converted
> to svg from the original png) is included to illustrate it. They were
> obtained from a discussion[1] in the amd-gfx mailing list.
> 
> [1] https://lore.kernel.org/amd-gfx/20220422142811.dm6vtk6v64jcwydk@mail.igalia.com/
> 
> v2:
> 
> - remove redundant comments (Harry)
> - fix typo (Harry)
> 
> Signed-off-by: Melissa Wen <mwen@igalia.com>
> ---
>   .../amdgpu/display/dcn2_cm_drm_current.svg    | 1370 +++++++++++++++
>   .../amdgpu/display/dcn3_cm_drm_current.svg    | 1529 +++++++++++++++++
>   .../gpu/amdgpu/display/display-manager.rst    |   35 +
>   drivers/gpu/drm/amd/display/dc/dc.h           |   74 +-
>   4 files changed, 2995 insertions(+), 13 deletions(-)
>   create mode 100644 Documentation/gpu/amdgpu/display/dcn2_cm_drm_current.svg
>   create mode 100644 Documentation/gpu/amdgpu/display/dcn3_cm_drm_current.svg
> 
> diff --git a/Documentation/gpu/amdgpu/display/dcn2_cm_drm_current.svg b/Documentation/gpu/amdgpu/display/dcn2_cm_drm_current.svg
> new file mode 100644
> index 000000000000..315ffc5a1a4b
> --- /dev/null
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> diff --git a/Documentation/gpu/amdgpu/display/display-manager.rst b/Documentation/gpu/amdgpu/display/display-manager.rst
> index b1b0f11aed83..8960a5f1fa66 100644
> --- a/Documentation/gpu/amdgpu/display/display-manager.rst
> +++ b/Documentation/gpu/amdgpu/display/display-manager.rst
> @@ -49,3 +49,38 @@ Color Management Properties
>   
>   .. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
>      :internal:
> +
> +
> +DC Color Capabilities between DCN generations
> +---------------------------------------------
> +
> +DRM/KMS framework defines three CRTC color correction properties: degamma,
> +color transformation matrix (ctm) and gamma, and two properties for degamma and

Abbreviations should be written as all-uppercase
https://docs.kernel.org/gpu/introduction.html?highlight=uppercase#style-guidelines

> +gamma lut sizes. AMD DC programs some of the color correction features
> +pre-blending but DRM/KMS has not per-plane color correction properties.
> +
> +What's possible to do before and after blending has changed quite a bit between
> +DCN generations as it depends on hardware color capabilities. DPP and MPC color
> +correction caps are described below.
> +
> +.. kernel-doc:: drivers/gpu/drm/amd/display/dc/dc.h
> +   :doc: color-management-caps
> +
> +.. kernel-doc:: drivers/gpu/drm/amd/display/dc/dc.h
> +   :internal:
> +
> +In general, the DRM three properties are programed to DC, as follows: CRT > +gamma after blending, and CRTC degamma pre-blending. Although CTM is 
programmed
> +after blending, it is mapped to DPP hw blocks (pre-blending). Other color caps
> +available in the hw is not currently exposed by DRM interface and are by
> +passed.  To illustrate DCN generation capabilities and differences between

possible typo: "by\npassed" -> "bypassed"

> +them, you can compare the color management schemas for DCN 2.0 and DCN 3.0
> +families below.
> +
> +**DCN 2.0 family color caps and mapping**
> +
> +.. kernel-figure:: dcn2_cm_drm_current.svg
> +
> +**DCN 3.0 family color caps and mapping**
> +
> +.. kernel-figure:: dcn3_cm_drm_current.svg
> diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
> index 7c42377f0aae..84275f3974c1 100644
> --- a/drivers/gpu/drm/amd/display/dc/dc.h
> +++ b/drivers/gpu/drm/amd/display/dc/dc.h
> @@ -118,7 +118,26 @@ struct dc_plane_cap {
>   	uint32_t min_height;
>   };
>   
> -// Color management caps (DPP and MPC)
> +/**
> + * DOC: color-management-caps
> + *
> + * **Color management caps (DPP and MPC)**
> + *
> + * Modules/color calculates various colour operations which are translated to

Nit: colour -> color
The DRM documentation has a **preference** for the american spelling 
https://www.kernel.org/doc/html/latest/gpu/introduction.html?highlight=American%20English#style-guidelines

> + * abstracted HW. DCE 5-12 had almost no important changes, but starting with
> + * DCN1, every new generation comes with fairly major differences in color
> + * pipeline. Therefore, we abstract color pipe capabilities so modules/DM can
> + * decide mapping to HW block based on logical capabilities.
> + */
> +
> +/**
> + * struct rom_curve_caps - predefined transfer function caps for degamma and regamma
> + * @srgb: RGB color space transfer func
> + * @bt2020: BT.2020 transfer func
> + * @gamma2_2: standard gamma
> + * @pq: perceptual quantizer transfer function
> + * @hlg: hybrid log–gamma transfer function
> + */
>   struct rom_curve_caps {
>   	uint16_t srgb : 1;
>   	uint16_t bt2020 : 1;
> @@ -127,36 +146,65 @@ struct rom_curve_caps {
>   	uint16_t hlg : 1;
>   };
>   
> +/**
> + * struct dpp_color_caps - color pipeline capabilities for display pipe and
> + * plane blocks
> + *
> + * @dcn_arch: all DCE generations treated the same
> + * @input_lut_shared: shared with DGAM. Input lut is different than most LUTs,
> + * just plain 256-entry lookup
> + * @icsc: input color space conversion

./drivers/gpu/drm/amd/display/dc/dc.h:181: warning: Function parameter 
or member 'dgam_ram' not described in 'dpp_color_caps'

> + * @post_csc: post color space conversion, before gamut remap
> + * @gamma_corr: degamma correction
> + * @hw_3d_lut: 3d lut support. It implies a shaper LUT before, it may be shared
> + * with MPC by setting mpc:shared_3d_lut flag
> + * @ogam_ram: blend gamma
> + * @ocsc: output color space conversion

./drivers/gpu/drm/amd/display/dc/dc.h:181: warning: Function parameter 
or member 'dgam_rom_for_yuv' not described in 'dpp_color_caps'

> + * @dgam_rom_caps: caps for degamma
> + * @ogam_rom_caps: caps for regamma 1D lut
> + *
> + * Note: hdr_mult and gamut remap (ctm) are always available in DPP (in that order)
> + */
>   struct dpp_color_caps {
> -	uint16_t dcn_arch : 1; // all DCE generations treated the same
> -	// input lut is different than most LUTs, just plain 256-entry lookup
> -	uint16_t input_lut_shared : 1; // shared with DGAM
> +	uint16_t dcn_arch : 1;
> +	uint16_t input_lut_shared : 1;
>   	uint16_t icsc : 1;
>   	uint16_t dgam_ram : 1;
> -	uint16_t post_csc : 1; // before gamut remap
> +	uint16_t post_csc : 1;
>   	uint16_t gamma_corr : 1;
> -
> -	// hdr_mult and gamut remap always available in DPP (in that order)
> -	// 3d lut implies shaper LUT,
> -	// it may be shared with MPC - check MPC:shared_3d_lut flag
>   	uint16_t hw_3d_lut : 1;
> -	uint16_t ogam_ram : 1; // blnd gam
> +	uint16_t ogam_ram : 1;
>   	uint16_t ocsc : 1;
>   	uint16_t dgam_rom_for_yuv : 1;
>   	struct rom_curve_caps dgam_rom_caps;
>   	struct rom_curve_caps ogam_rom_caps;
>   };
>   
> +/**
> + * struct mpc_color_caps - color pipeline capabilities for multiple pipe and
> + * plane combined blocks
> + *
> + * @gamut_remap: color transformation matrix

./drivers/gpu/drm/amd/display/dc/dc.h:201: warning: Function parameter 
or member 'ogam_ram' not described in 'mpc_color_caps'

> + * @ocsc: output color space conversion matrix
> + * @num_3dluts: 3d lut, always assumes a preceding shaper LUT
> + * @shared_3d_lut: shared 3d lut flag, can be either DPP or MPC, but single
> + * instance
> + * @ogam_rom_caps: caps for regama 1d lut

typo: regama -> regamma

> + */
>   struct mpc_color_caps {
>   	uint16_t gamut_remap : 1;
>   	uint16_t ogam_ram : 1;
>   	uint16_t ocsc : 1;
> -	uint16_t num_3dluts : 3; //3d lut always assumes a preceding shaper LUT
> -	uint16_t shared_3d_lut:1; //can be in either DPP or MPC, but single instance
> -
> +	uint16_t num_3dluts : 3;
> +	uint16_t shared_3d_lut:1;
>   	struct rom_curve_caps ogam_rom_caps;
>   };
>   
> +/**
> + * struct dc_color_caps - color pipes capabilities for DPP and MPC hw blocks
> + * @dpp: color pipes caps for DPP
> + * @mpc: color pipes caps for MPC
> + */
>   struct dc_color_caps {
>   	struct dpp_color_caps dpp;
>   	struct mpc_color_caps mpc;


Again, thanks for the documentation patch!

Kind regards,
Tales Aparecida

Re: [PATCH 2/4] Documentation/amdgpu/display: add DC color caps info

[Melissa Wen]

[-- Attachment #1: Type: text/plain, Size: 148895 bytes --]

On 07/17, Tales Lelo da Aparecida wrote:
> On 16/07/2022 19:25, Melissa Wen wrote:
> > Add details about color correction capabilities and explain a bit about
> > differences between DC hw generations and also how they are mapped
> > between DRM and DC interface. Two schemas for DCN 2.0 and 3.0 (converted
> > to svg from the original png) is included to illustrate it. They were
> > obtained from a discussion[1] in the amd-gfx mailing list.
> > 
> > [1] https://lore.kernel.org/amd-gfx/20220422142811.dm6vtk6v64jcwydk@mail.igalia.com/
> > 
> > v2:
> > 
> > - remove redundant comments (Harry)
> > - fix typo (Harry)
> > 
> > Signed-off-by: Melissa Wen <mwen@igalia.com>
> > ---
> >   .../amdgpu/display/dcn2_cm_drm_current.svg    | 1370 +++++++++++++++
> >   .../amdgpu/display/dcn3_cm_drm_current.svg    | 1529 +++++++++++++++++
> >   .../gpu/amdgpu/display/display-manager.rst    |   35 +
> >   drivers/gpu/drm/amd/display/dc/dc.h           |   74 +-
> >   4 files changed, 2995 insertions(+), 13 deletions(-)
> >   create mode 100644 Documentation/gpu/amdgpu/display/dcn2_cm_drm_current.svg
> >   create mode 100644 Documentation/gpu/amdgpu/display/dcn3_cm_drm_current.svg
> > 
> > diff --git a/Documentation/gpu/amdgpu/display/dcn2_cm_drm_current.svg b/Documentation/gpu/amdgpu/display/dcn2_cm_drm_current.svg
> > new file mode 100644
> > index 000000000000..315ffc5a1a4b
> > --- /dev/null
> > +++ b/Documentation/gpu/amdgpu/display/dcn2_cm_drm_current.svg
> > @@ -0,0 +1,1370 @@
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> > diff --git a/Documentation/gpu/amdgpu/display/display-manager.rst b/Documentation/gpu/amdgpu/display/display-manager.rst
> > index b1b0f11aed83..8960a5f1fa66 100644
> > --- a/Documentation/gpu/amdgpu/display/display-manager.rst
> > +++ b/Documentation/gpu/amdgpu/display/display-manager.rst
> > @@ -49,3 +49,38 @@ Color Management Properties
> >   .. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
> >      :internal:
> > +
> > +
> > +DC Color Capabilities between DCN generations
> > +---------------------------------------------
> > +
> > +DRM/KMS framework defines three CRTC color correction properties: degamma,
> > +color transformation matrix (ctm) and gamma, and two properties for degamma and
> 
> Abbreviations should be written as all-uppercase
> https://docs.kernel.org/gpu/introduction.html?highlight=uppercase#style-guidelines
> 
> > +gamma lut sizes. AMD DC programs some of the color correction features
> > +pre-blending but DRM/KMS has not per-plane color correction properties.
> > +
> > +What's possible to do before and after blending has changed quite a bit between
> > +DCN generations as it depends on hardware color capabilities. DPP and MPC color
> > +correction caps are described below.
> > +
> > +.. kernel-doc:: drivers/gpu/drm/amd/display/dc/dc.h
> > +   :doc: color-management-caps
> > +
> > +.. kernel-doc:: drivers/gpu/drm/amd/display/dc/dc.h
> > +   :internal:
> > +
> > +In general, the DRM three properties are programed to DC, as follows:
> > CRT > +gamma after blending, and CRTC degamma pre-blending. Although CTM
> > is
> programmed
> > +after blending, it is mapped to DPP hw blocks (pre-blending). Other color caps
> > +available in the hw is not currently exposed by DRM interface and are by
> > +passed.  To illustrate DCN generation capabilities and differences between
> 
> possible typo: "by\npassed" -> "bypassed"
> 
> > +them, you can compare the color management schemas for DCN 2.0 and DCN 3.0
> > +families below.
> > +
> > +**DCN 2.0 family color caps and mapping**
> > +
> > +.. kernel-figure:: dcn2_cm_drm_current.svg
> > +
> > +**DCN 3.0 family color caps and mapping**
> > +
> > +.. kernel-figure:: dcn3_cm_drm_current.svg
> > diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
> > index 7c42377f0aae..84275f3974c1 100644
> > --- a/drivers/gpu/drm/amd/display/dc/dc.h
> > +++ b/drivers/gpu/drm/amd/display/dc/dc.h
> > @@ -118,7 +118,26 @@ struct dc_plane_cap {
> >   	uint32_t min_height;
> >   };
> > -// Color management caps (DPP and MPC)
> > +/**
> > + * DOC: color-management-caps
> > + *
> > + * **Color management caps (DPP and MPC)**
> > + *
> > + * Modules/color calculates various colour operations which are translated to
> 
> Nit: colour -> color
> The DRM documentation has a **preference** for the american spelling https://www.kernel.org/doc/html/latest/gpu/introduction.html?highlight=American%20English#style-guidelines
> 
> > + * abstracted HW. DCE 5-12 had almost no important changes, but starting with
> > + * DCN1, every new generation comes with fairly major differences in color
> > + * pipeline. Therefore, we abstract color pipe capabilities so modules/DM can
> > + * decide mapping to HW block based on logical capabilities.
> > + */
> > +
> > +/**
> > + * struct rom_curve_caps - predefined transfer function caps for degamma and regamma
> > + * @srgb: RGB color space transfer func
> > + * @bt2020: BT.2020 transfer func
> > + * @gamma2_2: standard gamma
> > + * @pq: perceptual quantizer transfer function
> > + * @hlg: hybrid log–gamma transfer function
> > + */
> >   struct rom_curve_caps {
> >   	uint16_t srgb : 1;
> >   	uint16_t bt2020 : 1;
> > @@ -127,36 +146,65 @@ struct rom_curve_caps {
> >   	uint16_t hlg : 1;
> >   };
> > +/**
> > + * struct dpp_color_caps - color pipeline capabilities for display pipe and
> > + * plane blocks
> > + *
> > + * @dcn_arch: all DCE generations treated the same
> > + * @input_lut_shared: shared with DGAM. Input lut is different than most LUTs,
> > + * just plain 256-entry lookup
> > + * @icsc: input color space conversion
> 
> ./drivers/gpu/drm/amd/display/dc/dc.h:181: warning: Function parameter or
> member 'dgam_ram' not described in 'dpp_color_caps'
>
For both warnings, the same as I said in the other patch: it would be
nice if someone can help on explaining the behavior of them here:
dgam_rom, dgam_rom_for_yuv, ogam_rom. I can suppose the meaning, but the best
way is that someone, more familiar with it, explains it properly.

> > + * @post_csc: post color space conversion, before gamut remap
> > + * @gamma_corr: degamma correction
> > + * @hw_3d_lut: 3d lut support. It implies a shaper LUT before, it may be shared
> > + * with MPC by setting mpc:shared_3d_lut flag
> > + * @ogam_ram: blend gamma
> > + * @ocsc: output color space conversion
> 
> ./drivers/gpu/drm/amd/display/dc/dc.h:181: warning: Function parameter or
> member 'dgam_rom_for_yuv' not described in 'dpp_color_caps'
> 
> > + * @dgam_rom_caps: caps for degamma
> > + * @ogam_rom_caps: caps for regamma 1D lut
> > + *
> > + * Note: hdr_mult and gamut remap (ctm) are always available in DPP (in that order)
> > + */
> >   struct dpp_color_caps {
> > -	uint16_t dcn_arch : 1; // all DCE generations treated the same
> > -	// input lut is different than most LUTs, just plain 256-entry lookup
> > -	uint16_t input_lut_shared : 1; // shared with DGAM
> > +	uint16_t dcn_arch : 1;
> > +	uint16_t input_lut_shared : 1;
> >   	uint16_t icsc : 1;
> >   	uint16_t dgam_ram : 1;
> > -	uint16_t post_csc : 1; // before gamut remap
> > +	uint16_t post_csc : 1;
> >   	uint16_t gamma_corr : 1;
> > -
> > -	// hdr_mult and gamut remap always available in DPP (in that order)
> > -	// 3d lut implies shaper LUT,
> > -	// it may be shared with MPC - check MPC:shared_3d_lut flag
> >   	uint16_t hw_3d_lut : 1;
> > -	uint16_t ogam_ram : 1; // blnd gam
> > +	uint16_t ogam_ram : 1;
> >   	uint16_t ocsc : 1;
> >   	uint16_t dgam_rom_for_yuv : 1;
> >   	struct rom_curve_caps dgam_rom_caps;
> >   	struct rom_curve_caps ogam_rom_caps;
> >   };
> > +/**
> > + * struct mpc_color_caps - color pipeline capabilities for multiple pipe and
> > + * plane combined blocks
> > + *
> > + * @gamut_remap: color transformation matrix
> 
> ./drivers/gpu/drm/amd/display/dc/dc.h:201: warning: Function parameter or
> member 'ogam_ram' not described in 'mpc_color_caps'
> 
> > + * @ocsc: output color space conversion matrix
> > + * @num_3dluts: 3d lut, always assumes a preceding shaper LUT
> > + * @shared_3d_lut: shared 3d lut flag, can be either DPP or MPC, but single
> > + * instance
> > + * @ogam_rom_caps: caps for regama 1d lut
> 
> typo: regama -> regamma
> 
> > + */
> >   struct mpc_color_caps {
> >   	uint16_t gamut_remap : 1;
> >   	uint16_t ogam_ram : 1;
> >   	uint16_t ocsc : 1;
> > -	uint16_t num_3dluts : 3; //3d lut always assumes a preceding shaper LUT
> > -	uint16_t shared_3d_lut:1; //can be in either DPP or MPC, but single instance
> > -
> > +	uint16_t num_3dluts : 3;
> > +	uint16_t shared_3d_lut:1;
> >   	struct rom_curve_caps ogam_rom_caps;
> >   };
> > +/**
> > + * struct dc_color_caps - color pipes capabilities for DPP and MPC hw blocks
> > + * @dpp: color pipes caps for DPP
> > + * @mpc: color pipes caps for MPC
> > + */
> >   struct dc_color_caps {
> >   	struct dpp_color_caps dpp;
> >   	struct mpc_color_caps mpc;
> 
> 
> Again, thanks for the documentation patch!

Thank you for the careful review
> 
> Kind regards,
> Tales Aparecida

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Re: [PATCH 2/4] Documentation/amdgpu/display: add DC color caps info

[Rodrigo Siqueira Jordao]

On 2022-07-17 19:28, Tales Lelo da Aparecida wrote:
> On 16/07/2022 19:25, Melissa Wen wrote:
>> Add details about color correction capabilities and explain a bit about
>> differences between DC hw generations and also how they are mapped
>> between DRM and DC interface. Two schemas for DCN 2.0 and 3.0 (converted
>> to svg from the original png) is included to illustrate it. They were
>> obtained from a discussion[1] in the amd-gfx mailing list.
>>
>> [1] 
>> https://lore.kernel.org/amd-gfx/20220422142811.dm6vtk6v64jcwydk@mail.igalia.com/ 
>>
>>
>> v2:
>>
>> - remove redundant comments (Harry)
>> - fix typo (Harry)
>>
>> Signed-off-by: Melissa Wen <mwen@igalia.com>
>> ---
>>   .../amdgpu/display/dcn2_cm_drm_current.svg    | 1370 +++++++++++++++
>>   .../amdgpu/display/dcn3_cm_drm_current.svg    | 1529 +++++++++++++++++
>>   .../gpu/amdgpu/display/display-manager.rst    |   35 +
>>   drivers/gpu/drm/amd/display/dc/dc.h           |   74 +-
>>   4 files changed, 2995 insertions(+), 13 deletions(-)
>>   create mode 100644 
>> Documentation/gpu/amdgpu/display/dcn2_cm_drm_current.svg
>>   create mode 100644 
>> Documentation/gpu/amdgpu/display/dcn3_cm_drm_current.svg
>>
>> diff --git a/Documentation/gpu/amdgpu/display/dcn2_cm_drm_current.svg 
>> b/Documentation/gpu/amdgpu/display/dcn2_cm_drm_current.svg
>> new file mode 100644
>> index 000000000000..315ffc5a1a4b
>> --- /dev/null
>> +++ b/Documentation/gpu/amdgpu/display/dcn2_cm_drm_current.svg
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>> diff --git a/Documentation/gpu/amdgpu/display/display-manager.rst 
>> b/Documentation/gpu/amdgpu/display/display-manager.rst
>> index b1b0f11aed83..8960a5f1fa66 100644
>> --- a/Documentation/gpu/amdgpu/display/display-manager.rst
>> +++ b/Documentation/gpu/amdgpu/display/display-manager.rst
>> @@ -49,3 +49,38 @@ Color Management Properties
>>   .. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
>>      :internal:
>> +
>> +
>> +DC Color Capabilities between DCN generations
>> +---------------------------------------------
>> +
>> +DRM/KMS framework defines three CRTC color correction properties: 
>> degamma,
>> +color transformation matrix (ctm) and gamma, and two properties for 
>> degamma and
> 
> Abbreviations should be written as all-uppercase
> https://docs.kernel.org/gpu/introduction.html?highlight=uppercase#style-guidelines 
> 
> 
>> +gamma lut sizes. AMD DC programs some of the color correction features
>> +pre-blending but DRM/KMS has not per-plane color correction properties.
>> +
>> +What's possible to do before and after blending has changed quite a 
>> bit between
>> +DCN generations as it depends on hardware color capabilities. DPP and 
>> MPC color
>> +correction caps are described below.
>> +
>> +.. kernel-doc:: drivers/gpu/drm/amd/display/dc/dc.h
>> +   :doc: color-management-caps
>> +
>> +.. kernel-doc:: drivers/gpu/drm/amd/display/dc/dc.h
>> +   :internal:
>> +
>> +In general, the DRM three properties are programed to DC, as follows: 
>> CRT > +gamma after blending, and CRTC degamma pre-blending. Although 
>> CTM is 
> programmed
>> +after blending, it is mapped to DPP hw blocks (pre-blending). Other 
>> color caps
>> +available in the hw is not currently exposed by DRM interface and are by
>> +passed.  To illustrate DCN generation capabilities and differences 
>> between
> 
> possible typo: "by\npassed" -> "bypassed"
> 
>> +them, you can compare the color management schemas for DCN 2.0 and 
>> DCN 3.0
>> +families below.
>> +
>> +**DCN 2.0 family color caps and mapping**
>> +
>> +.. kernel-figure:: dcn2_cm_drm_current.svg
>> +
>> +**DCN 3.0 family color caps and mapping**
>> +
>> +.. kernel-figure:: dcn3_cm_drm_current.svg
>> diff --git a/drivers/gpu/drm/amd/display/dc/dc.h 
>> b/drivers/gpu/drm/amd/display/dc/dc.h
>> index 7c42377f0aae..84275f3974c1 100644
>> --- a/drivers/gpu/drm/amd/display/dc/dc.h
>> +++ b/drivers/gpu/drm/amd/display/dc/dc.h
>> @@ -118,7 +118,26 @@ struct dc_plane_cap {
>>       uint32_t min_height;
>>   };
>> -// Color management caps (DPP and MPC)
>> +/**
>> + * DOC: color-management-caps
>> + *
>> + * **Color management caps (DPP and MPC)**
>> + *
>> + * Modules/color calculates various colour operations which are 
>> translated to
> 
> Nit: colour -> color
> The DRM documentation has a **preference** for the american spelling 
> https://www.kernel.org/doc/html/latest/gpu/introduction.html?highlight=American%20English#style-guidelines 
> 
> 
>> + * abstracted HW. DCE 5-12 had almost no important changes, but 
>> starting with
>> + * DCN1, every new generation comes with fairly major differences in 
>> color
>> + * pipeline. Therefore, we abstract color pipe capabilities so 
>> modules/DM can
>> + * decide mapping to HW block based on logical capabilities.
>> + */
>> +
>> +/**
>> + * struct rom_curve_caps - predefined transfer function caps for 
>> degamma and regamma
>> + * @srgb: RGB color space transfer func
>> + * @bt2020: BT.2020 transfer func
>> + * @gamma2_2: standard gamma
>> + * @pq: perceptual quantizer transfer function
>> + * @hlg: hybrid log–gamma transfer function
>> + */
>>   struct rom_curve_caps {
>>       uint16_t srgb : 1;
>>       uint16_t bt2020 : 1;
>> @@ -127,36 +146,65 @@ struct rom_curve_caps {
>>       uint16_t hlg : 1;
>>   };
>> +/**
>> + * struct dpp_color_caps - color pipeline capabilities for display 
>> pipe and
>> + * plane blocks
>> + *
>> + * @dcn_arch: all DCE generations treated the same
>> + * @input_lut_shared: shared with DGAM. Input lut is different than 
>> most LUTs,
>> + * just plain 256-entry lookup
>> + * @icsc: input color space conversion
> 
> ./drivers/gpu/drm/amd/display/dc/dc.h:181: warning: Function parameter 
> or member 'dgam_ram' not described in 'dpp_color_caps'

Hi,

I was trying to figure out the meaning of some of these fields.


First of all, and in the LUT context, notice that some fields have the 
prefix _ram, and others have _rom. When you see the ram, it means that 
we have a hardware LUT in the device, and we can program its values. If 
you see rom, it also means that we have hardware LUT but have 
pre-hardcoded values, which means that we can only select between a few 
of them (e.g., sRGB, PQ, etc.). I guess ROM is preferable since it 
requires less configuration.

> 
>> + * @post_csc: post color space conversion, before gamut remap
>> + * @gamma_corr: degamma correction
>> + * @hw_3d_lut: 3d lut support. It implies a shaper LUT before, it may 
>> be shared
>> + * with MPC by setting mpc:shared_3d_lut flag
>> + * @ogam_ram: blend gamma

dgam refers to 'degamma'

and

ogam to 'out gamma'.


>> + * @ocsc: output color space conversion
> 
> ./drivers/gpu/drm/amd/display/dc/dc.h:181: warning: Function parameter 
> or member 'dgam_rom_for_yuv' not described in 'dpp_color_caps'

dgam_rom_for_yuv -> I don't know precisely why we have this, but since 
DCN3 introduced it, I guess this is a specific behavior to compute yuv.

afaik, this caps stands for capabilities, i.e., dpp_color_caps describes 
the DPP color capabilities configured for the specific hardware and setup.

Best Regards
Siqueira

> 
>> + * @dgam_rom_caps: caps for degamma
>> + * @ogam_rom_caps: caps for regamma 1D lut
>> + *
>> + * Note: hdr_mult and gamut remap (ctm) are always available in DPP 
>> (in that order)
>> + */
>>   struct dpp_color_caps {
>> -    uint16_t dcn_arch : 1; // all DCE generations treated the same
>> -    // input lut is different than most LUTs, just plain 256-entry 
>> lookup
>> -    uint16_t input_lut_shared : 1; // shared with DGAM
>> +    uint16_t dcn_arch : 1;
>> +    uint16_t input_lut_shared : 1;
>>       uint16_t icsc : 1;
>>       uint16_t dgam_ram : 1;
>> -    uint16_t post_csc : 1; // before gamut remap
>> +    uint16_t post_csc : 1;
>>       uint16_t gamma_corr : 1;
>> -
>> -    // hdr_mult and gamut remap always available in DPP (in that order)
>> -    // 3d lut implies shaper LUT,
>> -    // it may be shared with MPC - check MPC:shared_3d_lut flag
>>       uint16_t hw_3d_lut : 1;
>> -    uint16_t ogam_ram : 1; // blnd gam
>> +    uint16_t ogam_ram : 1;
>>       uint16_t ocsc : 1;
>>       uint16_t dgam_rom_for_yuv : 1;
>>       struct rom_curve_caps dgam_rom_caps;
>>       struct rom_curve_caps ogam_rom_caps;
>>   };
>> +/**
>> + * struct mpc_color_caps - color pipeline capabilities for multiple 
>> pipe and
>> + * plane combined blocks
>> + *
>> + * @gamut_remap: color transformation matrix
> 
> ./drivers/gpu/drm/amd/display/dc/dc.h:201: warning: Function parameter 
> or member 'ogam_ram' not described in 'mpc_color_caps'
> 
>> + * @ocsc: output color space conversion matrix
>> + * @num_3dluts: 3d lut, always assumes a preceding shaper LUT
>> + * @shared_3d_lut: shared 3d lut flag, can be either DPP or MPC, but 
>> single
>> + * instance
>> + * @ogam_rom_caps: caps for regama 1d lut
> 
> typo: regama -> regamma
> 
>> + */
>>   struct mpc_color_caps {
>>       uint16_t gamut_remap : 1;
>>       uint16_t ogam_ram : 1;
>>       uint16_t ocsc : 1;
>> -    uint16_t num_3dluts : 3; //3d lut always assumes a preceding 
>> shaper LUT
>> -    uint16_t shared_3d_lut:1; //can be in either DPP or MPC, but 
>> single instance
>> -
>> +    uint16_t num_3dluts : 3;
>> +    uint16_t shared_3d_lut:1;
>>       struct rom_curve_caps ogam_rom_caps;
>>   };
>> +/**
>> + * struct dc_color_caps - color pipes capabilities for DPP and MPC hw 
>> blocks
>> + * @dpp: color pipes caps for DPP
>> + * @mpc: color pipes caps for MPC
>> + */
>>   struct dc_color_caps {
>>       struct dpp_color_caps dpp;
>>       struct mpc_color_caps mpc;
> 
> 
> Again, thanks for the documentation patch!
> 
> Kind regards,
> Tales Aparecida

Re: [PATCH 2/4] Documentation/amdgpu/display: add DC color caps info

[Melissa Wen]

[-- Attachment #1: Type: text/plain, Size: 174808 bytes --]

On 07/27, Rodrigo Siqueira Jordao wrote:
> 
> 
> On 2022-07-17 19:28, Tales Lelo da Aparecida wrote:
> > On 16/07/2022 19:25, Melissa Wen wrote:
> > > Add details about color correction capabilities and explain a bit about
> > > differences between DC hw generations and also how they are mapped
> > > between DRM and DC interface. Two schemas for DCN 2.0 and 3.0 (converted
> > > to svg from the original png) is included to illustrate it. They were
> > > obtained from a discussion[1] in the amd-gfx mailing list.
> > > 
> > > [1] https://lore.kernel.org/amd-gfx/20220422142811.dm6vtk6v64jcwydk@mail.igalia.com/
> > > 
> > > 
> > > v2:
> > > 
> > > - remove redundant comments (Harry)
> > > - fix typo (Harry)
> > > 
> > > Signed-off-by: Melissa Wen <mwen@igalia.com>
> > > ---
> > >   .../amdgpu/display/dcn2_cm_drm_current.svg    | 1370 +++++++++++++++
> > >   .../amdgpu/display/dcn3_cm_drm_current.svg    | 1529 +++++++++++++++++
> > >   .../gpu/amdgpu/display/display-manager.rst    |   35 +
> > >   drivers/gpu/drm/amd/display/dc/dc.h           |   74 +-
> > >   4 files changed, 2995 insertions(+), 13 deletions(-)
> > >   create mode 100644
> > > Documentation/gpu/amdgpu/display/dcn2_cm_drm_current.svg
> > >   create mode 100644
> > > Documentation/gpu/amdgpu/display/dcn3_cm_drm_current.svg
> > > 
> > > diff --git
> > > a/Documentation/gpu/amdgpu/display/dcn2_cm_drm_current.svg
> > > b/Documentation/gpu/amdgpu/display/dcn2_cm_drm_current.svg
> > > new file mode 100644
> > > index 000000000000..315ffc5a1a4b
> > > --- /dev/null
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> > > +         style="font-size:18.6667px">Blend Gamma</tspan></text>
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> > > +    <text
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> > > +       x="913.72528"
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> > > +    <text
> > > +       xml:space="preserve"
> > > +       style="font-style:normal;font-weight:normal;font-size:18.6667px;line-height:1.25;font-family:sans-serif;fill:#000000;fill-opacity:1;stroke:none"
> > > 
> > > +       x="937.72528"
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> > > +    <text
> > > +       xml:space="preserve"
> > > +       style="font-style:normal;font-weight:normal;font-size:18.6667px;line-height:1.25;font-family:sans-serif;fill:#000000;fill-opacity:1;stroke:none"
> > > 
> > > +       x="945.9895"
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> > > +    <text
> > > +       xml:space="preserve"
> > > +       style="font-style:normal;font-weight:normal;font-size:18.6667px;line-height:1.25;font-family:sans-serif;fill:#000000;fill-opacity:1;stroke:none"
> > > 
> > > +       x="975.91803"
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> > > +         id="tspan137432"
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> > > +         style="font-size:18.6667px">Blender</tspan></text>
> > > +    <text
> > > +       xml:space="preserve"
> > > +       style="font-style:normal;font-weight:normal;font-size:18.6667px;line-height:1.25;font-family:sans-serif;fill:#000000;fill-opacity:1;stroke:none"
> > > 
> > > +       x="879.31372"
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> > > +         sodipodi:role="line"
> > > +         id="tspan137432-7"
> > > +         x="879.31372"
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> > > +         style="font-size:18.6667px">gamut_remap_matrix</tspan></text>
> > > +    <text
> > > +       xml:space="preserve"
> > > +       style="font-style:normal;font-weight:normal;font-size:18.6667px;line-height:1.25;font-family:sans-serif;fill:#000000;fill-opacity:1;stroke:none"
> > > 
> > > +       x="925.31372"
> > > +       y="1359.2747"
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> > > +         sodipodi:role="line"
> > > +         id="tspan137432-9"
> > > +         x="925.31372"
> > > +         y="1359.2747"
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> > > +    <text
> > > +       xml:space="preserve"
> > > +       style="font-style:normal;font-weight:normal;font-size:18.6667px;line-height:1.25;font-family:sans-serif;fill:#000000;fill-opacity:1;stroke:none"
> > > 
> > > +       x="930.33252"
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> > > +         sodipodi:role="line"
> > > +         id="tspan137432-6"
> > > +         x="930.33252"
> > > +         y="1430.2566"
> > > +         style="font-size:18.6667px">lut3d_func</tspan></text>
> > > +    <text
> > > +       xml:space="preserve"
> > > +       style="font-style:normal;font-weight:normal;font-size:18.6667px;line-height:1.25;font-family:sans-serif;fill:#000000;fill-opacity:1;stroke:none"
> > > 
> > > +       x="900.18158"
> > > +       y="1504.6725"
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> > > +         sodipodi:role="line"
> > > +         id="tspan137432-2"
> > > +         x="900.18158"
> > > +         y="1504.6725"
> > > +         style="font-size:18.6667px">out_transfer_func</tspan></text>
> > > +    <text
> > > +       xml:space="preserve"
> > > +       style="font-style:normal;font-weight:normal;font-size:18.6667px;line-height:1.25;font-family:sans-serif;fill:#000000;fill-opacity:1;stroke:none"
> > > 
> > > +       x="904.0307"
> > > +       y="1575.8053"
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> > > +         sodipodi:role="line"
> > > +         id="tspan137432-1"
> > > +         x="904.0307"
> > > +         y="1575.8053"
> > > +         style="font-size:18.6667px">csc_color_matrix</tspan></text>
> > > +    <text
> > > +       xml:space="preserve"
> > > +       style="font-style:normal;font-weight:normal;font-size:18.6667px;line-height:1.25;font-family:sans-serif;fill:#000000;fill-opacity:1;stroke:none"
> > > 
> > > +       x="903.16278"
> > > +       y="1642.1078"
> > > +       id="text137434-8"><tspan
> > > +         sodipodi:role="line"
> > > +         id="tspan137432-79"
> > > +         x="903.16278"
> > > +         y="1642.1078"
> > > +         style="font-size:18.6667px">bit_depth_param</tspan></text>
> > > +    <text
> > > +       xml:space="preserve"
> > > +       style="font-style:normal;font-weight:normal;font-size:18.6667px;line-height:1.25;font-family:sans-serif;fill:#000000;fill-opacity:1;stroke:none"
> > > 
> > > +       x="939.31372"
> > > +       y="1713.8068"
> > > +       id="text137434-20"><tspan
> > > +         sodipodi:role="line"
> > > +         id="tspan137432-23"
> > > +         x="939.31372"
> > > +         y="1713.8068"
> > > +         style="font-size:18.6667px">clamping</tspan></text>
> > > +    <text
> > > +       xml:space="preserve"
> > > +       style="font-style:normal;font-weight:normal;font-size:18.6667px;line-height:1.25;font-family:sans-serif;fill:#000000;fill-opacity:1;stroke:none"
> > > 
> > > +       x="894.0307"
> > > +       y="1782.5244"
> > > +       id="text137434-7"><tspan
> > > +         sodipodi:role="line"
> > > +         id="tspan137432-5"
> > > +         x="894.0307"
> > > +         y="1782.5244"
> > > +         style="font-size:18.6667px">output_color_space</tspan></text>
> > > +    <text
> > > +       xml:space="preserve"
> > > +       style="font-style:normal;font-weight:normal;font-size:18.6667px;line-height:1.25;font-family:sans-serif;fill:#000000;fill-opacity:1;stroke:none"
> > > 
> > > +       x="869.63062"
> > > +       y="117.7968"
> > > +       id="text176429"><tspan
> > > +         sodipodi:role="line"
> > > +         id="tspan176427"
> > > +         x="869.63062"
> > > +         y="117.7968"
> > > +         style="font-size:18.6667px">Plane</tspan></text>
> > > +    <text
> > > +       xml:space="preserve"
> > > +       style="font-style:normal;font-weight:normal;font-size:18.6667px;line-height:1.25;font-family:sans-serif;fill:#000000;fill-opacity:1;stroke:none"
> > > 
> > > +       x="27.605465"
> > > +       y="162.20587"
> > > +       id="text176429-2"><tspan
> > > +         sodipodi:role="line"
> > > +         id="tspan176427-0"
> > > +         x="27.605465"
> > > +         y="162.20587"
> > > +         style="font-size:18.6667px">Legend</tspan></text>
> > > +    <text
> > > +       xml:space="preserve"
> > > +       style="font-style:normal;font-weight:normal;font-size:18.6667px;line-height:1.25;font-family:sans-serif;fill:#000000;fill-opacity:1;stroke:none"
> > > 
> > > +       x="298.63959"
> > > +       y="59.293999"
> > > +       id="text176429-9"><tspan
> > > +         sodipodi:role="line"
> > > +         id="tspan176427-2"
> > > +         x="298.63959"
> > > +         y="59.293999"
> > > +         style="font-size:18.6667px">DCN 3.0</tspan></text>
> > > +    <text
> > > +       xml:space="preserve"
> > > +       style="font-style:normal;font-weight:normal;font-size:18.6667px;line-height:1.25;font-family:sans-serif;fill:#000000;fill-opacity:1;stroke:none"
> > > 
> > > +       x="826.65735"
> > > +       y="59.458061"
> > > +       id="text176429-66"><tspan
> > > +         sodipodi:role="line"
> > > +         id="tspan176427-4"
> > > +         x="826.65735"
> > > +         y="59.458061"
> > > +         style="font-size:18.6667px">DC Interface</tspan></text>
> > > +    <text
> > > +       xml:space="preserve"
> > > +       style="font-style:normal;font-weight:normal;font-size:18.6667px;line-height:1.25;font-family:sans-serif;fill:#000000;fill-opacity:1;stroke:none"
> > > 
> > > +       x="1362.9948"
> > > +       y="59.458061"
> > > +       id="text176429-95"><tspan
> > > +         sodipodi:role="line"
> > > +         id="tspan176427-04"
> > > +         x="1362.9948"
> > > +         y="59.458061"
> > > +         style="font-size:18.6667px">DRM Interface</tspan></text>
> > > +    <text
> > > +       xml:space="preserve"
> > > +       style="font-style:normal;font-weight:normal;font-size:40px;line-height:1.25;font-family:sans-serif;fill:#000000;fill-opacity:1;stroke:none"
> > > 
> > > +       x="867.34656"
> > > +       y="1194.5068"
> > > +       id="text184728"><tspan
> > > +         sodipodi:role="line"
> > > +         id="tspan184726"
> > > +         x="867.34656"
> > > +         y="1194.5068" /></text>
> > > +    <text
> > > +       xml:space="preserve"
> > > +       style="font-style:normal;font-weight:normal;font-size:18.6667px;line-height:1.25;font-family:sans-serif;fill:#000000;fill-opacity:1;stroke:none"
> > > 
> > > +       x="389.01593"
> > > +       y="159.8909"
> > > +       id="text64469-9-3"><tspan
> > > +         sodipodi:role="line"
> > > +         id="tspan64467-2-6"
> > > +         x="389.01593"
> > > +         y="159.8909"
> > > +         style="font-size:18.6667px">CNVC</tspan></text>
> > > +    <text
> > > +       xml:space="preserve"
> > > +       style="font-style:normal;font-weight:normal;font-size:18.6667px;line-height:1.25;font-family:sans-serif;fill:#000000;fill-opacity:1;stroke:none"
> > > 
> > > +       x="365.88379"
> > > +       y="303.59048"
> > > +       id="text64469-9-1"><tspan
> > > +         sodipodi:role="line"
> > > +         id="tspan64467-2-2"
> > > +         x="365.88379"
> > > +         y="303.59048"
> > > +         style="font-size:18.6667px">Input CSC</tspan></text>
> > > +    <text
> > > +       xml:space="preserve"
> > > +       style="font-style:normal;font-weight:normal;font-size:18.6667px;line-height:1.25;font-family:sans-serif;fill:#000000;fill-opacity:1;stroke:none"
> > > 
> > > +       x="413.06488"
> > > +       y="390.95001"
> > > +       id="text64469-9-93"><tspan
> > > +         sodipodi:role="line"
> > > +         id="tspan64467-2-1"
> > > +         x="413.06488"
> > > +         y="390.95001"
> > > +         style="font-size:18.6667px;text-align:center;text-anchor:middle">DeGamma</tspan><tspan
> > > 
> > > +         sodipodi:role="line"
> > > +         x="413.06488"
> > > +         y="414.28339"
> > > +
> > > style="font-size:18.6667px;text-align:center;text-anchor:middle"
> > > +         id="tspan233797">ROM</tspan><tspan
> > > +         sodipodi:role="line"
> > > +         x="413.06488"
> > > +         y="437.61676"
> > > +
> > > style="font-size:10.6667px;text-align:center;text-anchor:middle"
> > > +         id="tspan233799">(sRGB, BT2020, Gamma 2.2,</tspan><tspan
> > > +         sodipodi:role="line"
> > > +         x="413.06488"
> > > +         y="460.95013"
> > > +
> > > style="font-size:10.6667px;text-align:center;text-anchor:middle"
> > > +         id="tspan242597">PQ, HLG)</tspan></text>
> > > +    <text
> > > +       xml:space="preserve"
> > > +       style="font-style:normal;font-weight:normal;font-size:18.6667px;line-height:1.25;font-family:sans-serif;fill:#000000;fill-opacity:1;stroke:none"
> > > 
> > > +       x="372.44986"
> > > +       y="538.83807"
> > > +       id="text64469-9-94"><tspan
> > > +         sodipodi:role="line"
> > > +         id="tspan64467-2-78"
> > > +         x="372.44986"
> > > +         y="538.83807"
> > > +         style="font-size:18.6667px">Post CSC</tspan></text>
> > > +    <text
> > > +       xml:space="preserve"
> > > +       style="font-style:normal;font-weight:normal;font-size:16px;line-height:1.25;font-family:sans-serif;fill:#000000;fill-opacity:1;stroke:none"
> > > 
> > > +       x="335.31775"
> > > +       y="622.23511"
> > > +       id="text64469-9-4"><tspan
> > > +         sodipodi:role="line"
> > > +         id="tspan64467-2-5"
> > > +         x="335.31775"
> > > +         y="622.23511"
> > > +         style="font-size:16px">Gamma Correction</tspan></text>
> > > +    <text
> > > +       xml:space="preserve"
> > > +       style="font-style:normal;font-weight:normal;font-size:18.6667px;line-height:1.25;font-family:sans-serif;fill:#000000;fill-opacity:1;stroke:none"
> > > 
> > > +       x="351.16684"
> > > +       y="700.34918"
> > > +       id="text64469-9-0"><tspan
> > > +         sodipodi:role="line"
> > > +         id="tspan64467-2-3"
> > > +         x="351.16684"
> > > +         y="700.34918"
> > > +         style="font-size:18.6667px">HDR Multiply</tspan></text>
> > > +    <text
> > > +       xml:space="preserve"
> > > +       style="font-style:normal;font-weight:normal;font-size:18.6667px;line-height:1.25;font-family:sans-serif;fill:#000000;fill-opacity:1;stroke:none"
> > > 
> > > +       x="345.16684"
> > > +       y="771.33112"
> > > +       id="text64469-9-6"><tspan
> > > +         sodipodi:role="line"
> > > +         id="tspan64467-2-10"
> > > +         x="345.16684"
> > > +         y="771.33112"
> > > +         style="font-size:18.6667px">Gamut Remap</tspan></text>
> > > +    <text
> > > +       xml:space="preserve"
> > > +       style="font-style:normal;font-weight:normal;font-size:18.6667px;line-height:1.25;font-family:sans-serif;fill:#000000;fill-opacity:1;stroke:none"
> > > 
> > > +       x="412.5184"
> > > +       y="836.04877"
> > > +       id="text64469-9-63"><tspan
> > > +         sodipodi:role="line"
> > > +         id="tspan64467-2-20"
> > > +         x="412.5184"
> > > +         y="836.04877"
> > > +
> > > style="font-size:18.6667px;text-align:center;text-anchor:middle">Shaper
> > > LUT</tspan><tspan
> > > 
> > > +         sodipodi:role="line"
> > > +         x="412.5184"
> > > +         y="859.38214"
> > > +
> > > style="font-size:18.6667px;text-align:center;text-anchor:middle"
> > > +         id="tspan222533">RAM</tspan></text>
> > > +    <text
> > > +       xml:space="preserve"
> > > +       style="font-style:normal;font-weight:normal;font-size:18.6667px;line-height:1.25;font-family:sans-serif;fill:#000000;fill-opacity:1;stroke:none"
> > > 
> > > +       x="413.54086"
> > > +       y="908.61554"
> > > +       id="text64469-9-61"><tspan
> > > +         sodipodi:role="line"
> > > +         id="tspan64467-2-55"
> > > +         x="413.54086"
> > > +         y="908.61554"
> > > +
> > > style="font-size:18.6667px;text-align:center;text-anchor:middle">3D
> > > LUT</tspan><tspan
> > > +         sodipodi:role="line"
> > > +         x="413.54086"
> > > +         y="931.94891"
> > > +
> > > style="font-size:18.6667px;text-align:center;text-anchor:middle"
> > > +         id="tspan221121">RAM</tspan></text>
> > > +    <text
> > > +       xml:space="preserve"
> > > +       style="font-style:normal;font-weight:normal;font-size:18.6667px;line-height:1.25;font-family:sans-serif;fill:#000000;fill-opacity:1;stroke:none"
> > > 
> > > +       x="344.0347"
> > > +       y="985.33319"
> > > +       id="text64469-9-47"><tspan
> > > +         sodipodi:role="line"
> > > +         id="tspan64467-2-65"
> > > +         x="344.0347"
> > > +         y="985.33319"
> > > +         style="font-size:18.6667px">Blend Gamma</tspan></text>
> > > +    <text
> > > +       xml:space="preserve"
> > > +       style="font-style:normal;font-weight:normal;font-size:18.6667px;line-height:1.25;font-family:sans-serif;fill:#000000;fill-opacity:1;stroke:none"
> > > 
> > > +       x="433.84625"
> > > +       y="1223.411"
> > > +       id="text64469-9-69"><tspan
> > > +         sodipodi:role="line"
> > > +         id="tspan64467-2-37"
> > > +         x="433.84625"
> > > +         y="1223.411"
> > > +         style="font-size:18.6667px">Blender</tspan></text>
> > > +    <text
> > > +       xml:space="preserve"
> > > +       style="font-style:normal;font-weight:normal;font-size:18.6667px;line-height:1.25;font-family:sans-serif;fill:#000000;fill-opacity:1;stroke:none"
> > > 
> > > +       x="343.73291"
> > > +       y="1290.2421"
> > > +       id="text64469-9-45"><tspan
> > > +         sodipodi:role="line"
> > > +         id="tspan64467-2-25"
> > > +         x="343.73291"
> > > +         y="1290.2421"
> > > +         style="font-size:18.6667px">Gamut Remap</tspan></text>
> > > +    <text
> > > +       xml:space="preserve"
> > > +       style="font-style:normal;font-weight:normal;font-size:18.6667px;line-height:1.25;font-family:sans-serif;fill:#000000;fill-opacity:1;stroke:none"
> > > 
> > > +       x="408.74442"
> > > +       y="1344.2428"
> > > +       id="text64469-9-474"><tspan
> > > +         sodipodi:role="line"
> > > +         id="tspan64467-2-4"
> > > +         x="408.74442"
> > > +         y="1344.2428"
> > > +
> > > style="font-size:18.6667px;text-align:center;text-anchor:middle">Shaper
> > > LUT</tspan><tspan
> > > 
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> > > diff --git a/Documentation/gpu/amdgpu/display/display-manager.rst
> > > b/Documentation/gpu/amdgpu/display/display-manager.rst
> > > index b1b0f11aed83..8960a5f1fa66 100644
> > > --- a/Documentation/gpu/amdgpu/display/display-manager.rst
> > > +++ b/Documentation/gpu/amdgpu/display/display-manager.rst
> > > @@ -49,3 +49,38 @@ Color Management Properties
> > >   .. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
> > >      :internal:
> > > +
> > > +
> > > +DC Color Capabilities between DCN generations
> > > +---------------------------------------------
> > > +
> > > +DRM/KMS framework defines three CRTC color correction properties:
> > > degamma,
> > > +color transformation matrix (ctm) and gamma, and two properties for
> > > degamma and
> > 
> > Abbreviations should be written as all-uppercase
> > https://docs.kernel.org/gpu/introduction.html?highlight=uppercase#style-guidelines
> > 
> > 
> > > +gamma lut sizes. AMD DC programs some of the color correction features
> > > +pre-blending but DRM/KMS has not per-plane color correction properties.
> > > +
> > > +What's possible to do before and after blending has changed quite a
> > > bit between
> > > +DCN generations as it depends on hardware color capabilities. DPP
> > > and MPC color
> > > +correction caps are described below.
> > > +
> > > +.. kernel-doc:: drivers/gpu/drm/amd/display/dc/dc.h
> > > +   :doc: color-management-caps
> > > +
> > > +.. kernel-doc:: drivers/gpu/drm/amd/display/dc/dc.h
> > > +   :internal:
> > > +
> > > +In general, the DRM three properties are programed to DC, as
> > > follows: CRT > +gamma after blending, and CRTC degamma pre-blending.
> > > Although CTM is
> > programmed
> > > +after blending, it is mapped to DPP hw blocks (pre-blending). Other
> > > color caps
> > > +available in the hw is not currently exposed by DRM interface and are by
> > > +passed.  To illustrate DCN generation capabilities and differences
> > > between
> > 
> > possible typo: "by\npassed" -> "bypassed"
> > 
> > > +them, you can compare the color management schemas for DCN 2.0 and
> > > DCN 3.0
> > > +families below.
> > > +
> > > +**DCN 2.0 family color caps and mapping**
> > > +
> > > +.. kernel-figure:: dcn2_cm_drm_current.svg
> > > +
> > > +**DCN 3.0 family color caps and mapping**
> > > +
> > > +.. kernel-figure:: dcn3_cm_drm_current.svg
> > > diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
> > > b/drivers/gpu/drm/amd/display/dc/dc.h
> > > index 7c42377f0aae..84275f3974c1 100644
> > > --- a/drivers/gpu/drm/amd/display/dc/dc.h
> > > +++ b/drivers/gpu/drm/amd/display/dc/dc.h
> > > @@ -118,7 +118,26 @@ struct dc_plane_cap {
> > >       uint32_t min_height;
> > >   };
> > > -// Color management caps (DPP and MPC)
> > > +/**
> > > + * DOC: color-management-caps
> > > + *
> > > + * **Color management caps (DPP and MPC)**
> > > + *
> > > + * Modules/color calculates various colour operations which are
> > > translated to
> > 
> > Nit: colour -> color
> > The DRM documentation has a **preference** for the american spelling https://www.kernel.org/doc/html/latest/gpu/introduction.html?highlight=American%20English#style-guidelines
> > 
> > 
> > > + * abstracted HW. DCE 5-12 had almost no important changes, but
> > > starting with
> > > + * DCN1, every new generation comes with fairly major differences
> > > in color
> > > + * pipeline. Therefore, we abstract color pipe capabilities so
> > > modules/DM can
> > > + * decide mapping to HW block based on logical capabilities.
> > > + */
> > > +
> > > +/**
> > > + * struct rom_curve_caps - predefined transfer function caps for
> > > degamma and regamma
> > > + * @srgb: RGB color space transfer func
> > > + * @bt2020: BT.2020 transfer func
> > > + * @gamma2_2: standard gamma
> > > + * @pq: perceptual quantizer transfer function
> > > + * @hlg: hybrid log–gamma transfer function
> > > + */
> > >   struct rom_curve_caps {
> > >       uint16_t srgb : 1;
> > >       uint16_t bt2020 : 1;
> > > @@ -127,36 +146,65 @@ struct rom_curve_caps {
> > >       uint16_t hlg : 1;
> > >   };
> > > +/**
> > > + * struct dpp_color_caps - color pipeline capabilities for display
> > > pipe and
> > > + * plane blocks
> > > + *
> > > + * @dcn_arch: all DCE generations treated the same
> > > + * @input_lut_shared: shared with DGAM. Input lut is different than
> > > most LUTs,
> > > + * just plain 256-entry lookup
> > > + * @icsc: input color space conversion
> > 
> > ./drivers/gpu/drm/amd/display/dc/dc.h:181: warning: Function parameter
> > or member 'dgam_ram' not described in 'dpp_color_caps'
> 
> Hi,
> 
> I was trying to figure out the meaning of some of these fields.
> 
> 
> First of all, and in the LUT context, notice that some fields have the
> prefix _ram, and others have _rom. When you see the ram, it means that we
> have a hardware LUT in the device, and we can program its values. If you see
> rom, it also means that we have hardware LUT but have pre-hardcoded values,
> which means that we can only select between a few of them (e.g., sRGB, PQ,
> etc.). I guess ROM is preferable since it requires less configuration.

Hi Siqueira,

Oh, thanks for describing the rom/ram differences (and sounds like a
analogy).

> 
> > 
> > > + * @post_csc: post color space conversion, before gamut remap
> > > + * @gamma_corr: degamma correction
> > > + * @hw_3d_lut: 3d lut support. It implies a shaper LUT before, it
> > > may be shared
> > > + * with MPC by setting mpc:shared_3d_lut flag
> > > + * @ogam_ram: blend gamma
> 
> dgam refers to 'degamma'
> 
> and
> 
> ogam to 'out gamma'.
> 
> 
> > > + * @ocsc: output color space conversion
> > 
> > ./drivers/gpu/drm/amd/display/dc/dc.h:181: warning: Function parameter
> > or member 'dgam_rom_for_yuv' not described in 'dpp_color_caps'
> 
> dgam_rom_for_yuv -> I don't know precisely why we have this, but since DCN3
> introduced it, I guess this is a specific behavior to compute yuv.
> 
> afaik, this caps stands for capabilities, i.e., dpp_color_caps describes the
> DPP color capabilities configured for the specific hardware and setup.

I'm preparing a v2 that includes your inputs.

Thanks again,

Melissa
> 
> Best Regards
> Siqueira
> 
> > 
> > > + * @dgam_rom_caps: caps for degamma
> > > + * @ogam_rom_caps: caps for regamma 1D lut
> > > + *
> > > + * Note: hdr_mult and gamut remap (ctm) are always available in DPP
> > > (in that order)
> > > + */
> > >   struct dpp_color_caps {
> > > -    uint16_t dcn_arch : 1; // all DCE generations treated the same
> > > -    // input lut is different than most LUTs, just plain 256-entry
> > > lookup
> > > -    uint16_t input_lut_shared : 1; // shared with DGAM
> > > +    uint16_t dcn_arch : 1;
> > > +    uint16_t input_lut_shared : 1;
> > >       uint16_t icsc : 1;
> > >       uint16_t dgam_ram : 1;
> > > -    uint16_t post_csc : 1; // before gamut remap
> > > +    uint16_t post_csc : 1;
> > >       uint16_t gamma_corr : 1;
> > > -
> > > -    // hdr_mult and gamut remap always available in DPP (in that order)
> > > -    // 3d lut implies shaper LUT,
> > > -    // it may be shared with MPC - check MPC:shared_3d_lut flag
> > >       uint16_t hw_3d_lut : 1;
> > > -    uint16_t ogam_ram : 1; // blnd gam
> > > +    uint16_t ogam_ram : 1;
> > >       uint16_t ocsc : 1;
> > >       uint16_t dgam_rom_for_yuv : 1;
> > >       struct rom_curve_caps dgam_rom_caps;
> > >       struct rom_curve_caps ogam_rom_caps;
> > >   };
> > > +/**
> > > + * struct mpc_color_caps - color pipeline capabilities for multiple
> > > pipe and
> > > + * plane combined blocks
> > > + *
> > > + * @gamut_remap: color transformation matrix
> > 
> > ./drivers/gpu/drm/amd/display/dc/dc.h:201: warning: Function parameter
> > or member 'ogam_ram' not described in 'mpc_color_caps'
> > 
> > > + * @ocsc: output color space conversion matrix
> > > + * @num_3dluts: 3d lut, always assumes a preceding shaper LUT
> > > + * @shared_3d_lut: shared 3d lut flag, can be either DPP or MPC,
> > > but single
> > > + * instance
> > > + * @ogam_rom_caps: caps for regama 1d lut
> > 
> > typo: regama -> regamma
> > 
> > > + */
> > >   struct mpc_color_caps {
> > >       uint16_t gamut_remap : 1;
> > >       uint16_t ogam_ram : 1;
> > >       uint16_t ocsc : 1;
> > > -    uint16_t num_3dluts : 3; //3d lut always assumes a preceding
> > > shaper LUT
> > > -    uint16_t shared_3d_lut:1; //can be in either DPP or MPC, but
> > > single instance
> > > -
> > > +    uint16_t num_3dluts : 3;
> > > +    uint16_t shared_3d_lut:1;
> > >       struct rom_curve_caps ogam_rom_caps;
> > >   };
> > > +/**
> > > + * struct dc_color_caps - color pipes capabilities for DPP and MPC
> > > hw blocks
> > > + * @dpp: color pipes caps for DPP
> > > + * @mpc: color pipes caps for MPC
> > > + */
> > >   struct dc_color_caps {
> > >       struct dpp_color_caps dpp;
> > >       struct mpc_color_caps mpc;
> > 
> > 
> > Again, thanks for the documentation patch!
> > 
> > Kind regards,
> > Tales Aparecida
> 

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[PATCH 3/4] drm/amd/display: add doc entries for MPC blending configuration

[Melissa Wen]

Describe structs and enums used to set blend mode properties to MPC
blocks. Some pieces of information are already available as code
comments, and were just formatted. Others were collected and summarised
from discusssions on AMD issue tracker[1][2].

[1] https://gitlab.freedesktop.org/drm/amd/-/issues/1734
[2] https://gitlab.freedesktop.org/drm/amd/-/issues/1769

Signed-off-by: Melissa Wen <mwen@igalia.com>
---
 drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h | 91 +++++++++++++++++----
 1 file changed, 77 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h b/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h
index 5097037e3962..cf28b841c42d 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h
@@ -22,6 +22,16 @@
  *
  */
 
+/**
+ * DOC: mpc-overview
+ *
+ * Multiple Pipe/Plane Combined (MPC) is a component in the hardware pipeline
+ * that performs blending of multiple planes, using global and per-pixel alpha.
+ * It also performs post-blending color correction operations according to the
+ * hardware capabilities, such as color transformation matrix and gamma 1D and
+ * 3D LUT.
+ */
+
 #ifndef __DC_MPCC_H__
 #define __DC_MPCC_H__
 
@@ -48,14 +58,39 @@ enum mpcc_blend_mode {
 	MPCC_BLEND_MODE_TOP_BOT_BLENDING
 };
 
+/**
+ * enum mpcc_alpha_blend_mode - define the alpha blend mode regarding pixel
+ * alpha and plane alpha values
+ */
 enum mpcc_alpha_blend_mode {
+	/**
+	 * @MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA: per pixel alpha using DPP
+	 * alpha value
+	 */
 	MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA,
+	/**
+	 * @MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN: per
+	 * pixel alpha using DPP alpha value multiplied by a global gain (plane
+	 * alpha)
+	 */
 	MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN,
+	/**
+	 * @MPCC_ALPHA_BLEND_MODE_GLOBAL_ALPHA: global alpha value, ignores
+	 * pixel alpha and consider only plane alpha
+	 */
 	MPCC_ALPHA_BLEND_MODE_GLOBAL_ALPHA
 };
 
-/*
- * MPCC blending configuration
+/**
+ * struct mpcc_blnd_cfg - MPCC blending configuration
+ *
+ * @black_color: background color
+ * @alpha_mode: alpha blend mode (MPCC_ALPHA_BLND_MODE)
+ * @pre_multiplied_alpha: whether pixel color values were pre-multiplied by the
+ * alpha channel (MPCC_ALPHA_MULTIPLIED_MODE)
+ * @global_gain: used when blend mode considers both pixel alpha and plane
+ * alpha value and assumes the global alpha value.
+ * @global_alpha: plane alpha value
  */
 struct mpcc_blnd_cfg {
 	struct tg_color black_color;	/* background color */
@@ -107,8 +142,15 @@ struct mpc_dwb_flow_control {
 	int flow_ctrl_cnt1;
 };
 
-/*
- * MPCC connection and blending configuration for a single MPCC instance.
+/**
+ * struct mpcc - MPCC connection and blending configuration for a single MPCC instance.
+ * @mpcc_id: MPCC physical instance
+ * @dpp_id: DPP input to this MPCC
+ * @mpcc_bot: pointer to bottom layer MPCC. NULL when not connected.
+ * @blnd_cfg: the blending configuration for this MPCC
+ * @sm_cfg: stereo mix setting for this MPCC
+ * @shared_bottom: if MPCC output to both OPP and DWB endpoints, true. Othewise, false.
+ *
  * This struct is used as a node in an MPC tree.
  */
 struct mpcc {
@@ -120,8 +162,12 @@ struct mpcc {
 	bool shared_bottom;		/* TRUE if MPCC output to both OPP and DWB endpoints, else FALSE */
 };
 
-/*
- * MPC tree represents all MPCC connections for a pipe.
+/**
+ * struct mpc_tree - MPC tree represents all MPCC connections for a pipe.
+ *
+ * @opp_id: the OPP instance that owns this MPC tree
+ * @opp_list: the top MPCC layer of the MPC tree that outputs to OPP endpoint
+ *
  */
 struct mpc_tree {
 	int opp_id;			/* The OPP instance that owns this MPC tree */
@@ -149,13 +195,18 @@ struct mpcc_state {
 	uint32_t busy;
 };
 
+/**
+ * struct mpc_funcs - funcs
+ */
 struct mpc_funcs {
 	void (*read_mpcc_state)(
 			struct mpc *mpc,
 			int mpcc_inst,
 			struct mpcc_state *s);
 
-	/*
+	/**
+	 * @insert_plane:
+	 *
 	 * Insert DPP into MPC tree based on specified blending position.
 	 * Only used for planes that are part of blending chain for OPP output
 	 *
@@ -180,7 +231,9 @@ struct mpc_funcs {
 			int dpp_id,
 			int mpcc_id);
 
-	/*
+	/**
+	 * @remove_mpcc:
+	 *
 	 * Remove a specified MPCC from the MPC tree.
 	 *
 	 * Parameters:
@@ -195,7 +248,9 @@ struct mpc_funcs {
 			struct mpc_tree *tree,
 			struct mpcc *mpcc);
 
-	/*
+	/**
+	 * @mpc_init:
+	 *
 	 * Reset the MPCC HW status by disconnecting all muxes.
 	 *
 	 * Parameters:
@@ -208,7 +263,9 @@ struct mpc_funcs {
 			struct mpc *mpc,
 			unsigned int mpcc_id);
 
-	/*
+	/**
+	 * @update_blending:
+	 *
 	 * Update the blending configuration for a specified MPCC.
 	 *
 	 * Parameters:
@@ -223,7 +280,9 @@ struct mpc_funcs {
 		struct mpcc_blnd_cfg *blnd_cfg,
 		int mpcc_id);
 
-	/*
+	/**
+	 * @cursor_lock:
+	 *
 	 * Lock cursor updates for the specified OPP.
 	 * OPP defines the set of MPCC that are locked together for cursor.
 	 *
@@ -239,8 +298,10 @@ struct mpc_funcs {
 			int opp_id,
 			bool lock);
 
-	/*
-	 * Add DPP into 'secondary' MPC tree based on specified blending position.
+	/**
+	 * @insert_plane_to_secondary:
+	 *
+	 * Add DPP into secondary MPC tree based on specified blending position.
 	 * Only used for planes that are part of blending chain for DWB output
 	 *
 	 * Parameters:
@@ -264,7 +325,9 @@ struct mpc_funcs {
 			int dpp_id,
 			int mpcc_id);
 
-	/*
+	/**
+	 * @remove_mpcc_from_secondary:
+	 *
 	 * Remove a specified DPP from the 'secondary' MPC tree.
 	 *
 	 * Parameters:
-- 
2.35.1

Re: [PATCH 3/4] drm/amd/display: add doc entries for MPC blending configuration

[Tales Lelo da Aparecida]

On 16/07/2022 19:25, Melissa Wen wrote:
> Describe structs and enums used to set blend mode properties to MPC
> blocks. Some pieces of information are already available as code
> comments, and were just formatted. Others were collected and summarised
> from discusssions on AMD issue tracker[1][2].

Typo in the commit message: discusssions -> discussions

> 
> [1] https://gitlab.freedesktop.org/drm/amd/-/issues/1734
> [2] https://gitlab.freedesktop.org/drm/amd/-/issues/1769
> 
> Signed-off-by: Melissa Wen <mwen@igalia.com>
> ---
>   drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h | 91 +++++++++++++++++----
>   1 file changed, 77 insertions(+), 14 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h b/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h
> index 5097037e3962..cf28b841c42d 100644
> --- a/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h
> +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h
> @@ -22,6 +22,16 @@
>    *
>    */
>   
> +/**
> + * DOC: mpc-overview
> + *
> + * Multiple Pipe/Plane Combined (MPC) is a component in the hardware pipeline
> + * that performs blending of multiple planes, using global and per-pixel alpha.
> + * It also performs post-blending color correction operations according to the
> + * hardware capabilities, such as color transformation matrix and gamma 1D and
> + * 3D LUT.
> + */
> +
>   #ifndef __DC_MPCC_H__
>   #define __DC_MPCC_H__
>   
> @@ -48,14 +58,39 @@ enum mpcc_blend_mode {
>   	MPCC_BLEND_MODE_TOP_BOT_BLENDING
>   };
>   
> +/**
> + * enum mpcc_alpha_blend_mode - define the alpha blend mode regarding pixel
> + * alpha and plane alpha values
> + */
>   enum mpcc_alpha_blend_mode {
> +	/**
> +	 * @MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA: per pixel alpha using DPP
> +	 * alpha value
> +	 */
>   	MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA,
> +	/**
> +	 * @MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN: per
> +	 * pixel alpha using DPP alpha value multiplied by a global gain (plane
> +	 * alpha)
> +	 */
>   	MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN,
> +	/**
> +	 * @MPCC_ALPHA_BLEND_MODE_GLOBAL_ALPHA: global alpha value, ignores
> +	 * pixel alpha and consider only plane alpha
> +	 */
>   	MPCC_ALPHA_BLEND_MODE_GLOBAL_ALPHA
>   };
>   
> -/*
> - * MPCC blending configuration
> +/**
> + * struct mpcc_blnd_cfg - MPCC blending configuration
> + *
> + * @black_color: background color
> + * @alpha_mode: alpha blend mode (MPCC_ALPHA_BLND_MODE)
> + * @pre_multiplied_alpha: whether pixel color values were pre-multiplied by the
> + * alpha channel (MPCC_ALPHA_MULTIPLIED_MODE)
> + * @global_gain: used when blend mode considers both pixel alpha and plane
> + * alpha value and assumes the global alpha value.
> + * @global_alpha: plane alpha value

There's quite a few members missing definition. After reading the 4th 
patch may I conclude that they weren't relevant for what's being 
described about alpha blending?

./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h:109: warning: Function 
parameter or member 'overlap_only' not described in 'mpcc_blnd_cfg'
./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h:109: warning: Function 
parameter or member 'bottom_gain_mode' not described in 'mpcc_blnd_cfg'
./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h:109: warning: Function 
parameter or member 'background_color_bpc' not described in 'mpcc_blnd_cfg'
./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h:109: warning: Function 
parameter or member 'top_gain' not described in 'mpcc_blnd_cfg'
./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h:109: warning: Function 
parameter or member 'bottom_inside_gain' not described in 'mpcc_blnd_cfg'
./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h:109: warning: Function 
parameter or member 'bottom_outside_gain' not described in 'mpcc_blnd_cfg'

>    */
>   struct mpcc_blnd_cfg {
>   	struct tg_color black_color;	/* background color */
> @@ -107,8 +142,15 @@ struct mpc_dwb_flow_control {
>   	int flow_ctrl_cnt1;
>   };
>   
> -/*
> - * MPCC connection and blending configuration for a single MPCC instance.
> +/**
> + * struct mpcc - MPCC connection and blending configuration for a single MPCC instance.

Might be worth writing the definition of the abbreviation, if not here, 
in the glossary... I couldn't find what the last "C" stands for, my 
guess would be "context". hehehe

> + * @mpcc_id: MPCC physical instance
> + * @dpp_id: DPP input to this MPCC
> + * @mpcc_bot: pointer to bottom layer MPCC. NULL when not connected.
> + * @blnd_cfg: the blending configuration for this MPCC
> + * @sm_cfg: stereo mix setting for this MPCC
> + * @shared_bottom: if MPCC output to both OPP and DWB endpoints, true. Othewise, false.

Typo Othewise -> Otherwise

> + *
>    * This struct is used as a node in an MPC tree.
>    */
>   struct mpcc {
> @@ -120,8 +162,12 @@ struct mpcc {
>   	bool shared_bottom;		/* TRUE if MPCC output to both OPP and DWB endpoints, else FALSE */
>   };
>   
> -/*
> - * MPC tree represents all MPCC connections for a pipe.
> +/**
> + * struct mpc_tree - MPC tree represents all MPCC connections for a pipe.
> + *
> + * @opp_id: the OPP instance that owns this MPC tree
> + * @opp_list: the top MPCC layer of the MPC tree that outputs to OPP endpoint
> + *
>    */
>   struct mpc_tree {
>   	int opp_id;			/* The OPP instance that owns this MPC tree */
> @@ -149,13 +195,18 @@ struct mpcc_state {
>   	uint32_t busy;
>   };
>   
> +/**
> + * struct mpc_funcs - funcs
> + */
>   struct mpc_funcs {
>   	void (*read_mpcc_state)(
>   			struct mpc *mpc,
>   			int mpcc_inst,
>   			struct mpcc_state *s);
>   
> -	/*
> +	/**
> +	 * @insert_plane:
> +	 *
>   	 * Insert DPP into MPC tree based on specified blending position.
>   	 * Only used for planes that are part of blending chain for OPP output
>   	 *
> @@ -180,7 +231,9 @@ struct mpc_funcs {
>   			int dpp_id,
>   			int mpcc_id);
>   
> -	/*
> +	/**
> +	 * @remove_mpcc:
> +	 *
>   	 * Remove a specified MPCC from the MPC tree.
>   	 *
>   	 * Parameters:
> @@ -195,7 +248,9 @@ struct mpc_funcs {
>   			struct mpc_tree *tree,
>   			struct mpcc *mpcc);
>   
> -	/*
> +	/**
> +	 * @mpc_init:
> +	 *
>   	 * Reset the MPCC HW status by disconnecting all muxes.
>   	 *
>   	 * Parameters:
> @@ -208,7 +263,9 @@ struct mpc_funcs {
>   			struct mpc *mpc,
>   			unsigned int mpcc_id);
>   
> -	/*
> +	/**
> +	 * @update_blending:
> +	 *
>   	 * Update the blending configuration for a specified MPCC.
>   	 *
>   	 * Parameters:
> @@ -223,7 +280,9 @@ struct mpc_funcs {
>   		struct mpcc_blnd_cfg *blnd_cfg,
>   		int mpcc_id);
>   
> -	/*
> +	/**
> +	 * @cursor_lock:
> +	 *
>   	 * Lock cursor updates for the specified OPP.
>   	 * OPP defines the set of MPCC that are locked together for cursor.
>   	 *
> @@ -239,8 +298,10 @@ struct mpc_funcs {
>   			int opp_id,
>   			bool lock);
>   
> -	/*
> -	 * Add DPP into 'secondary' MPC tree based on specified blending position.
> +	/**
> +	 * @insert_plane_to_secondary:
> +	 *
> +	 * Add DPP into secondary MPC tree based on specified blending position.
>   	 * Only used for planes that are part of blending chain for DWB output
>   	 *
>   	 * Parameters:
> @@ -264,7 +325,9 @@ struct mpc_funcs {
>   			int dpp_id,
>   			int mpcc_id);
>   
> -	/*
> +	/**
> +	 * @remove_mpcc_from_secondary:
> +	 *
>   	 * Remove a specified DPP from the 'secondary' MPC tree.
>   	 *
>   	 * Parameters:

Thanks for the patch,
Tales Aparecida

Re: [PATCH 3/4] drm/amd/display: add doc entries for MPC blending configuration

[Melissa Wen]

[-- Attachment #1.1: Type: text/plain, Size: 8380 bytes --]

On 07/17, Tales Lelo da Aparecida wrote:
> On 16/07/2022 19:25, Melissa Wen wrote:
> > Describe structs and enums used to set blend mode properties to MPC
> > blocks. Some pieces of information are already available as code
> > comments, and were just formatted. Others were collected and summarised
> > from discusssions on AMD issue tracker[1][2].
> 
> Typo in the commit message: discusssions -> discussions
> 
> > 
> > [1] https://gitlab.freedesktop.org/drm/amd/-/issues/1734
> > [2] https://gitlab.freedesktop.org/drm/amd/-/issues/1769
> > 
> > Signed-off-by: Melissa Wen <mwen@igalia.com>
> > ---
> >   drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h | 91 +++++++++++++++++----
> >   1 file changed, 77 insertions(+), 14 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h b/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h
> > index 5097037e3962..cf28b841c42d 100644
> > --- a/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h
> > +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h
> > @@ -22,6 +22,16 @@
> >    *
> >    */
> > +/**
> > + * DOC: mpc-overview
> > + *
> > + * Multiple Pipe/Plane Combined (MPC) is a component in the hardware pipeline
> > + * that performs blending of multiple planes, using global and per-pixel alpha.
> > + * It also performs post-blending color correction operations according to the
> > + * hardware capabilities, such as color transformation matrix and gamma 1D and
> > + * 3D LUT.
> > + */
> > +
> >   #ifndef __DC_MPCC_H__
> >   #define __DC_MPCC_H__
> > @@ -48,14 +58,39 @@ enum mpcc_blend_mode {
> >   	MPCC_BLEND_MODE_TOP_BOT_BLENDING
> >   };
> > +/**
> > + * enum mpcc_alpha_blend_mode - define the alpha blend mode regarding pixel
> > + * alpha and plane alpha values
> > + */
> >   enum mpcc_alpha_blend_mode {
> > +	/**
> > +	 * @MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA: per pixel alpha using DPP
> > +	 * alpha value
> > +	 */
> >   	MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA,
> > +	/**
> > +	 * @MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN: per
> > +	 * pixel alpha using DPP alpha value multiplied by a global gain (plane
> > +	 * alpha)
> > +	 */
> >   	MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN,
> > +	/**
> > +	 * @MPCC_ALPHA_BLEND_MODE_GLOBAL_ALPHA: global alpha value, ignores
> > +	 * pixel alpha and consider only plane alpha
> > +	 */
> >   	MPCC_ALPHA_BLEND_MODE_GLOBAL_ALPHA
> >   };
> > -/*
> > - * MPCC blending configuration
> > +/**
> > + * struct mpcc_blnd_cfg - MPCC blending configuration
> > + *
> > + * @black_color: background color
> > + * @alpha_mode: alpha blend mode (MPCC_ALPHA_BLND_MODE)
> > + * @pre_multiplied_alpha: whether pixel color values were pre-multiplied by the
> > + * alpha channel (MPCC_ALPHA_MULTIPLIED_MODE)
> > + * @global_gain: used when blend mode considers both pixel alpha and plane
> > + * alpha value and assumes the global alpha value.
> > + * @global_alpha: plane alpha value
> 
> There's quite a few members missing definition. After reading the 4th patch
> may I conclude that they weren't relevant for what's being described about
> alpha blending?

Hi Tales,

although they aren't changed for DRM blend modes programming, it would
be nice if someone can describe them and also avoid those warnings. I
wasn't able to identify how they behave for MPC programming (hope
someone from AMD can help on documenting them).

> 
> ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h:109: warning: Function
> parameter or member 'overlap_only' not described in 'mpcc_blnd_cfg'
> ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h:109: warning: Function
> parameter or member 'bottom_gain_mode' not described in 'mpcc_blnd_cfg'
> ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h:109: warning: Function
> parameter or member 'background_color_bpc' not described in 'mpcc_blnd_cfg'
> ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h:109: warning: Function
> parameter or member 'top_gain' not described in 'mpcc_blnd_cfg'
> ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h:109: warning: Function
> parameter or member 'bottom_inside_gain' not described in 'mpcc_blnd_cfg'
> ./drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h:109: warning: Function
> parameter or member 'bottom_outside_gain' not described in 'mpcc_blnd_cfg'
> 
> >    */
> >   struct mpcc_blnd_cfg {
> >   	struct tg_color black_color;	/* background color */
> > @@ -107,8 +142,15 @@ struct mpc_dwb_flow_control {
> >   	int flow_ctrl_cnt1;
> >   };
> > -/*
> > - * MPCC connection and blending configuration for a single MPCC instance.
> > +/**
> > + * struct mpcc - MPCC connection and blending configuration for a single MPCC instance.
> 
> Might be worth writing the definition of the abbreviation, if not here, in
> the glossary... I couldn't find what the last "C" stands for, my guess would
> be "context". hehehe
> 
> > + * @mpcc_id: MPCC physical instance
> > + * @dpp_id: DPP input to this MPCC
> > + * @mpcc_bot: pointer to bottom layer MPCC. NULL when not connected.
> > + * @blnd_cfg: the blending configuration for this MPCC
> > + * @sm_cfg: stereo mix setting for this MPCC
> > + * @shared_bottom: if MPCC output to both OPP and DWB endpoints, true. Othewise, false.
> 
> Typo Othewise -> Otherwise
> 
> > + *
> >    * This struct is used as a node in an MPC tree.
> >    */
> >   struct mpcc {
> > @@ -120,8 +162,12 @@ struct mpcc {
> >   	bool shared_bottom;		/* TRUE if MPCC output to both OPP and DWB endpoints, else FALSE */
> >   };
> > -/*
> > - * MPC tree represents all MPCC connections for a pipe.
> > +/**
> > + * struct mpc_tree - MPC tree represents all MPCC connections for a pipe.
> > + *
> > + * @opp_id: the OPP instance that owns this MPC tree
> > + * @opp_list: the top MPCC layer of the MPC tree that outputs to OPP endpoint
> > + *
> >    */
> >   struct mpc_tree {
> >   	int opp_id;			/* The OPP instance that owns this MPC tree */
> > @@ -149,13 +195,18 @@ struct mpcc_state {
> >   	uint32_t busy;
> >   };
> > +/**
> > + * struct mpc_funcs - funcs
> > + */
> >   struct mpc_funcs {
> >   	void (*read_mpcc_state)(
> >   			struct mpc *mpc,
> >   			int mpcc_inst,
> >   			struct mpcc_state *s);
> > -	/*
> > +	/**
> > +	 * @insert_plane:
> > +	 *
> >   	 * Insert DPP into MPC tree based on specified blending position.
> >   	 * Only used for planes that are part of blending chain for OPP output
> >   	 *
> > @@ -180,7 +231,9 @@ struct mpc_funcs {
> >   			int dpp_id,
> >   			int mpcc_id);
> > -	/*
> > +	/**
> > +	 * @remove_mpcc:
> > +	 *
> >   	 * Remove a specified MPCC from the MPC tree.
> >   	 *
> >   	 * Parameters:
> > @@ -195,7 +248,9 @@ struct mpc_funcs {
> >   			struct mpc_tree *tree,
> >   			struct mpcc *mpcc);
> > -	/*
> > +	/**
> > +	 * @mpc_init:
> > +	 *
> >   	 * Reset the MPCC HW status by disconnecting all muxes.
> >   	 *
> >   	 * Parameters:
> > @@ -208,7 +263,9 @@ struct mpc_funcs {
> >   			struct mpc *mpc,
> >   			unsigned int mpcc_id);
> > -	/*
> > +	/**
> > +	 * @update_blending:
> > +	 *
> >   	 * Update the blending configuration for a specified MPCC.
> >   	 *
> >   	 * Parameters:
> > @@ -223,7 +280,9 @@ struct mpc_funcs {
> >   		struct mpcc_blnd_cfg *blnd_cfg,
> >   		int mpcc_id);
> > -	/*
> > +	/**
> > +	 * @cursor_lock:
> > +	 *
> >   	 * Lock cursor updates for the specified OPP.
> >   	 * OPP defines the set of MPCC that are locked together for cursor.
> >   	 *
> > @@ -239,8 +298,10 @@ struct mpc_funcs {
> >   			int opp_id,
> >   			bool lock);
> > -	/*
> > -	 * Add DPP into 'secondary' MPC tree based on specified blending position.
> > +	/**
> > +	 * @insert_plane_to_secondary:
> > +	 *
> > +	 * Add DPP into secondary MPC tree based on specified blending position.
> >   	 * Only used for planes that are part of blending chain for DWB output
> >   	 *
> >   	 * Parameters:
> > @@ -264,7 +325,9 @@ struct mpc_funcs {
> >   			int dpp_id,
> >   			int mpcc_id);
> > -	/*
> > +	/**
> > +	 * @remove_mpcc_from_secondary:
> > +	 *
> >   	 * Remove a specified DPP from the 'secondary' MPC tree.
> >   	 *
> >   	 * Parameters:
> 
> Thanks for the patch,
> Tales Aparecida

Thanks for reviewing them. I'll address your suggestions in the next
version.

Melissa


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[PATCH 4/4] Documentation/gpu/amdgpu/amdgpu_dm: add DM docs for pixel blend mode

[Melissa Wen]

AMD GPU display manager (DM) maps DRM pixel blend modes (None,
Pre-multiplied, Coverage) to MPC hw blocks through blend configuration
options. Describe relevant elements and how to set and test them to get
the expected DRM blend mode on DCN hw.

Signed-off-by: Melissa Wen <mwen@igalia.com>
---
 .../gpu/amdgpu/display/display-manager.rst    | 98 +++++++++++++++++++
 Documentation/gpu/drm-kms.rst                 |  2 +
 2 files changed, 100 insertions(+)

diff --git a/Documentation/gpu/amdgpu/display/display-manager.rst b/Documentation/gpu/amdgpu/display/display-manager.rst
index 8960a5f1fa66..7a495ed1f69e 100644
--- a/Documentation/gpu/amdgpu/display/display-manager.rst
+++ b/Documentation/gpu/amdgpu/display/display-manager.rst
@@ -84,3 +84,101 @@ families below.
 **DCN 3.0 family color caps and mapping**
 
 .. kernel-figure:: dcn3_cm_drm_current.svg
+
+Blend Mode Properties
+=====================
+
+Pixel blend mode is a DRM plane composition property of :c:type:`drm_plane` used to
+describes how pixels from a foreground plane (fg) are composited with the
+background plane (bg). Here, we present main concepts of DRM blend mode to help
+to understand how this property is mapped to AMD DC interface. See more about
+this DRM property and the alpha blending equations in :ref:`DRM Plane
+Composition Properties <plane_composition_properties>`.
+
+Basically, a blend mode sets the alpha blending equation for plane
+composition that fits the mode in which the alpha channel affects the state of
+pixel color values and, therefore, the resulted pixel color. For
+example, consider the following elements of the alpha blending equation:
+
+- *fg.rgb*: Each of the RGB component values from the foreground's pixel.
+- *fg.alpha*: Alpha component value from the foreground's pixel.
+- *bg.rgb*: Each of the RGB component values from the background.
+- *plane_alpha*: Plane alpha value set by the **plane "alpha" property**, see
+  more in `DRM Plane Composition Properties <plane_composition_properties>`.
+
+in the basic alpha blending equation::
+
+   out.rgb = alpha * fg.rgb + (1 - alpha) * bg.rgb
+
+the alpha channel value of each pixel in a plane is ignored and only the plane
+alpha affects the resulted pixel color values.
+
+DRM has three blend mode to define the blend formula in the plane composition:
+
+* **None**: Blend formula that ignores the pixel alpha.
+
+* **Pre-multiplied**: Blend formula that assumes the pixel color values in a
+  plane was already pre-multiplied by its own alpha channel before storage.
+
+* **Coverage**: Blend formula that assumes the pixel color values were not
+  pre-multiplied with the alpha channel values.
+
+and pre-multiplied is the default pixel blend mode, that means, when no blend
+mode property is created or defined, DRM considers the plane's pixels has
+pre-multiplied color values. On IGT GPU tools, the kms_plane_alpha_blend test
+provides a set of subtests to verify plane alpha and blend mode properties.
+
+The DRM blend mode and its elements are then mapped by AMDGPU display manager
+(DM) to program the blending configuration of the Multiple Pipe/Plane Combined
+(MPC), as follows:
+
+.. kernel-doc:: drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h
+   :doc: mpc-overview
+
+.. kernel-doc:: drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h
+   :functions: mpcc_blnd_cfg
+
+Therefore, the blending configuration for a single MPCC instance on the MPC
+tree is defined by :c:type:`mpcc_blnd_cfg`, where
+:c:type:`pre_multiplied_alpha` is the alpha pre-multiplied mode flag used to
+set :c:type:`MPCC_ALPHA_MULTIPLIED_MODE`. It controls whether alpha is
+multiplied (true/false), being only true for DRM pre-multiplied blend mode.
+:c:type:`mpcc_alpha_blend_mode` defines the alpha blend mode regarding pixel
+alpha and plane alpha values. It sets one of the three modes for
+:c:type:`MPCC_ALPHA_BLND_MODE`, as described below.
+
+.. kernel-doc:: drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h
+   :functions: mpcc_alpha_blend_mode
+
+DM then maps the elements of `enum mpcc_alpha_blend_mode` to those in the DRM
+blend formula, as follows:
+
+* *MPC pixel alpha* matches *DRM fg.alpha* as the alpha component value
+  from the plane's pixel
+* *MPC global alpha* matches *DRM plane_alpha* when the pixel alpha should
+  be ignored and, therefore, pixel values are not pre-multiplied
+* *MPC global gain* assumes *MPC global alpha* value when both *DRM
+  fg.alpha* and *DRM plane_alpha* participate in the blend equation
+
+In short, *fg.alpha* is ignored by selecting
+:c:type:`MPCC_ALPHA_BLEND_MODE_GLOBAL_ALPHA`. On the other hand, (plane_alpha *
+fg.alpha) component becomes available by selecting
+:c:type:`MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN`. And the
+:c:type:`MPCC_ALPHA_MULTIPLIED_MODE` defines if the pixel color values are
+pre-multiplied by alpha or not.
+
+Blend configuration flow
+------------------------
+
+The alpha blending equation is configured from DRM to DC interface by the
+following path:
+
+1. When updating a :c:type:`drm_plane_state <drm_plane_state>`, DM calls
+   :c:type:`fill_blending_from_plane_state()` that maps
+   :c:type:`drm_plane_state <drm_plane_state>` attributes to
+   :c:type:`dc_plane_info <dc_plane_info>` struct to be handled in the
+   OS-agnostic component (DC).
+
+2. On DC interface, :c:type:`struct mpcc_blnd_cfg <mpcc_blnd_cfg>` programs the
+   MPCC blend configuration considering the :c:type:`dc_plane_info
+   <dc_plane_info>` input from DPP.
diff --git a/Documentation/gpu/drm-kms.rst b/Documentation/gpu/drm-kms.rst
index d14bf1c35d7e..7ec9dbe18b65 100644
--- a/Documentation/gpu/drm-kms.rst
+++ b/Documentation/gpu/drm-kms.rst
@@ -532,6 +532,8 @@ Standard Plane Properties
 .. kernel-doc:: drivers/gpu/drm/drm_plane.c
    :doc: standard plane properties
 
+.. _plane_composition_properties:
+
 Plane Composition Properties
 ----------------------------
 
-- 
2.35.1

Re: [PATCH 4/4] Documentation/gpu/amdgpu/amdgpu_dm: add DM docs for pixel blend mode

[Tales Lelo da Aparecida]

On 16/07/2022 19:25, Melissa Wen wrote:
> AMD GPU display manager (DM) maps DRM pixel blend modes (None,
> Pre-multiplied, Coverage) to MPC hw blocks through blend configuration
> options. Describe relevant elements and how to set and test them to get
> the expected DRM blend mode on DCN hw.
> 
> Signed-off-by: Melissa Wen <mwen@igalia.com>
> ---
>   .../gpu/amdgpu/display/display-manager.rst    | 98 +++++++++++++++++++
>   Documentation/gpu/drm-kms.rst                 |  2 +
>   2 files changed, 100 insertions(+)
> 
> diff --git a/Documentation/gpu/amdgpu/display/display-manager.rst b/Documentation/gpu/amdgpu/display/display-manager.rst
> index 8960a5f1fa66..7a495ed1f69e 100644
> --- a/Documentation/gpu/amdgpu/display/display-manager.rst
> +++ b/Documentation/gpu/amdgpu/display/display-manager.rst
> @@ -84,3 +84,101 @@ families below.
>   **DCN 3.0 family color caps and mapping**
>   
>   .. kernel-figure:: dcn3_cm_drm_current.svg
> +
> +Blend Mode Properties
> +=====================
> +
> +Pixel blend mode is a DRM plane composition property of :c:type:`drm_plane` used to
> +describes how pixels from a foreground plane (fg) are composited with the
> +background plane (bg). Here, we present main concepts of DRM blend mode to help
> +to understand how this property is mapped to AMD DC interface. See more about
> +this DRM property and the alpha blending equations in :ref:`DRM Plane
> +Composition Properties <plane_composition_properties>`.
> +
> +Basically, a blend mode sets the alpha blending equation for plane
> +composition that fits the mode in which the alpha channel affects the state of
> +pixel color values and, therefore, the resulted pixel color. For
> +example, consider the following elements of the alpha blending equation:
> +
> +- *fg.rgb*: Each of the RGB component values from the foreground's pixel.
> +- *fg.alpha*: Alpha component value from the foreground's pixel.
> +- *bg.rgb*: Each of the RGB component values from the background.
> +- *plane_alpha*: Plane alpha value set by the **plane "alpha" property**, see
> +  more in `DRM Plane Composition Properties <plane_composition_properties>`.

You forgot to use :ref: in here.

> +
> +in the basic alpha blending equation::
> +
> +   out.rgb = alpha * fg.rgb + (1 - alpha) * bg.rgb
> +
> +the alpha channel value of each pixel in a plane is ignored and only the plane
> +alpha affects the resulted pixel color values.
> +
> +DRM has three blend mode to define the blend formula in the plane composition:
> +
> +* **None**: Blend formula that ignores the pixel alpha.
> +
> +* **Pre-multiplied**: Blend formula that assumes the pixel color values in a
> +  plane was already pre-multiplied by its own alpha channel before storage.
> +
> +* **Coverage**: Blend formula that assumes the pixel color values were not
> +  pre-multiplied with the alpha channel values.
> +
> +and pre-multiplied is the default pixel blend mode, that means, when no blend
> +mode property is created or defined, DRM considers the plane's pixels has
> +pre-multiplied color values. On IGT GPU tools, the kms_plane_alpha_blend test
> +provides a set of subtests to verify plane alpha and blend mode properties.
> +
> +The DRM blend mode and its elements are then mapped by AMDGPU display manager
> +(DM) to program the blending configuration of the Multiple Pipe/Plane Combined
> +(MPC), as follows:
> +
> +.. kernel-doc:: drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h
> +   :doc: mpc-overview
> +
> +.. kernel-doc:: drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h
> +   :functions: mpcc_blnd_cfg
> +
> +Therefore, the blending configuration for a single MPCC instance on the MPC
> +tree is defined by :c:type:`mpcc_blnd_cfg`, where
> +:c:type:`pre_multiplied_alpha` is the alpha pre-multiplied mode flag used to
> +set :c:type:`MPCC_ALPHA_MULTIPLIED_MODE`. It controls whether alpha is
> +multiplied (true/false), being only true for DRM pre-multiplied blend mode.
> +:c:type:`mpcc_alpha_blend_mode` defines the alpha blend mode regarding pixel
> +alpha and plane alpha values. It sets one of the three modes for
> +:c:type:`MPCC_ALPHA_BLND_MODE`, as described below.
> +
> +.. kernel-doc:: drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h
> +   :functions: mpcc_alpha_blend_mode
> +
> +DM then maps the elements of `enum mpcc_alpha_blend_mode` to those in the DRM
> +blend formula, as follows:
> +
> +* *MPC pixel alpha* matches *DRM fg.alpha* as the alpha component value
> +  from the plane's pixel
> +* *MPC global alpha* matches *DRM plane_alpha* when the pixel alpha should
> +  be ignored and, therefore, pixel values are not pre-multiplied
> +* *MPC global gain* assumes *MPC global alpha* value when both *DRM
> +  fg.alpha* and *DRM plane_alpha* participate in the blend equation
> +
> +In short, *fg.alpha* is ignored by selecting
> +:c:type:`MPCC_ALPHA_BLEND_MODE_GLOBAL_ALPHA`. On the other hand, (plane_alpha *
> +fg.alpha) component becomes available by selecting
> +:c:type:`MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN`. And the
> +:c:type:`MPCC_ALPHA_MULTIPLIED_MODE` defines if the pixel color values are
> +pre-multiplied by alpha or not.
> +
> +Blend configuration flow
> +------------------------
> +
> +The alpha blending equation is configured from DRM to DC interface by the
> +following path:
> +
> +1. When updating a :c:type:`drm_plane_state <drm_plane_state>`, DM calls
> +   :c:type:`fill_blending_from_plane_state()` that maps
> +   :c:type:`drm_plane_state <drm_plane_state>` attributes to
> +   :c:type:`dc_plane_info <dc_plane_info>` struct to be handled in the
> +   OS-agnostic component (DC).
> +
> +2. On DC interface, :c:type:`struct mpcc_blnd_cfg <mpcc_blnd_cfg>` programs the
> +   MPCC blend configuration considering the :c:type:`dc_plane_info
> +   <dc_plane_info>` input from DPP.
> diff --git a/Documentation/gpu/drm-kms.rst b/Documentation/gpu/drm-kms.rst
> index d14bf1c35d7e..7ec9dbe18b65 100644
> --- a/Documentation/gpu/drm-kms.rst
> +++ b/Documentation/gpu/drm-kms.rst
> @@ -532,6 +532,8 @@ Standard Plane Properties
>   .. kernel-doc:: drivers/gpu/drm/drm_plane.c
>      :doc: standard plane properties
>   
> +.. _plane_composition_properties:
> +
>   Plane Composition Properties
>   ----------------------------
>   

 From a beginner's perspective, the changes from this series are 
readable, but I cannot tell if there are any technical mistakes. So,
regarding readability and rendering htmldocs, apart from the nits I've 
raised, this whole series is

Reviewed-by: Tales Aparecida <tales.aparecida@gmail.com>

Thanks for the patch series, Melissa,
Tales Aparecida

Re: [PATCH 4/4] Documentation/gpu/amdgpu/amdgpu_dm: add DM docs for pixel blend mode

[Melissa Wen]

[-- Attachment #1: Type: text/plain, Size: 7218 bytes --]

On 07/17, Tales Lelo da Aparecida wrote:
> On 16/07/2022 19:25, Melissa Wen wrote:
> > AMD GPU display manager (DM) maps DRM pixel blend modes (None,
> > Pre-multiplied, Coverage) to MPC hw blocks through blend configuration
> > options. Describe relevant elements and how to set and test them to get
> > the expected DRM blend mode on DCN hw.
> > 
> > Signed-off-by: Melissa Wen <mwen@igalia.com>
> > ---
> >   .../gpu/amdgpu/display/display-manager.rst    | 98 +++++++++++++++++++
> >   Documentation/gpu/drm-kms.rst                 |  2 +
> >   2 files changed, 100 insertions(+)
> > 
> > diff --git a/Documentation/gpu/amdgpu/display/display-manager.rst b/Documentation/gpu/amdgpu/display/display-manager.rst
> > index 8960a5f1fa66..7a495ed1f69e 100644
> > --- a/Documentation/gpu/amdgpu/display/display-manager.rst
> > +++ b/Documentation/gpu/amdgpu/display/display-manager.rst
> > @@ -84,3 +84,101 @@ families below.
> >   **DCN 3.0 family color caps and mapping**
> >   .. kernel-figure:: dcn3_cm_drm_current.svg
> > +
> > +Blend Mode Properties
> > +=====================
> > +
> > +Pixel blend mode is a DRM plane composition property of :c:type:`drm_plane` used to
> > +describes how pixels from a foreground plane (fg) are composited with the
> > +background plane (bg). Here, we present main concepts of DRM blend mode to help
> > +to understand how this property is mapped to AMD DC interface. See more about
> > +this DRM property and the alpha blending equations in :ref:`DRM Plane
> > +Composition Properties <plane_composition_properties>`.
> > +
> > +Basically, a blend mode sets the alpha blending equation for plane
> > +composition that fits the mode in which the alpha channel affects the state of
> > +pixel color values and, therefore, the resulted pixel color. For
> > +example, consider the following elements of the alpha blending equation:
> > +
> > +- *fg.rgb*: Each of the RGB component values from the foreground's pixel.
> > +- *fg.alpha*: Alpha component value from the foreground's pixel.
> > +- *bg.rgb*: Each of the RGB component values from the background.
> > +- *plane_alpha*: Plane alpha value set by the **plane "alpha" property**, see
> > +  more in `DRM Plane Composition Properties <plane_composition_properties>`.
> 
> You forgot to use :ref: in here.
> 
> > +
> > +in the basic alpha blending equation::
> > +
> > +   out.rgb = alpha * fg.rgb + (1 - alpha) * bg.rgb
> > +
> > +the alpha channel value of each pixel in a plane is ignored and only the plane
> > +alpha affects the resulted pixel color values.
> > +
> > +DRM has three blend mode to define the blend formula in the plane composition:
> > +
> > +* **None**: Blend formula that ignores the pixel alpha.
> > +
> > +* **Pre-multiplied**: Blend formula that assumes the pixel color values in a
> > +  plane was already pre-multiplied by its own alpha channel before storage.
> > +
> > +* **Coverage**: Blend formula that assumes the pixel color values were not
> > +  pre-multiplied with the alpha channel values.
> > +
> > +and pre-multiplied is the default pixel blend mode, that means, when no blend
> > +mode property is created or defined, DRM considers the plane's pixels has
> > +pre-multiplied color values. On IGT GPU tools, the kms_plane_alpha_blend test
> > +provides a set of subtests to verify plane alpha and blend mode properties.
> > +
> > +The DRM blend mode and its elements are then mapped by AMDGPU display manager
> > +(DM) to program the blending configuration of the Multiple Pipe/Plane Combined
> > +(MPC), as follows:
> > +
> > +.. kernel-doc:: drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h
> > +   :doc: mpc-overview
> > +
> > +.. kernel-doc:: drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h
> > +   :functions: mpcc_blnd_cfg
> > +
> > +Therefore, the blending configuration for a single MPCC instance on the MPC
> > +tree is defined by :c:type:`mpcc_blnd_cfg`, where
> > +:c:type:`pre_multiplied_alpha` is the alpha pre-multiplied mode flag used to
> > +set :c:type:`MPCC_ALPHA_MULTIPLIED_MODE`. It controls whether alpha is
> > +multiplied (true/false), being only true for DRM pre-multiplied blend mode.
> > +:c:type:`mpcc_alpha_blend_mode` defines the alpha blend mode regarding pixel
> > +alpha and plane alpha values. It sets one of the three modes for
> > +:c:type:`MPCC_ALPHA_BLND_MODE`, as described below.
> > +
> > +.. kernel-doc:: drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h
> > +   :functions: mpcc_alpha_blend_mode
> > +
> > +DM then maps the elements of `enum mpcc_alpha_blend_mode` to those in the DRM
> > +blend formula, as follows:
> > +
> > +* *MPC pixel alpha* matches *DRM fg.alpha* as the alpha component value
> > +  from the plane's pixel
> > +* *MPC global alpha* matches *DRM plane_alpha* when the pixel alpha should
> > +  be ignored and, therefore, pixel values are not pre-multiplied
> > +* *MPC global gain* assumes *MPC global alpha* value when both *DRM
> > +  fg.alpha* and *DRM plane_alpha* participate in the blend equation
> > +
> > +In short, *fg.alpha* is ignored by selecting
> > +:c:type:`MPCC_ALPHA_BLEND_MODE_GLOBAL_ALPHA`. On the other hand, (plane_alpha *
> > +fg.alpha) component becomes available by selecting
> > +:c:type:`MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN`. And the
> > +:c:type:`MPCC_ALPHA_MULTIPLIED_MODE` defines if the pixel color values are
> > +pre-multiplied by alpha or not.
> > +
> > +Blend configuration flow
> > +------------------------
> > +
> > +The alpha blending equation is configured from DRM to DC interface by the
> > +following path:
> > +
> > +1. When updating a :c:type:`drm_plane_state <drm_plane_state>`, DM calls
> > +   :c:type:`fill_blending_from_plane_state()` that maps
> > +   :c:type:`drm_plane_state <drm_plane_state>` attributes to
> > +   :c:type:`dc_plane_info <dc_plane_info>` struct to be handled in the
> > +   OS-agnostic component (DC).
> > +
> > +2. On DC interface, :c:type:`struct mpcc_blnd_cfg <mpcc_blnd_cfg>` programs the
> > +   MPCC blend configuration considering the :c:type:`dc_plane_info
> > +   <dc_plane_info>` input from DPP.
> > diff --git a/Documentation/gpu/drm-kms.rst b/Documentation/gpu/drm-kms.rst
> > index d14bf1c35d7e..7ec9dbe18b65 100644
> > --- a/Documentation/gpu/drm-kms.rst
> > +++ b/Documentation/gpu/drm-kms.rst
> > @@ -532,6 +532,8 @@ Standard Plane Properties
> >   .. kernel-doc:: drivers/gpu/drm/drm_plane.c
> >      :doc: standard plane properties
> > +.. _plane_composition_properties:
> > +
> >   Plane Composition Properties
> >   ----------------------------
> 
> From a beginner's perspective, the changes from this series are readable,
> but I cannot tell if there are any technical mistakes. So,
> regarding readability and rendering htmldocs, apart from the nits I've
> raised, this whole series is
> 
> Reviewed-by: Tales Aparecida <tales.aparecida@gmail.com>
> 
> Thanks for the patch series, Melissa,

Hi Tales,

Thanks for taking a look at this series and reviewing it carefully.
Again, I'll address your comments in the next version.

Best Regards,

Melissa

> Tales Aparecida

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