Re: [PATCH v2 03/10] drm/amd/display: dc/core: add DCE6 support

From: "Wentland, Harry" <Harry.Wentland-5C7GfCeVMHo@public.gmane.org>
To: Mauro Rossi <issor.oruam-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>,
	"amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org"
	<amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org>
Cc: "Deucher,
	Alexander" <Alexander.Deucher-5C7GfCeVMHo@public.gmane.org>,
	"mike-4+n8WJKc9ve9FHfhHBbuYA@public.gmane.org"
	<mike-4+n8WJKc9ve9FHfhHBbuYA@public.gmane.org>,
	"sylvain.bertrand-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org"
	<sylvain.bertrand-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>,
	"ckoenig.leichtzumerken-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org"
	<ckoenig.leichtzumerken-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Subject: Re: [PATCH v2 03/10] drm/amd/display: dc/core: add DCE6 support
Date: Wed, 17 Oct 2018 19:53:56 +0000	[thread overview]
Message-ID: <cf3f8b07-5c66-e693-540a-a78697dfabce@amd.com> (raw)
In-Reply-To: <c7882ed4-9a83-8838-8966-c1f725fa4a18-5C7GfCeVMHo@public.gmane.org>


On 2018-10-17 3:50 p.m., Wentland, Harry wrote:
> On 2018-10-17 4:35 a.m., Mauro Rossi wrote:
>> DCE6 targets are added as branching of existing DCE8 implementation.
> 
> All your parents require a Signed-off-by. See https://www.kernel.org/doc/html/v4.17/process/submitting-patches.html#developer-s-certificate-of-origin-1-1

s/parents/patches

Harry

> 
> Harry
> 
>> ---
>>  .../gpu/drm/amd/display/dc/core/dc_resource.c | 29 +++++++++++++++++++
>>  1 file changed, 29 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
>> index a5eb80aa3dd9..07bd4f72acc5 100644
>> --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
>> +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
>> @@ -37,6 +37,9 @@
>>  #include "virtual/virtual_stream_encoder.h"
>>  #include "dpcd_defs.h"
>>  
>> +#if defined(CONFIG_DRM_AMD_DC_SI)
>> +#include "dce60/dce60_resource.h"
>> +#endif
>>  #include "dce80/dce80_resource.h"
>>  #include "dce100/dce100_resource.h"
>>  #include "dce110/dce110_resource.h"
>> @@ -53,6 +56,18 @@ enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id)
>>  	enum dce_version dc_version = DCE_VERSION_UNKNOWN;
>>  	switch (asic_id.chip_family) {
>>  
>> +#if defined(CONFIG_DRM_AMD_DC_SI)
>> +	case FAMILY_SI:
>> +		if (ASIC_REV_IS_TAHITI_P(asic_id.hw_internal_rev) ||
>> +		    ASIC_REV_IS_PITCAIRN_PM(asic_id.hw_internal_rev) ||
>> +		    ASIC_REV_IS_CAPEVERDE_M(asic_id.hw_internal_rev))
>> +		dc_version = DCE_VERSION_6_0;
>> +		else if (ASIC_REV_IS_OLAND_M(asic_id.hw_internal_rev))
>> +			dc_version = DCE_VERSION_6_4;
>> +		else
>> +			dc_version = DCE_VERSION_6_1;
>> +		break;
>> +#endif
>>  	case FAMILY_CI:
>>  		dc_version = DCE_VERSION_8_0;
>>  		break;
>> @@ -110,6 +125,20 @@ struct resource_pool *dc_create_resource_pool(
>>  	struct resource_pool *res_pool = NULL;
>>  
>>  	switch (dc_version) {
>> +#if defined(CONFIG_DRM_AMD_DC_SI)
>> +	case DCE_VERSION_6_0:
>> +		res_pool = dce60_create_resource_pool(
>> +			num_virtual_links, dc);
>> +		break;
>> +	case DCE_VERSION_6_1:
>> +		res_pool = dce61_create_resource_pool(
>> +			num_virtual_links, dc);
>> +		break;
>> +	case DCE_VERSION_6_4:
>> +		res_pool = dce64_create_resource_pool(
>> +			num_virtual_links, dc);
>> +		break;
>> +#endif
>>  	case DCE_VERSION_8_0:
>>  		res_pool = dce80_create_resource_pool(
>>  			num_virtual_links, dc);
>>
> _______________________________________________
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