[PATCH v1 00/15] VCN IP DUMP support for remaining IP's

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* [PATCH v1 00/15] VCN IP DUMP support for remaining IP's
@ 2024-08-06  8:18 Sunil Khatri
  2024-08-06  8:18 ` [PATCH v1 01/15] drm/amdgpu: add vcn_v5_0 ip dump support Sunil Khatri
                   ` (14 more replies)
  0 siblings, 15 replies; 28+ messages in thread
From: Sunil Khatri @ 2024-08-06  8:18 UTC (permalink / raw)
  To: Alex Deucher, Christian König; +Cc: amd-gfx, Sunil Khatri

VCN IP dump support for
a. 1.0
b. 2.0
c. 2.5
d. 2.6
e. 4.0
f. 4.0.3
g. 4.0.5
h. 5.0

Testing is done on VCN 3.x 4.x 5.x only as older version of VCN targets
are not available but it should work as the methodology to read and dump
value in devcoredump remains same. All the registers are validated
against the IP and from windows program as much as possible.


Sunil Khatri (15):
  drm/amdgpu: add vcn_v5_0 ip dump support
  drm/amdgpu: add print support for vcn_v5_0 ip dump
  drm/amdgpu: add vcn_v4_0 ip dump support
  drm/amdgpu: add print support for vcn_v4_0 ip dump
  drm/amdgpu: add vcn_v4_0_3 ip dump support
  drm/amdgpu: add print support for vcn_v4_0_3 ip dump
  drm/amdgpu: add vcn_v4_0_5 ip dump support
  drm/amdgpu: add print support for vcn_v4_0_5 ip dump
  drm/amdgpu: add vcn_v1_0 ip dump support
  drm/amdgpu: add print support for vcn_v1_0 ip dump
  drm/amdgpu: add vcn_v2_0 ip dump support
  drm/amdgpu: add print support for vcn_v2_0 ip dump
  drm/amdgpu: add vcn_v2_5 ip dump support
  drm/amdgpu: add print support for vcn_v2_5 ip dump
  drm/amdgpu: add vcn ip dump support for vcn_v2_6

 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c   | 129 ++++++++++++++-
 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c   | 145 ++++++++++++++++-
 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c   | 148 ++++++++++++++++-
 drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c   | 203 ++++++++++++++++++++++-
 drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c | 204 +++++++++++++++++++++++-
 drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c | 203 ++++++++++++++++++++++-
 drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c | 204 +++++++++++++++++++++++-
 7 files changed, 1220 insertions(+), 16 deletions(-)

-- 
2.34.1


^ permalink raw reply	[flat|nested] 28+ messages in thread

* [PATCH v1 01/15] drm/amdgpu: add vcn_v5_0 ip dump support
  2024-08-06  8:18 [PATCH v1 00/15] VCN IP DUMP support for remaining IP's Sunil Khatri
@ 2024-08-06  8:18 ` Sunil Khatri
  2024-08-06  8:18 ` [PATCH v1 02/15] drm/amdgpu: add print support for vcn_v5_0 ip dump Sunil Khatri
                   ` (13 subsequent siblings)
  14 siblings, 0 replies; 28+ messages in thread
From: Sunil Khatri @ 2024-08-06  8:18 UTC (permalink / raw)
  To: Alex Deucher, Christian König; +Cc: amd-gfx, Sunil Khatri

Add support of vcn ip dump in the devcoredump
for vcn_v5_0.

Signed-off-by: Sunil Khatri <sunil.khatri@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c | 170 +++++++++++++++++++++++-
 1 file changed, 169 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
index 68c97fcd539b..a4260774dace 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
@@ -37,6 +37,134 @@
 
 #include <drm/drm_drv.h>
 
+static const struct amdgpu_hwip_reg_entry vcn_reg_list_5_0[] = {
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_POWER_STATUS),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_STATUS),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_VCPU_CACHE_OFFSET0),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_VCPU_CACHE_OFFSET1),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_VCPU_CACHE_OFFSET2),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CONTEXT_ID),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_DATA0),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_DATA1),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_CMD),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_NC1_64BIT_BAR_HIGH),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_NC1_64BIT_BAR_LOW),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE_VMIDS_MULTI),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_NC_VMIDS_MULTI),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI2),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO2),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI3),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO3),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI4),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO4),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR2),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR2),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR3),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR3),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR4),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR4),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE2),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE3),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_SOFT_RESET),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_SOFT_RESET2),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CGC_GATE),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CGC_STATUS),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CGC_CTRL),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CGC_CTRL3),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_SUVD_CGC_GATE),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_SUVD_CGC_STATUS),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_SUVD_CGC_CTRL),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_SUVD_CGC_GATE2),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE3),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE4),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE4),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_SUVD_CGC_STATUS2),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_SUVD_CGC_GATE2),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_VCPU_CACHE_OFFSET2),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_GPGPU_64BIT_BAR_LOW),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_GPGPU_64BIT_BAR_HIGH),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_CURR_LUMA_64BIT_BAR_LOW),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_CURR_LUMA_64BIT_BAR_HIGH),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_CURR_CHROMA_64BIT_BAR_LOW),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_CURR_CHROMA_64BIT_BAR_HIGH),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_DBW_64BIT_BAR_LOW),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_DBW_64BIT_BAR_HIGH),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_CM_COLOC_64BIT_BAR_LOW),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_CM_COLOC_64BIT_BAR_HIGH),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSP0_64BIT_BAR_LOW),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSP0_64BIT_BAR_HIGH),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSP1_64BIT_BAR_LOW),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSP1_64BIT_BAR_HIGH),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSP2_64BIT_BAR_LOW),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSP2_64BIT_BAR_HIGH),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSP3_64BIT_BAR_LOW),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSP3_64BIT_BAR_HIGH),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSD0_64BIT_BAR_LOW),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSD0_64BIT_BAR_HIGH),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSD1_64BIT_BAR_LOW),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSD1_64BIT_BAR_HIGH),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSD2_64BIT_BAR_LOW),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSD2_64BIT_BAR_HIGH),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSD3_64BIT_BAR_LOW),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSD3_64BIT_BAR_HIGH),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSD4_64BIT_BAR_LOW),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSD4_64BIT_BAR_HIGH),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE3_64BIT_BAR_LOW),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE3_64BIT_BAR_HIGH),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE4_64BIT_BAR_LOW),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE4_64BIT_BAR_HIGH),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE5_64BIT_BAR_LOW),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE5_64BIT_BAR_HIGH),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE6_64BIT_BAR_LOW),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE6_64BIT_BAR_HIGH),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE7_64BIT_BAR_LOW),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE7_64BIT_BAR_HIGH),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_SCLR_64BIT_BAR_LOW),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_SCLR_64BIT_BAR_HIGH),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_SCLR2_64BIT_BAR_LOW),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_SCLR2_64BIT_BAR_HIGH),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_IMAGEPASTE_LUMA_64BIT_BAR_LOW),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_IMAGEPASTE_LUMA_64BIT_BAR_HIGH),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_IMAGEPASTE_CHROMA_64BIT_BAR_LOW),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_IMAGEPASTE_CHROMA_64BIT_BAR_HIGH),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_PRIVACY_LUMA_64BIT_BAR_LOW),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_PRIVACY_LUMA_64BIT_BAR_HIGH),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_PRIVACY_CHROMA_64BIT_BAR_LOW),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_PRIVACY_CHROMA_64BIT_BAR_HIGH),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_STATUS),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_IPX_DLDO_CONFIG),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_IPX_DLDO_STATUS),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_CTL),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_DATA),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_MASK),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_PAUSE),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_VCPU_CACHE_OFFSET0),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMI_VCPU_CACHE_VMID),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_CLK_EN_VCPU_REPORT),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_CTL),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_CTL2),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_SCRATCH1)
+};
+
 static int amdgpu_ih_clientid_vcns[] = {
 	SOC15_IH_CLIENTID_VCN,
 	SOC15_IH_CLIENTID_VCN1
@@ -83,6 +211,8 @@ static int vcn_v5_0_0_sw_init(void *handle)
 	struct amdgpu_ring *ring;
 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 	int i, r;
+	uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_5_0);
+	uint32_t *ptr;
 
 	r = amdgpu_vcn_sw_init(adev);
 	if (r)
@@ -137,6 +267,14 @@ static int vcn_v5_0_0_sw_init(void *handle)
 	if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)
 		adev->vcn.pause_dpg_mode = vcn_v5_0_0_pause_dpg_mode;
 
+	/* Allocate memory for VCN IP Dump buffer */
+	ptr = kcalloc(adev->vcn.num_vcn_inst * reg_count, sizeof(uint32_t), GFP_KERNEL);
+	if (ptr == NULL) {
+		DRM_ERROR("Failed to allocate memory for VCN IP Dump\n");
+		adev->vcn.ip_dump = NULL;
+	} else {
+		adev->vcn.ip_dump = ptr;
+	}
 	return 0;
 }
 
@@ -173,6 +311,8 @@ static int vcn_v5_0_0_sw_fini(void *handle)
 
 	r = amdgpu_vcn_sw_fini(adev);
 
+	kfree(adev->vcn.ip_dump);
+
 	return r;
 }
 
@@ -1297,6 +1437,34 @@ static void vcn_v5_0_0_set_irq_funcs(struct amdgpu_device *adev)
 	}
 }
 
+static void vcn_v5_0_dump_ip_state(void *handle)
+{
+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+	int i, j;
+	bool is_powered;
+	uint32_t inst_off;
+	uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_5_0);
+
+	if (!adev->vcn.ip_dump)
+		return;
+
+	for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
+		if (adev->vcn.harvest_config & (1 << i))
+			continue;
+
+		inst_off = i * reg_count;
+		/* mmUVD_POWER_STATUS is always readable and is first element of the array */
+		adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, i, regUVD_POWER_STATUS);
+		is_powered = (adev->vcn.ip_dump[inst_off] &
+				UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
+
+		if (is_powered)
+			for (j = 1; j < reg_count; j++)
+				adev->vcn.ip_dump[inst_off + j] =
+					RREG32(SOC15_REG_ENTRY_OFFSET_INST(vcn_reg_list_5_0[j], i));
+	}
+}
+
 static const struct amd_ip_funcs vcn_v5_0_0_ip_funcs = {
 	.name = "vcn_v5_0_0",
 	.early_init = vcn_v5_0_0_early_init,
@@ -1315,7 +1483,7 @@ static const struct amd_ip_funcs vcn_v5_0_0_ip_funcs = {
 	.post_soft_reset = NULL,
 	.set_clockgating_state = vcn_v5_0_0_set_clockgating_state,
 	.set_powergating_state = vcn_v5_0_0_set_powergating_state,
-	.dump_ip_state = NULL,
+	.dump_ip_state = vcn_v5_0_dump_ip_state,
 	.print_ip_state = NULL,
 };
 
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 28+ messages in thread

* [PATCH v1 02/15] drm/amdgpu: add print support for vcn_v5_0 ip dump
  2024-08-06  8:18 [PATCH v1 00/15] VCN IP DUMP support for remaining IP's Sunil Khatri
  2024-08-06  8:18 ` [PATCH v1 01/15] drm/amdgpu: add vcn_v5_0 ip dump support Sunil Khatri
@ 2024-08-06  8:18 ` Sunil Khatri
  2024-08-06  8:18 ` [PATCH v1 03/15] drm/amdgpu: add vcn_v4_0 ip dump support Sunil Khatri
                   ` (12 subsequent siblings)
  14 siblings, 0 replies; 28+ messages in thread
From: Sunil Khatri @ 2024-08-06  8:18 UTC (permalink / raw)
  To: Alex Deucher, Christian König; +Cc: amd-gfx, Sunil Khatri

Add support for logging the registers in devcoredump
buffer for vcn_v5_0.

Signed-off-by: Sunil Khatri <sunil.khatri@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c | 34 ++++++++++++++++++++++++-
 1 file changed, 33 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
index a4260774dace..0a5283af2a4a 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c
@@ -1437,6 +1437,38 @@ static void vcn_v5_0_0_set_irq_funcs(struct amdgpu_device *adev)
 	}
 }
 
+static void vcn_v5_0_print_ip_state(void *handle, struct drm_printer *p)
+{
+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+	int i, j;
+	uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_5_0);
+	uint32_t inst_off, is_powered;
+
+	if (!adev->vcn.ip_dump)
+		return;
+
+	drm_printf(p, "num_instances:%d\n", adev->vcn.num_vcn_inst);
+	for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
+		if (adev->vcn.harvest_config & (1 << i)) {
+			drm_printf(p, "\nHarvested Instance:VCN%d Skipping dump\n", i);
+			continue;
+		}
+
+		inst_off = i * reg_count;
+		is_powered = (adev->vcn.ip_dump[inst_off] &
+				UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
+
+		if (is_powered) {
+			drm_printf(p, "\nActive Instance:VCN%d\n", i);
+			for (j = 0; j < reg_count; j++)
+				drm_printf(p, "%-50s \t 0x%08x\n", vcn_reg_list_5_0[j].reg_name,
+					   adev->vcn.ip_dump[inst_off + j]);
+		} else {
+			drm_printf(p, "\nInactive Instance:VCN%d\n", i);
+		}
+	}
+}
+
 static void vcn_v5_0_dump_ip_state(void *handle)
 {
 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
@@ -1484,7 +1516,7 @@ static const struct amd_ip_funcs vcn_v5_0_0_ip_funcs = {
 	.set_clockgating_state = vcn_v5_0_0_set_clockgating_state,
 	.set_powergating_state = vcn_v5_0_0_set_powergating_state,
 	.dump_ip_state = vcn_v5_0_dump_ip_state,
-	.print_ip_state = NULL,
+	.print_ip_state = vcn_v5_0_print_ip_state,
 };
 
 const struct amdgpu_ip_block_version vcn_v5_0_0_ip_block = {
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 28+ messages in thread

* [PATCH v1 03/15] drm/amdgpu: add vcn_v4_0 ip dump support
  2024-08-06  8:18 [PATCH v1 00/15] VCN IP DUMP support for remaining IP's Sunil Khatri
  2024-08-06  8:18 ` [PATCH v1 01/15] drm/amdgpu: add vcn_v5_0 ip dump support Sunil Khatri
  2024-08-06  8:18 ` [PATCH v1 02/15] drm/amdgpu: add print support for vcn_v5_0 ip dump Sunil Khatri
@ 2024-08-06  8:18 ` Sunil Khatri
  2024-08-06  8:18 ` [PATCH v1 04/15] drm/amdgpu: add print support for vcn_v4_0 ip dump Sunil Khatri
                   ` (11 subsequent siblings)
  14 siblings, 0 replies; 28+ messages in thread
From: Sunil Khatri @ 2024-08-06  8:18 UTC (permalink / raw)
  To: Alex Deucher, Christian König; +Cc: amd-gfx, Sunil Khatri

Add support of vcn ip dump in the devcoredump
for vcn_v4_0.

Signed-off-by: Sunil Khatri <sunil.khatri@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c | 169 +++++++++++++++++++++++++-
 1 file changed, 168 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
index 776c539bfdda..344e57bf49d2 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
@@ -52,6 +52,132 @@
 #define RDECODE_MSG_CREATE							0x00000000
 #define RDECODE_MESSAGE_CREATE							0x00000001
 
+static const struct amdgpu_hwip_reg_entry vcn_reg_list_4_0[] = {
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_POWER_STATUS),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_STATUS),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_VCPU_CACHE_OFFSET0),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_VCPU_CACHE_OFFSET1),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_VCPU_CACHE_OFFSET2),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CONTEXT_ID),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_DATA0),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_DATA1),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_CMD),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_NC1_64BIT_BAR_HIGH),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_NC1_64BIT_BAR_LOW),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE_VMIDS_MULTI),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_NC_VMIDS_MULTI),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI2),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO2),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI3),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO3),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI4),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO4),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR2),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR2),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR3),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR3),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR4),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR4),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE2),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE3),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_SOFT_RESET),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_SOFT_RESET2),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CGC_GATE),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CGC_STATUS),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CGC_CTRL),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CGC_CTRL3),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_SUVD_CGC_GATE),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_SUVD_CGC_STATUS),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_SUVD_CGC_CTRL),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_SUVD_CGC_GATE2),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE3),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE4),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE4),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_SUVD_CGC_STATUS2),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_SUVD_CGC_GATE2),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_VCPU_CACHE_OFFSET2),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_GPGPU_64BIT_BAR_LOW),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_GPGPU_64BIT_BAR_HIGH),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_CURR_LUMA_64BIT_BAR_LOW),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_CURR_LUMA_64BIT_BAR_HIGH),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_CURR_CHROMA_64BIT_BAR_LOW),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_CURR_CHROMA_64BIT_BAR_HIGH),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_DBW_64BIT_BAR_LOW),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_DBW_64BIT_BAR_HIGH),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_CM_COLOC_64BIT_BAR_LOW),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_CM_COLOC_64BIT_BAR_HIGH),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSP0_64BIT_BAR_LOW),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSP0_64BIT_BAR_HIGH),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSP1_64BIT_BAR_LOW),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSP1_64BIT_BAR_HIGH),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSP2_64BIT_BAR_LOW),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSP2_64BIT_BAR_HIGH),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSP3_64BIT_BAR_LOW),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSP3_64BIT_BAR_HIGH),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSD0_64BIT_BAR_LOW),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSD0_64BIT_BAR_HIGH),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSD1_64BIT_BAR_LOW),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSD1_64BIT_BAR_HIGH),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSD2_64BIT_BAR_LOW),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSD2_64BIT_BAR_HIGH),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSD3_64BIT_BAR_LOW),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSD3_64BIT_BAR_HIGH),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSD4_64BIT_BAR_LOW),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSD4_64BIT_BAR_HIGH),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE3_64BIT_BAR_LOW),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE3_64BIT_BAR_HIGH),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE4_64BIT_BAR_LOW),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE4_64BIT_BAR_HIGH),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE5_64BIT_BAR_LOW),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE5_64BIT_BAR_HIGH),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE6_64BIT_BAR_LOW),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE6_64BIT_BAR_HIGH),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE7_64BIT_BAR_LOW),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE7_64BIT_BAR_HIGH),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_SCLR_64BIT_BAR_LOW),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_SCLR_64BIT_BAR_HIGH),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_SCLR2_64BIT_BAR_LOW),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_SCLR2_64BIT_BAR_HIGH),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_IMAGEPASTE_LUMA_64BIT_BAR_LOW),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_IMAGEPASTE_LUMA_64BIT_BAR_HIGH),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_IMAGEPASTE_CHROMA_64BIT_BAR_LOW),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_IMAGEPASTE_CHROMA_64BIT_BAR_HIGH),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_PRIVACY_LUMA_64BIT_BAR_LOW),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_PRIVACY_LUMA_64BIT_BAR_HIGH),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_PRIVACY_CHROMA_64BIT_BAR_LOW),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_PRIVACY_CHROMA_64BIT_BAR_HIGH),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_STATUS),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_CTL),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_DATA),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_MASK),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_PAUSE),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_VCPU_CACHE_OFFSET0),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMI_VCPU_CACHE_VMID),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_CLK_EN_VCPU_REPORT),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_CTL),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_CTL2),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_SCRATCH1)
+};
+
 static int amdgpu_ih_clientid_vcns[] = {
 	SOC15_IH_CLIENTID_VCN,
 	SOC15_IH_CLIENTID_VCN1
@@ -137,6 +263,8 @@ static int vcn_v4_0_sw_init(void *handle)
 	struct amdgpu_ring *ring;
 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 	int i, r;
+	uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_4_0);
+	uint32_t *ptr;
 
 	r = amdgpu_vcn_sw_init(adev);
 	if (r)
@@ -200,6 +328,15 @@ static int vcn_v4_0_sw_init(void *handle)
 	if (r)
 		return r;
 
+	/* Allocate memory for VCN IP Dump buffer */
+	ptr = kcalloc(adev->vcn.num_vcn_inst * reg_count, sizeof(uint32_t), GFP_KERNEL);
+	if (ptr == NULL) {
+		DRM_ERROR("Failed to allocate memory for VCN IP Dump\n");
+		adev->vcn.ip_dump = NULL;
+	} else {
+		adev->vcn.ip_dump = ptr;
+	}
+
 	return 0;
 }
 
@@ -239,6 +376,8 @@ static int vcn_v4_0_sw_fini(void *handle)
 
 	r = amdgpu_vcn_sw_fini(adev);
 
+	kfree(adev->vcn.ip_dump);
+
 	return r;
 }
 
@@ -2109,6 +2248,34 @@ static void vcn_v4_0_set_irq_funcs(struct amdgpu_device *adev)
 	}
 }
 
+static void vcn_v4_0_dump_ip_state(void *handle)
+{
+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+	int i, j;
+	bool is_powered;
+	uint32_t inst_off;
+	uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_4_0);
+
+	if (!adev->vcn.ip_dump)
+		return;
+
+	for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
+		if (adev->vcn.harvest_config & (1 << i))
+			continue;
+
+		inst_off = i * reg_count;
+		/* mmUVD_POWER_STATUS is always readable and is first element of the array */
+		adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, i, regUVD_POWER_STATUS);
+		is_powered = (adev->vcn.ip_dump[inst_off] &
+				UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
+
+		if (is_powered)
+			for (j = 1; j < reg_count; j++)
+				adev->vcn.ip_dump[inst_off + j] =
+					RREG32(SOC15_REG_ENTRY_OFFSET_INST(vcn_reg_list_4_0[j], i));
+	}
+}
+
 static const struct amd_ip_funcs vcn_v4_0_ip_funcs = {
 	.name = "vcn_v4_0",
 	.early_init = vcn_v4_0_early_init,
@@ -2127,7 +2294,7 @@ static const struct amd_ip_funcs vcn_v4_0_ip_funcs = {
 	.post_soft_reset = NULL,
 	.set_clockgating_state = vcn_v4_0_set_clockgating_state,
 	.set_powergating_state = vcn_v4_0_set_powergating_state,
-	.dump_ip_state = NULL,
+	.dump_ip_state = vcn_v4_0_dump_ip_state,
 	.print_ip_state = NULL,
 };
 
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 28+ messages in thread

* [PATCH v1 04/15] drm/amdgpu: add print support for vcn_v4_0 ip dump
  2024-08-06  8:18 [PATCH v1 00/15] VCN IP DUMP support for remaining IP's Sunil Khatri
                   ` (2 preceding siblings ...)
  2024-08-06  8:18 ` [PATCH v1 03/15] drm/amdgpu: add vcn_v4_0 ip dump support Sunil Khatri
@ 2024-08-06  8:18 ` Sunil Khatri
  2024-08-06  8:18 ` [PATCH v1 05/15] drm/amdgpu: add vcn_v4_0_3 ip dump support Sunil Khatri
                   ` (10 subsequent siblings)
  14 siblings, 0 replies; 28+ messages in thread
From: Sunil Khatri @ 2024-08-06  8:18 UTC (permalink / raw)
  To: Alex Deucher, Christian König; +Cc: amd-gfx, Sunil Khatri

Add support for logging the registers in devcoredump
buffer for vcn_v4_0.

Signed-off-by: Sunil Khatri <sunil.khatri@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c | 34 ++++++++++++++++++++++++++-
 1 file changed, 33 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
index 344e57bf49d2..a34a8594945f 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
@@ -2248,6 +2248,38 @@ static void vcn_v4_0_set_irq_funcs(struct amdgpu_device *adev)
 	}
 }
 
+static void vcn_v4_0_print_ip_state(void *handle, struct drm_printer *p)
+{
+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+	int i, j;
+	uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_4_0);
+	uint32_t inst_off, is_powered;
+
+	if (!adev->vcn.ip_dump)
+		return;
+
+	drm_printf(p, "num_instances:%d\n", adev->vcn.num_vcn_inst);
+	for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
+		if (adev->vcn.harvest_config & (1 << i)) {
+			drm_printf(p, "\nHarvested Instance:VCN%d Skipping dump\n", i);
+			continue;
+		}
+
+		inst_off = i * reg_count;
+		is_powered = (adev->vcn.ip_dump[inst_off] &
+				UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
+
+		if (is_powered) {
+			drm_printf(p, "\nActive Instance:VCN%d\n", i);
+			for (j = 0; j < reg_count; j++)
+				drm_printf(p, "%-50s \t 0x%08x\n", vcn_reg_list_4_0[j].reg_name,
+					   adev->vcn.ip_dump[inst_off + j]);
+		} else {
+			drm_printf(p, "\nInactive Instance:VCN%d\n", i);
+		}
+	}
+}
+
 static void vcn_v4_0_dump_ip_state(void *handle)
 {
 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
@@ -2295,7 +2327,7 @@ static const struct amd_ip_funcs vcn_v4_0_ip_funcs = {
 	.set_clockgating_state = vcn_v4_0_set_clockgating_state,
 	.set_powergating_state = vcn_v4_0_set_powergating_state,
 	.dump_ip_state = vcn_v4_0_dump_ip_state,
-	.print_ip_state = NULL,
+	.print_ip_state = vcn_v4_0_print_ip_state,
 };
 
 const struct amdgpu_ip_block_version vcn_v4_0_ip_block = {
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 28+ messages in thread

* [PATCH v1 05/15] drm/amdgpu: add vcn_v4_0_3 ip dump support
  2024-08-06  8:18 [PATCH v1 00/15] VCN IP DUMP support for remaining IP's Sunil Khatri
                   ` (3 preceding siblings ...)
  2024-08-06  8:18 ` [PATCH v1 04/15] drm/amdgpu: add print support for vcn_v4_0 ip dump Sunil Khatri
@ 2024-08-06  8:18 ` Sunil Khatri
  2024-08-06 21:28   ` Alex Deucher
  2024-08-06  8:18 ` [PATCH v1 06/15] drm/amdgpu: add print support for vcn_v4_0_3 ip dump Sunil Khatri
                   ` (9 subsequent siblings)
  14 siblings, 1 reply; 28+ messages in thread
From: Sunil Khatri @ 2024-08-06  8:18 UTC (permalink / raw)
  To: Alex Deucher, Christian König; +Cc: amd-gfx, Sunil Khatri

Add support of vcn ip dump in the devcoredump
for vcn_v4_0_3.

Signed-off-by: Sunil Khatri <sunil.khatri@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c | 170 +++++++++++++++++++++++-
 1 file changed, 169 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
index 9bae95538b62..dd3baccb2904 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
@@ -45,6 +45,132 @@
 #define VCN_VID_SOC_ADDRESS_2_0		0x1fb00
 #define VCN1_VID_SOC_ADDRESS_3_0	0x48300
 
+static const struct amdgpu_hwip_reg_entry vcn_reg_list_4_0_3[] = {
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_POWER_STATUS),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_STATUS),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_VCPU_CACHE_OFFSET0),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_VCPU_CACHE_OFFSET1),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_VCPU_CACHE_OFFSET2),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CONTEXT_ID),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_DATA0),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_DATA1),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_CMD),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_NC1_64BIT_BAR_HIGH),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_NC1_64BIT_BAR_LOW),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE_VMIDS_MULTI),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_NC_VMIDS_MULTI),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI2),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO2),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI3),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO3),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI4),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO4),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR2),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR2),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR3),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR3),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR4),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR4),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE2),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE3),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_SOFT_RESET),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_SOFT_RESET2),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CGC_GATE),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CGC_STATUS),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CGC_CTRL),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CGC_CTRL3),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_SUVD_CGC_GATE),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_SUVD_CGC_STATUS),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_SUVD_CGC_CTRL),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_SUVD_CGC_GATE2),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE3),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE4),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE4),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_SUVD_CGC_STATUS2),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_SUVD_CGC_GATE2),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_VCPU_CACHE_OFFSET2),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_GPGPU_64BIT_BAR_LOW),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_GPGPU_64BIT_BAR_HIGH),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_CURR_LUMA_64BIT_BAR_LOW),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_CURR_LUMA_64BIT_BAR_HIGH),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_CURR_CHROMA_64BIT_BAR_LOW),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_CURR_CHROMA_64BIT_BAR_HIGH),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_DBW_64BIT_BAR_LOW),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_DBW_64BIT_BAR_HIGH),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_CM_COLOC_64BIT_BAR_LOW),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_CM_COLOC_64BIT_BAR_HIGH),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSP0_64BIT_BAR_LOW),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSP0_64BIT_BAR_HIGH),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSP1_64BIT_BAR_LOW),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSP1_64BIT_BAR_HIGH),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSP2_64BIT_BAR_LOW),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSP2_64BIT_BAR_HIGH),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSP3_64BIT_BAR_LOW),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSP3_64BIT_BAR_HIGH),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSD0_64BIT_BAR_LOW),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSD0_64BIT_BAR_HIGH),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSD1_64BIT_BAR_LOW),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSD1_64BIT_BAR_HIGH),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSD2_64BIT_BAR_LOW),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSD2_64BIT_BAR_HIGH),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSD3_64BIT_BAR_LOW),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSD3_64BIT_BAR_HIGH),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSD4_64BIT_BAR_LOW),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSD4_64BIT_BAR_HIGH),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE3_64BIT_BAR_LOW),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE3_64BIT_BAR_HIGH),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE4_64BIT_BAR_LOW),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE4_64BIT_BAR_HIGH),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE5_64BIT_BAR_LOW),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE5_64BIT_BAR_HIGH),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE6_64BIT_BAR_LOW),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE6_64BIT_BAR_HIGH),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE7_64BIT_BAR_LOW),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE7_64BIT_BAR_HIGH),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_SCLR_64BIT_BAR_LOW),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_SCLR_64BIT_BAR_HIGH),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_SCLR2_64BIT_BAR_LOW),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_SCLR2_64BIT_BAR_HIGH),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_IMAGEPASTE_LUMA_64BIT_BAR_LOW),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_IMAGEPASTE_LUMA_64BIT_BAR_HIGH),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_IMAGEPASTE_CHROMA_64BIT_BAR_LOW),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_IMAGEPASTE_CHROMA_64BIT_BAR_HIGH),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_PRIVACY_LUMA_64BIT_BAR_LOW),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_PRIVACY_LUMA_64BIT_BAR_HIGH),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_PRIVACY_CHROMA_64BIT_BAR_LOW),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_PRIVACY_CHROMA_64BIT_BAR_HIGH),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_STATUS),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_CTL),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_DATA),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_MASK),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_PAUSE),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_VCPU_CACHE_OFFSET0),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMI_VCPU_CACHE_VMID),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_CLK_EN_VCPU_REPORT),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_CTL),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_CTL2),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_SCRATCH1)
+};
+
 #define NORMALIZE_VCN_REG_OFFSET(offset) \
 		(offset & 0x1FFFF)
 
@@ -92,6 +218,8 @@ static int vcn_v4_0_3_sw_init(void *handle)
 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 	struct amdgpu_ring *ring;
 	int i, r, vcn_inst;
+	uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_4_0_3);
+	uint32_t *ptr;
 
 	r = amdgpu_vcn_sw_init(adev);
 	if (r)
@@ -159,6 +287,15 @@ static int vcn_v4_0_3_sw_init(void *handle)
 		}
 	}
 
+	/* Allocate memory for VCN IP Dump buffer */
+	ptr = kcalloc(adev->vcn.num_vcn_inst * reg_count, sizeof(uint32_t), GFP_KERNEL);
+	if (ptr == NULL) {
+		DRM_ERROR("Failed to allocate memory for VCN IP Dump\n");
+		adev->vcn.ip_dump = NULL;
+	} else {
+		adev->vcn.ip_dump = ptr;
+	}
+
 	return 0;
 }
 
@@ -194,6 +331,8 @@ static int vcn_v4_0_3_sw_fini(void *handle)
 
 	r = amdgpu_vcn_sw_fini(adev);
 
+	kfree(adev->vcn.ip_dump);
+
 	return r;
 }
 
@@ -1684,6 +1823,35 @@ static void vcn_v4_0_3_set_irq_funcs(struct amdgpu_device *adev)
 	adev->vcn.inst->irq.funcs = &vcn_v4_0_3_irq_funcs;
 }
 
+static void vcn_v4_0_3_dump_ip_state(void *handle)
+{
+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+	int i, j;
+	bool is_powered;
+	uint32_t inst_off;
+	uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_4_0_3);
+
+	if (!adev->vcn.ip_dump)
+		return;
+
+	for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
+		if (adev->vcn.harvest_config & (1 << i))
+			continue;
+
+		inst_off = i * reg_count;
+		/* mmUVD_POWER_STATUS is always readable and is first element of the array */
+		adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, i, regUVD_POWER_STATUS);
+		is_powered = (adev->vcn.ip_dump[inst_off] &
+				UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
+
+		if (is_powered)
+			for (j = 1; j < reg_count; j++)
+				adev->vcn.ip_dump[inst_off + j] =
+					RREG32(SOC15_REG_ENTRY_OFFSET_INST(
+						vcn_reg_list_4_0_3[j], i));
+	}
+}
+
 static const struct amd_ip_funcs vcn_v4_0_3_ip_funcs = {
 	.name = "vcn_v4_0_3",
 	.early_init = vcn_v4_0_3_early_init,
@@ -1702,7 +1870,7 @@ static const struct amd_ip_funcs vcn_v4_0_3_ip_funcs = {
 	.post_soft_reset = NULL,
 	.set_clockgating_state = vcn_v4_0_3_set_clockgating_state,
 	.set_powergating_state = vcn_v4_0_3_set_powergating_state,
-	.dump_ip_state = NULL,
+	.dump_ip_state = vcn_v4_0_3_dump_ip_state,
 	.print_ip_state = NULL,
 };
 
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 28+ messages in thread

* Re: [PATCH v1 05/15] drm/amdgpu: add vcn_v4_0_3 ip dump support
  2024-08-06  8:18 ` [PATCH v1 05/15] drm/amdgpu: add vcn_v4_0_3 ip dump support Sunil Khatri
@ 2024-08-06 21:28   ` Alex Deucher
  2024-08-07  3:47     ` Khatri, Sunil
  2024-08-08  5:50     ` Lazar, Lijo
  0 siblings, 2 replies; 28+ messages in thread
From: Alex Deucher @ 2024-08-06 21:28 UTC (permalink / raw)
  To: Sunil Khatri; +Cc: Alex Deucher, Christian König, amd-gfx

On Tue, Aug 6, 2024 at 4:18 AM Sunil Khatri <sunil.khatri@amd.com> wrote:
>
> Add support of vcn ip dump in the devcoredump
> for vcn_v4_0_3.
>
> Signed-off-by: Sunil Khatri <sunil.khatri@amd.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c | 170 +++++++++++++++++++++++-
>  1 file changed, 169 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
> index 9bae95538b62..dd3baccb2904 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
> @@ -45,6 +45,132 @@
>  #define VCN_VID_SOC_ADDRESS_2_0                0x1fb00
>  #define VCN1_VID_SOC_ADDRESS_3_0       0x48300
>
> +static const struct amdgpu_hwip_reg_entry vcn_reg_list_4_0_3[] = {
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_POWER_STATUS),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_STATUS),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_VCPU_CACHE_OFFSET0),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_VCPU_CACHE_OFFSET1),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_VCPU_CACHE_OFFSET2),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CONTEXT_ID),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_DATA0),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_DATA1),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_CMD),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_NC1_64BIT_BAR_HIGH),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_NC1_64BIT_BAR_LOW),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE_VMIDS_MULTI),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_NC_VMIDS_MULTI),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI2),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO2),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI3),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO3),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI4),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO4),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR2),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR2),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR3),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR3),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR4),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR4),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE2),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE3),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_SOFT_RESET),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_SOFT_RESET2),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CGC_GATE),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CGC_STATUS),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CGC_CTRL),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CGC_CTRL3),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_SUVD_CGC_GATE),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_SUVD_CGC_STATUS),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_SUVD_CGC_CTRL),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_SUVD_CGC_GATE2),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE3),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE4),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE4),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_SUVD_CGC_STATUS2),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_SUVD_CGC_GATE2),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_VCPU_CACHE_OFFSET2),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_GPGPU_64BIT_BAR_LOW),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_GPGPU_64BIT_BAR_HIGH),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_CURR_LUMA_64BIT_BAR_LOW),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_CURR_LUMA_64BIT_BAR_HIGH),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_CURR_CHROMA_64BIT_BAR_LOW),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_CURR_CHROMA_64BIT_BAR_HIGH),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_DBW_64BIT_BAR_LOW),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_DBW_64BIT_BAR_HIGH),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_CM_COLOC_64BIT_BAR_LOW),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_CM_COLOC_64BIT_BAR_HIGH),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSP0_64BIT_BAR_LOW),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSP0_64BIT_BAR_HIGH),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSP1_64BIT_BAR_LOW),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSP1_64BIT_BAR_HIGH),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSP2_64BIT_BAR_LOW),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSP2_64BIT_BAR_HIGH),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSP3_64BIT_BAR_LOW),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSP3_64BIT_BAR_HIGH),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSD0_64BIT_BAR_LOW),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSD0_64BIT_BAR_HIGH),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSD1_64BIT_BAR_LOW),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSD1_64BIT_BAR_HIGH),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSD2_64BIT_BAR_LOW),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSD2_64BIT_BAR_HIGH),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSD3_64BIT_BAR_LOW),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSD3_64BIT_BAR_HIGH),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSD4_64BIT_BAR_LOW),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSD4_64BIT_BAR_HIGH),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE3_64BIT_BAR_LOW),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE3_64BIT_BAR_HIGH),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE4_64BIT_BAR_LOW),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE4_64BIT_BAR_HIGH),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE5_64BIT_BAR_LOW),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE5_64BIT_BAR_HIGH),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE6_64BIT_BAR_LOW),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE6_64BIT_BAR_HIGH),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE7_64BIT_BAR_LOW),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE7_64BIT_BAR_HIGH),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_SCLR_64BIT_BAR_LOW),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_SCLR_64BIT_BAR_HIGH),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_SCLR2_64BIT_BAR_LOW),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_SCLR2_64BIT_BAR_HIGH),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_IMAGEPASTE_LUMA_64BIT_BAR_LOW),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_IMAGEPASTE_LUMA_64BIT_BAR_HIGH),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_IMAGEPASTE_CHROMA_64BIT_BAR_LOW),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_IMAGEPASTE_CHROMA_64BIT_BAR_HIGH),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_PRIVACY_LUMA_64BIT_BAR_LOW),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_PRIVACY_LUMA_64BIT_BAR_HIGH),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_PRIVACY_CHROMA_64BIT_BAR_LOW),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_PRIVACY_CHROMA_64BIT_BAR_HIGH),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_STATUS),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_CTL),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_DATA),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_MASK),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_PAUSE),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_VCPU_CACHE_OFFSET0),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMI_VCPU_CACHE_VMID),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_CLK_EN_VCPU_REPORT),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_CTL),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_CTL2),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_SCRATCH1)
> +};
> +
>  #define NORMALIZE_VCN_REG_OFFSET(offset) \
>                 (offset & 0x1FFFF)
>
> @@ -92,6 +218,8 @@ static int vcn_v4_0_3_sw_init(void *handle)
>         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>         struct amdgpu_ring *ring;
>         int i, r, vcn_inst;
> +       uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_4_0_3);
> +       uint32_t *ptr;
>
>         r = amdgpu_vcn_sw_init(adev);
>         if (r)
> @@ -159,6 +287,15 @@ static int vcn_v4_0_3_sw_init(void *handle)
>                 }
>         }
>
> +       /* Allocate memory for VCN IP Dump buffer */
> +       ptr = kcalloc(adev->vcn.num_vcn_inst * reg_count, sizeof(uint32_t), GFP_KERNEL);
> +       if (ptr == NULL) {
> +               DRM_ERROR("Failed to allocate memory for VCN IP Dump\n");
> +               adev->vcn.ip_dump = NULL;
> +       } else {
> +               adev->vcn.ip_dump = ptr;
> +       }
> +
>         return 0;
>  }
>
> @@ -194,6 +331,8 @@ static int vcn_v4_0_3_sw_fini(void *handle)
>
>         r = amdgpu_vcn_sw_fini(adev);
>
> +       kfree(adev->vcn.ip_dump);
> +
>         return r;
>  }
>
> @@ -1684,6 +1823,35 @@ static void vcn_v4_0_3_set_irq_funcs(struct amdgpu_device *adev)
>         adev->vcn.inst->irq.funcs = &vcn_v4_0_3_irq_funcs;
>  }
>
> +static void vcn_v4_0_3_dump_ip_state(void *handle)
> +{
> +       struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> +       int i, j;
> +       bool is_powered;
> +       uint32_t inst_off;
> +       uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_4_0_3);
> +
> +       if (!adev->vcn.ip_dump)
> +               return;
> +
> +       for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
> +               if (adev->vcn.harvest_config & (1 << i))
> +                       continue;
> +
> +               inst_off = i * reg_count;
> +               /* mmUVD_POWER_STATUS is always readable and is first element of the array */
> +               adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, i, regUVD_POWER_STATUS);

I think you need to use the GET_INST() macro to properly handle this.  E.g.,
vcn_inst = GET_INST(VCN, i);

Alex

> +               is_powered = (adev->vcn.ip_dump[inst_off] &
> +                               UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
> +
> +               if (is_powered)
> +                       for (j = 1; j < reg_count; j++)
> +                               adev->vcn.ip_dump[inst_off + j] =
> +                                       RREG32(SOC15_REG_ENTRY_OFFSET_INST(
> +                                               vcn_reg_list_4_0_3[j], i));
> +       }
> +}
> +
>  static const struct amd_ip_funcs vcn_v4_0_3_ip_funcs = {
>         .name = "vcn_v4_0_3",
>         .early_init = vcn_v4_0_3_early_init,
> @@ -1702,7 +1870,7 @@ static const struct amd_ip_funcs vcn_v4_0_3_ip_funcs = {
>         .post_soft_reset = NULL,
>         .set_clockgating_state = vcn_v4_0_3_set_clockgating_state,
>         .set_powergating_state = vcn_v4_0_3_set_powergating_state,
> -       .dump_ip_state = NULL,
> +       .dump_ip_state = vcn_v4_0_3_dump_ip_state,
>         .print_ip_state = NULL,
>  };
>
> --
> 2.34.1
>

^ permalink raw reply	[flat|nested] 28+ messages in thread

* Re: [PATCH v1 05/15] drm/amdgpu: add vcn_v4_0_3 ip dump support
  2024-08-06 21:28   ` Alex Deucher
@ 2024-08-07  3:47     ` Khatri, Sunil
  2024-08-07  3:51       ` Alex Deucher
  2024-08-08  5:50     ` Lazar, Lijo
  1 sibling, 1 reply; 28+ messages in thread
From: Khatri, Sunil @ 2024-08-07  3:47 UTC (permalink / raw)
  To: Alex Deucher, Sunil Khatri; +Cc: Alex Deucher, Christian König, amd-gfx

[-- Attachment #1: Type: text/plain, Size: 12928 bytes --]


On 8/7/2024 2:58 AM, Alex Deucher wrote:
> On Tue, Aug 6, 2024 at 4:18 AM Sunil Khatri<sunil.khatri@amd.com>  wrote:
>> Add support of vcn ip dump in the devcoredump
>> for vcn_v4_0_3.
>>
>> Signed-off-by: Sunil Khatri<sunil.khatri@amd.com>
>> ---
>>   drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c | 170 +++++++++++++++++++++++-
>>   1 file changed, 169 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
>> index 9bae95538b62..dd3baccb2904 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
>> @@ -45,6 +45,132 @@
>>   #define VCN_VID_SOC_ADDRESS_2_0                0x1fb00
>>   #define VCN1_VID_SOC_ADDRESS_3_0       0x48300
>>
>> +static const struct amdgpu_hwip_reg_entry vcn_reg_list_4_0_3[] = {
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_POWER_STATUS),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_STATUS),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_VCPU_CACHE_OFFSET0),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_VCPU_CACHE_OFFSET1),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_VCPU_CACHE_OFFSET2),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CONTEXT_ID),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_DATA0),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_DATA1),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_CMD),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_NC1_64BIT_BAR_HIGH),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_NC1_64BIT_BAR_LOW),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE_VMIDS_MULTI),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_NC_VMIDS_MULTI),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI2),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO2),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI3),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO3),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI4),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO4),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR2),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR2),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR3),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR3),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR4),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR4),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE2),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE3),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_SOFT_RESET),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_SOFT_RESET2),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CGC_GATE),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CGC_STATUS),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CGC_CTRL),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CGC_CTRL3),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_SUVD_CGC_GATE),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_SUVD_CGC_STATUS),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_SUVD_CGC_CTRL),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_SUVD_CGC_GATE2),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE3),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE4),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE4),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_SUVD_CGC_STATUS2),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_SUVD_CGC_GATE2),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_VCPU_CACHE_OFFSET2),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_GPGPU_64BIT_BAR_LOW),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_GPGPU_64BIT_BAR_HIGH),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_CURR_LUMA_64BIT_BAR_LOW),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_CURR_LUMA_64BIT_BAR_HIGH),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_CURR_CHROMA_64BIT_BAR_LOW),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_CURR_CHROMA_64BIT_BAR_HIGH),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_DBW_64BIT_BAR_LOW),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_DBW_64BIT_BAR_HIGH),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_CM_COLOC_64BIT_BAR_LOW),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_CM_COLOC_64BIT_BAR_HIGH),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSP0_64BIT_BAR_LOW),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSP0_64BIT_BAR_HIGH),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSP1_64BIT_BAR_LOW),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSP1_64BIT_BAR_HIGH),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSP2_64BIT_BAR_LOW),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSP2_64BIT_BAR_HIGH),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSP3_64BIT_BAR_LOW),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSP3_64BIT_BAR_HIGH),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSD0_64BIT_BAR_LOW),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSD0_64BIT_BAR_HIGH),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSD1_64BIT_BAR_LOW),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSD1_64BIT_BAR_HIGH),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSD2_64BIT_BAR_LOW),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSD2_64BIT_BAR_HIGH),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSD3_64BIT_BAR_LOW),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSD3_64BIT_BAR_HIGH),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSD4_64BIT_BAR_LOW),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSD4_64BIT_BAR_HIGH),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE3_64BIT_BAR_LOW),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE3_64BIT_BAR_HIGH),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE4_64BIT_BAR_LOW),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE4_64BIT_BAR_HIGH),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE5_64BIT_BAR_LOW),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE5_64BIT_BAR_HIGH),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE6_64BIT_BAR_LOW),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE6_64BIT_BAR_HIGH),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE7_64BIT_BAR_LOW),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE7_64BIT_BAR_HIGH),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_SCLR_64BIT_BAR_LOW),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_SCLR_64BIT_BAR_HIGH),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_SCLR2_64BIT_BAR_LOW),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_SCLR2_64BIT_BAR_HIGH),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_IMAGEPASTE_LUMA_64BIT_BAR_LOW),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_IMAGEPASTE_LUMA_64BIT_BAR_HIGH),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_IMAGEPASTE_CHROMA_64BIT_BAR_LOW),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_IMAGEPASTE_CHROMA_64BIT_BAR_HIGH),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_PRIVACY_LUMA_64BIT_BAR_LOW),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_PRIVACY_LUMA_64BIT_BAR_HIGH),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_PRIVACY_CHROMA_64BIT_BAR_LOW),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_PRIVACY_CHROMA_64BIT_BAR_HIGH),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_STATUS),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_CTL),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_DATA),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_MASK),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_PAUSE),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_VCPU_CACHE_OFFSET0),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMI_VCPU_CACHE_VMID),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_CLK_EN_VCPU_REPORT),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_CTL),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_CTL2),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_SCRATCH1)
>> +};
>> +
>>   #define NORMALIZE_VCN_REG_OFFSET(offset) \
>>                  (offset & 0x1FFFF)
>>
>> @@ -92,6 +218,8 @@ static int vcn_v4_0_3_sw_init(void *handle)
>>          struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>>          struct amdgpu_ring *ring;
>>          int i, r, vcn_inst;
>> +       uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_4_0_3);
>> +       uint32_t *ptr;
>>
>>          r = amdgpu_vcn_sw_init(adev);
>>          if (r)
>> @@ -159,6 +287,15 @@ static int vcn_v4_0_3_sw_init(void *handle)
>>                  }
>>          }
>>
>> +       /* Allocate memory for VCN IP Dump buffer */
>> +       ptr = kcalloc(adev->vcn.num_vcn_inst * reg_count, sizeof(uint32_t), GFP_KERNEL);
>> +       if (ptr == NULL) {
>> +               DRM_ERROR("Failed to allocate memory for VCN IP Dump\n");
>> +               adev->vcn.ip_dump = NULL;
>> +       } else {
>> +               adev->vcn.ip_dump = ptr;
>> +       }
>> +
>>          return 0;
>>   }
>>
>> @@ -194,6 +331,8 @@ static int vcn_v4_0_3_sw_fini(void *handle)
>>
>>          r = amdgpu_vcn_sw_fini(adev);
>>
>> +       kfree(adev->vcn.ip_dump);
>> +
>>          return r;
>>   }
>>
>> @@ -1684,6 +1823,35 @@ static void vcn_v4_0_3_set_irq_funcs(struct amdgpu_device *adev)
>>          adev->vcn.inst->irq.funcs = &vcn_v4_0_3_irq_funcs;
>>   }
>>
>> +static void vcn_v4_0_3_dump_ip_state(void *handle)
>> +{
>> +       struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> +       int i, j;
>> +       bool is_powered;
>> +       uint32_t inst_off;
>> +       uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_4_0_3);
>> +
>> +       if (!adev->vcn.ip_dump)
>> +               return;
>> +
>> +       for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
>> +               if (adev->vcn.harvest_config & (1 << i))
>> +                       continue;
>> +
>> +               inst_off = i * reg_count;
>> +               /* mmUVD_POWER_STATUS is always readable and is first element of the array */
>> +               adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, i, regUVD_POWER_STATUS);
> I think you need to use the GET_INST() macro to properly handle this.  E.g.,
> vcn_inst = GET_INST(VCN, i);
Thanks for that. In all other cases apart from 4.0.3 it use array index 
itself as the Instance id.
GET_INST is only used here in 4.0.3, Is there a special demand for 4.0.3 ?
Regards
Sunil khatri
>
> Alex
>
>> +               is_powered = (adev->vcn.ip_dump[inst_off] &
>> +                               UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
>> +
>> +               if (is_powered)
>> +                       for (j = 1; j < reg_count; j++)
>> +                               adev->vcn.ip_dump[inst_off + j] =
>> +                                       RREG32(SOC15_REG_ENTRY_OFFSET_INST(
>> +                                               vcn_reg_list_4_0_3[j], i));
>> +       }
>> +}
>> +
>>   static const struct amd_ip_funcs vcn_v4_0_3_ip_funcs = {
>>          .name = "vcn_v4_0_3",
>>          .early_init = vcn_v4_0_3_early_init,
>> @@ -1702,7 +1870,7 @@ static const struct amd_ip_funcs vcn_v4_0_3_ip_funcs = {
>>          .post_soft_reset = NULL,
>>          .set_clockgating_state = vcn_v4_0_3_set_clockgating_state,
>>          .set_powergating_state = vcn_v4_0_3_set_powergating_state,
>> -       .dump_ip_state = NULL,
>> +       .dump_ip_state = vcn_v4_0_3_dump_ip_state,
>>          .print_ip_state = NULL,
>>   };
>>
>> --
>> 2.34.1
>>

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^ permalink raw reply	[flat|nested] 28+ messages in thread

* Re: [PATCH v1 05/15] drm/amdgpu: add vcn_v4_0_3 ip dump support
  2024-08-07  3:47     ` Khatri, Sunil
@ 2024-08-07  3:51       ` Alex Deucher
  0 siblings, 0 replies; 28+ messages in thread
From: Alex Deucher @ 2024-08-07  3:51 UTC (permalink / raw)
  To: Khatri, Sunil; +Cc: Sunil Khatri, Alex Deucher, Christian König, amd-gfx

On Tue, Aug 6, 2024 at 11:47 PM Khatri, Sunil <sukhatri@amd.com> wrote:
>
>
> On 8/7/2024 2:58 AM, Alex Deucher wrote:
>
> On Tue, Aug 6, 2024 at 4:18 AM Sunil Khatri <sunil.khatri@amd.com> wrote:
>
> Add support of vcn ip dump in the devcoredump
> for vcn_v4_0_3.
>
> Signed-off-by: Sunil Khatri <sunil.khatri@amd.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c | 170 +++++++++++++++++++++++-
>  1 file changed, 169 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
> index 9bae95538b62..dd3baccb2904 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
> @@ -45,6 +45,132 @@
>  #define VCN_VID_SOC_ADDRESS_2_0                0x1fb00
>  #define VCN1_VID_SOC_ADDRESS_3_0       0x48300
>
> +static const struct amdgpu_hwip_reg_entry vcn_reg_list_4_0_3[] = {
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_POWER_STATUS),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_STATUS),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_VCPU_CACHE_OFFSET0),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_VCPU_CACHE_OFFSET1),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_VCPU_CACHE_OFFSET2),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CONTEXT_ID),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_DATA0),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_DATA1),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_CMD),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_NC1_64BIT_BAR_HIGH),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_NC1_64BIT_BAR_LOW),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE_VMIDS_MULTI),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_NC_VMIDS_MULTI),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI2),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO2),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI3),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO3),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI4),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO4),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR2),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR2),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR3),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR3),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR4),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR4),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE2),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE3),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_SOFT_RESET),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_SOFT_RESET2),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CGC_GATE),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CGC_STATUS),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CGC_CTRL),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CGC_CTRL3),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_SUVD_CGC_GATE),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_SUVD_CGC_STATUS),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_SUVD_CGC_CTRL),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_SUVD_CGC_GATE2),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE3),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE4),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE4),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_SUVD_CGC_STATUS2),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_SUVD_CGC_GATE2),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_VCPU_CACHE_OFFSET2),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_GPGPU_64BIT_BAR_LOW),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_GPGPU_64BIT_BAR_HIGH),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_CURR_LUMA_64BIT_BAR_LOW),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_CURR_LUMA_64BIT_BAR_HIGH),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_CURR_CHROMA_64BIT_BAR_LOW),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_CURR_CHROMA_64BIT_BAR_HIGH),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_DBW_64BIT_BAR_LOW),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_DBW_64BIT_BAR_HIGH),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_CM_COLOC_64BIT_BAR_LOW),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_CM_COLOC_64BIT_BAR_HIGH),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSP0_64BIT_BAR_LOW),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSP0_64BIT_BAR_HIGH),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSP1_64BIT_BAR_LOW),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSP1_64BIT_BAR_HIGH),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSP2_64BIT_BAR_LOW),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSP2_64BIT_BAR_HIGH),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSP3_64BIT_BAR_LOW),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSP3_64BIT_BAR_HIGH),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSD0_64BIT_BAR_LOW),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSD0_64BIT_BAR_HIGH),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSD1_64BIT_BAR_LOW),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSD1_64BIT_BAR_HIGH),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSD2_64BIT_BAR_LOW),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSD2_64BIT_BAR_HIGH),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSD3_64BIT_BAR_LOW),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSD3_64BIT_BAR_HIGH),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSD4_64BIT_BAR_LOW),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSD4_64BIT_BAR_HIGH),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE3_64BIT_BAR_LOW),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE3_64BIT_BAR_HIGH),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE4_64BIT_BAR_LOW),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE4_64BIT_BAR_HIGH),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE5_64BIT_BAR_LOW),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE5_64BIT_BAR_HIGH),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE6_64BIT_BAR_LOW),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE6_64BIT_BAR_HIGH),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE7_64BIT_BAR_LOW),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE7_64BIT_BAR_HIGH),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_SCLR_64BIT_BAR_LOW),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_SCLR_64BIT_BAR_HIGH),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_SCLR2_64BIT_BAR_LOW),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_SCLR2_64BIT_BAR_HIGH),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_IMAGEPASTE_LUMA_64BIT_BAR_LOW),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_IMAGEPASTE_LUMA_64BIT_BAR_HIGH),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_IMAGEPASTE_CHROMA_64BIT_BAR_LOW),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_IMAGEPASTE_CHROMA_64BIT_BAR_HIGH),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_PRIVACY_LUMA_64BIT_BAR_LOW),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_PRIVACY_LUMA_64BIT_BAR_HIGH),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_PRIVACY_CHROMA_64BIT_BAR_LOW),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_PRIVACY_CHROMA_64BIT_BAR_HIGH),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_STATUS),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_CTL),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_DATA),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_MASK),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_PAUSE),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_VCPU_CACHE_OFFSET0),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMI_VCPU_CACHE_VMID),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_CLK_EN_VCPU_REPORT),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_CTL),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_CTL2),
> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_SCRATCH1)
> +};
> +
>  #define NORMALIZE_VCN_REG_OFFSET(offset) \
>                 (offset & 0x1FFFF)
>
> @@ -92,6 +218,8 @@ static int vcn_v4_0_3_sw_init(void *handle)
>         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>         struct amdgpu_ring *ring;
>         int i, r, vcn_inst;
> +       uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_4_0_3);
> +       uint32_t *ptr;
>
>         r = amdgpu_vcn_sw_init(adev);
>         if (r)
> @@ -159,6 +287,15 @@ static int vcn_v4_0_3_sw_init(void *handle)
>                 }
>         }
>
> +       /* Allocate memory for VCN IP Dump buffer */
> +       ptr = kcalloc(adev->vcn.num_vcn_inst * reg_count, sizeof(uint32_t), GFP_KERNEL);
> +       if (ptr == NULL) {
> +               DRM_ERROR("Failed to allocate memory for VCN IP Dump\n");
> +               adev->vcn.ip_dump = NULL;
> +       } else {
> +               adev->vcn.ip_dump = ptr;
> +       }
> +
>         return 0;
>  }
>
> @@ -194,6 +331,8 @@ static int vcn_v4_0_3_sw_fini(void *handle)
>
>         r = amdgpu_vcn_sw_fini(adev);
>
> +       kfree(adev->vcn.ip_dump);
> +
>         return r;
>  }
>
> @@ -1684,6 +1823,35 @@ static void vcn_v4_0_3_set_irq_funcs(struct amdgpu_device *adev)
>         adev->vcn.inst->irq.funcs = &vcn_v4_0_3_irq_funcs;
>  }
>
> +static void vcn_v4_0_3_dump_ip_state(void *handle)
> +{
> +       struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> +       int i, j;
> +       bool is_powered;
> +       uint32_t inst_off;
> +       uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_4_0_3);
> +
> +       if (!adev->vcn.ip_dump)
> +               return;
> +
> +       for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
> +               if (adev->vcn.harvest_config & (1 << i))
> +                       continue;
> +
> +               inst_off = i * reg_count;
> +               /* mmUVD_POWER_STATUS is always readable and is first element of the array */
> +               adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, i, regUVD_POWER_STATUS);
>
> I think you need to use the GET_INST() macro to properly handle this.  E.g.,
> vcn_inst = GET_INST(VCN, i);
>
> Thanks for that. In all other cases apart from 4.0.3 it use array index itself as the Instance id.
> GET_INST is only used here in 4.0.3, Is there a special demand for 4.0.3 ?

VCN 4.0.3 is part of MI300 so it requires special handling of the
instances.  Similar for GC 9.4.3.

Alex

> Regards
> Sunil khatri
>
> Alex
>
> +               is_powered = (adev->vcn.ip_dump[inst_off] &
> +                               UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
> +
> +               if (is_powered)
> +                       for (j = 1; j < reg_count; j++)
> +                               adev->vcn.ip_dump[inst_off + j] =
> +                                       RREG32(SOC15_REG_ENTRY_OFFSET_INST(
> +                                               vcn_reg_list_4_0_3[j], i));
> +       }
> +}
> +
>  static const struct amd_ip_funcs vcn_v4_0_3_ip_funcs = {
>         .name = "vcn_v4_0_3",
>         .early_init = vcn_v4_0_3_early_init,
> @@ -1702,7 +1870,7 @@ static const struct amd_ip_funcs vcn_v4_0_3_ip_funcs = {
>         .post_soft_reset = NULL,
>         .set_clockgating_state = vcn_v4_0_3_set_clockgating_state,
>         .set_powergating_state = vcn_v4_0_3_set_powergating_state,
> -       .dump_ip_state = NULL,
> +       .dump_ip_state = vcn_v4_0_3_dump_ip_state,
>         .print_ip_state = NULL,
>  };
>
> --
> 2.34.1
>

^ permalink raw reply	[flat|nested] 28+ messages in thread

* Re: [PATCH v1 05/15] drm/amdgpu: add vcn_v4_0_3 ip dump support
  2024-08-06 21:28   ` Alex Deucher
  2024-08-07  3:47     ` Khatri, Sunil
@ 2024-08-08  5:50     ` Lazar, Lijo
  2024-08-08  7:06       ` Khatri, Sunil
  1 sibling, 1 reply; 28+ messages in thread
From: Lazar, Lijo @ 2024-08-08  5:50 UTC (permalink / raw)
  To: Alex Deucher, Sunil Khatri; +Cc: Alex Deucher, Christian König, amd-gfx



On 8/7/2024 2:58 AM, Alex Deucher wrote:
> On Tue, Aug 6, 2024 at 4:18 AM Sunil Khatri <sunil.khatri@amd.com> wrote:
>>
>> Add support of vcn ip dump in the devcoredump
>> for vcn_v4_0_3.
>>
>> Signed-off-by: Sunil Khatri <sunil.khatri@amd.com>
>> ---
>>  drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c | 170 +++++++++++++++++++++++-
>>  1 file changed, 169 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
>> index 9bae95538b62..dd3baccb2904 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
>> @@ -45,6 +45,132 @@
>>  #define VCN_VID_SOC_ADDRESS_2_0                0x1fb00
>>  #define VCN1_VID_SOC_ADDRESS_3_0       0x48300
>>
>> +static const struct amdgpu_hwip_reg_entry vcn_reg_list_4_0_3[] = {
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_POWER_STATUS),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_STATUS),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_VCPU_CACHE_OFFSET0),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_VCPU_CACHE_OFFSET1),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_VCPU_CACHE_OFFSET2),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CONTEXT_ID),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_DATA0),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_DATA1),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_CMD),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_NC1_64BIT_BAR_HIGH),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_NC1_64BIT_BAR_LOW),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE_VMIDS_MULTI),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_NC_VMIDS_MULTI),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI2),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO2),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI3),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO3),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI4),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO4),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR2),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR2),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR3),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR3),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR4),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR4),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE2),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE3),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_SOFT_RESET),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_SOFT_RESET2),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CGC_GATE),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CGC_STATUS),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CGC_CTRL),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CGC_CTRL3),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_SUVD_CGC_GATE),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_SUVD_CGC_STATUS),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_SUVD_CGC_CTRL),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_SUVD_CGC_GATE2),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE3),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE4),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE4),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_SUVD_CGC_STATUS2),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_SUVD_CGC_GATE2),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_VCPU_CACHE_OFFSET2),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_GPGPU_64BIT_BAR_LOW),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_GPGPU_64BIT_BAR_HIGH),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_CURR_LUMA_64BIT_BAR_LOW),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_CURR_LUMA_64BIT_BAR_HIGH),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_CURR_CHROMA_64BIT_BAR_LOW),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_CURR_CHROMA_64BIT_BAR_HIGH),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_DBW_64BIT_BAR_LOW),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_DBW_64BIT_BAR_HIGH),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_CM_COLOC_64BIT_BAR_LOW),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_CM_COLOC_64BIT_BAR_HIGH),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSP0_64BIT_BAR_LOW),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSP0_64BIT_BAR_HIGH),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSP1_64BIT_BAR_LOW),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSP1_64BIT_BAR_HIGH),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSP2_64BIT_BAR_LOW),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSP2_64BIT_BAR_HIGH),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSP3_64BIT_BAR_LOW),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSP3_64BIT_BAR_HIGH),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSD0_64BIT_BAR_LOW),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSD0_64BIT_BAR_HIGH),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSD1_64BIT_BAR_LOW),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSD1_64BIT_BAR_HIGH),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSD2_64BIT_BAR_LOW),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSD2_64BIT_BAR_HIGH),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSD3_64BIT_BAR_LOW),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSD3_64BIT_BAR_HIGH),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSD4_64BIT_BAR_LOW),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSD4_64BIT_BAR_HIGH),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE3_64BIT_BAR_LOW),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE3_64BIT_BAR_HIGH),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE4_64BIT_BAR_LOW),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE4_64BIT_BAR_HIGH),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE5_64BIT_BAR_LOW),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE5_64BIT_BAR_HIGH),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE6_64BIT_BAR_LOW),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE6_64BIT_BAR_HIGH),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE7_64BIT_BAR_LOW),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE7_64BIT_BAR_HIGH),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_SCLR_64BIT_BAR_LOW),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_SCLR_64BIT_BAR_HIGH),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_SCLR2_64BIT_BAR_LOW),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_SCLR2_64BIT_BAR_HIGH),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_IMAGEPASTE_LUMA_64BIT_BAR_LOW),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_IMAGEPASTE_LUMA_64BIT_BAR_HIGH),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_IMAGEPASTE_CHROMA_64BIT_BAR_LOW),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_IMAGEPASTE_CHROMA_64BIT_BAR_HIGH),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_PRIVACY_LUMA_64BIT_BAR_LOW),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_PRIVACY_LUMA_64BIT_BAR_HIGH),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_PRIVACY_CHROMA_64BIT_BAR_LOW),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_PRIVACY_CHROMA_64BIT_BAR_HIGH),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_STATUS),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_CTL),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_DATA),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_MASK),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_PAUSE),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_VCPU_CACHE_OFFSET0),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMI_VCPU_CACHE_VMID),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_CLK_EN_VCPU_REPORT),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_CTL),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_CTL2),
>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_SCRATCH1)
>> +};
>> +
>>  #define NORMALIZE_VCN_REG_OFFSET(offset) \
>>                 (offset & 0x1FFFF)
>>
>> @@ -92,6 +218,8 @@ static int vcn_v4_0_3_sw_init(void *handle)
>>         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>>         struct amdgpu_ring *ring;
>>         int i, r, vcn_inst;
>> +       uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_4_0_3);
>> +       uint32_t *ptr;
>>
>>         r = amdgpu_vcn_sw_init(adev);
>>         if (r)
>> @@ -159,6 +287,15 @@ static int vcn_v4_0_3_sw_init(void *handle)
>>                 }
>>         }
>>
>> +       /* Allocate memory for VCN IP Dump buffer */
>> +       ptr = kcalloc(adev->vcn.num_vcn_inst * reg_count, sizeof(uint32_t), GFP_KERNEL);
>> +       if (ptr == NULL) {
>> +               DRM_ERROR("Failed to allocate memory for VCN IP Dump\n");
>> +               adev->vcn.ip_dump = NULL;
>> +       } else {
>> +               adev->vcn.ip_dump = ptr;
>> +       }
>> +
>>         return 0;
>>  }
>>
>> @@ -194,6 +331,8 @@ static int vcn_v4_0_3_sw_fini(void *handle)
>>
>>         r = amdgpu_vcn_sw_fini(adev);
>>
>> +       kfree(adev->vcn.ip_dump);
>> +
>>         return r;
>>  }
>>
>> @@ -1684,6 +1823,35 @@ static void vcn_v4_0_3_set_irq_funcs(struct amdgpu_device *adev)
>>         adev->vcn.inst->irq.funcs = &vcn_v4_0_3_irq_funcs;
>>  }
>>
>> +static void vcn_v4_0_3_dump_ip_state(void *handle)
>> +{
>> +       struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> +       int i, j;
>> +       bool is_powered;
>> +       uint32_t inst_off;
>> +       uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_4_0_3);
>> +
>> +       if (!adev->vcn.ip_dump)
>> +               return;
>> +
>> +       for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
>> +               if (adev->vcn.harvest_config & (1 << i))
>> +                       continue;
>> +
>> +               inst_off = i * reg_count;
>> +               /* mmUVD_POWER_STATUS is always readable and is first element of the array */
>> +               adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, i, regUVD_POWER_STATUS);
> 
> I think you need to use the GET_INST() macro to properly handle this.  E.g.,
> vcn_inst = GET_INST(VCN, i);
> 
> Alex
> 
>> +               is_powered = (adev->vcn.ip_dump[inst_off] &
>> +                               UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
>> +
>> +               if (is_powered)
>> +                       for (j = 1; j < reg_count; j++)
>> +                               adev->vcn.ip_dump[inst_off + j] =
>> +                                       RREG32(SOC15_REG_ENTRY_OFFSET_INST(
>> +                                               vcn_reg_list_4_0_3[j], i));

VCN 4.0.3 supports DPG. As far as I understand, most of these registers
are accessed indirectly in DPG mode through indirect SRAM.

Checking UVD power status alone may not be sufficient for direct access.

Thanks,
Lijo

>> +       }
>> +}
>> +
>>  static const struct amd_ip_funcs vcn_v4_0_3_ip_funcs = {
>>         .name = "vcn_v4_0_3",
>>         .early_init = vcn_v4_0_3_early_init,
>> @@ -1702,7 +1870,7 @@ static const struct amd_ip_funcs vcn_v4_0_3_ip_funcs = {
>>         .post_soft_reset = NULL,
>>         .set_clockgating_state = vcn_v4_0_3_set_clockgating_state,
>>         .set_powergating_state = vcn_v4_0_3_set_powergating_state,
>> -       .dump_ip_state = NULL,
>> +       .dump_ip_state = vcn_v4_0_3_dump_ip_state,
>>         .print_ip_state = NULL,
>>  };
>>
>> --
>> 2.34.1
>>

^ permalink raw reply	[flat|nested] 28+ messages in thread

* Re: [PATCH v1 05/15] drm/amdgpu: add vcn_v4_0_3 ip dump support
  2024-08-08  5:50     ` Lazar, Lijo
@ 2024-08-08  7:06       ` Khatri, Sunil
  2024-08-08  7:14         ` Lazar, Lijo
  0 siblings, 1 reply; 28+ messages in thread
From: Khatri, Sunil @ 2024-08-08  7:06 UTC (permalink / raw)
  To: Lazar, Lijo, Alex Deucher, Sunil Khatri
  Cc: Alex Deucher, Christian König, amd-gfx


On 8/8/2024 11:20 AM, Lazar, Lijo wrote:
>
> On 8/7/2024 2:58 AM, Alex Deucher wrote:
>> On Tue, Aug 6, 2024 at 4:18 AM Sunil Khatri <sunil.khatri@amd.com> wrote:
>>> Add support of vcn ip dump in the devcoredump
>>> for vcn_v4_0_3.
>>>
>>> Signed-off-by: Sunil Khatri <sunil.khatri@amd.com>
>>> ---
>>>   drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c | 170 +++++++++++++++++++++++-
>>>   1 file changed, 169 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
>>> index 9bae95538b62..dd3baccb2904 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
>>> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
>>> @@ -45,6 +45,132 @@
>>>   #define VCN_VID_SOC_ADDRESS_2_0                0x1fb00
>>>   #define VCN1_VID_SOC_ADDRESS_3_0       0x48300
>>>
>>> +static const struct amdgpu_hwip_reg_entry vcn_reg_list_4_0_3[] = {
>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_POWER_STATUS),
>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_STATUS),
>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),
>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),
>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),
>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),
>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_VCPU_CACHE_OFFSET0),
>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_VCPU_CACHE_OFFSET1),
>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_VCPU_CACHE_OFFSET2),
>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CONTEXT_ID),
>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_DATA0),
>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_DATA1),
>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_CMD),
>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_NC1_64BIT_BAR_HIGH),
>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_NC1_64BIT_BAR_LOW),
>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH),
>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW),
>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE_VMIDS_MULTI),
>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_NC_VMIDS_MULTI),
>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI),
>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO),
>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI2),
>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO2),
>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI3),
>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO3),
>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI4),
>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO4),
>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR),
>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR),
>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR2),
>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR2),
>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR3),
>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR3),
>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR4),
>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR4),
>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE),
>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE2),
>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE3),
>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_SOFT_RESET),
>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_SOFT_RESET2),
>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CGC_GATE),
>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CGC_STATUS),
>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CGC_CTRL),
>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CGC_CTRL3),
>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_SUVD_CGC_GATE),
>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_SUVD_CGC_STATUS),
>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_SUVD_CGC_CTRL),
>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_SUVD_CGC_GATE2),
>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE3),
>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE4),
>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE4),
>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_SUVD_CGC_STATUS2),
>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_SUVD_CGC_GATE2),
>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_VCPU_CACHE_OFFSET2),
>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_GPGPU_64BIT_BAR_LOW),
>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_GPGPU_64BIT_BAR_HIGH),
>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_CURR_LUMA_64BIT_BAR_LOW),
>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_CURR_LUMA_64BIT_BAR_HIGH),
>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_CURR_CHROMA_64BIT_BAR_LOW),
>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_CURR_CHROMA_64BIT_BAR_HIGH),
>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_DBW_64BIT_BAR_LOW),
>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_DBW_64BIT_BAR_HIGH),
>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_CM_COLOC_64BIT_BAR_LOW),
>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_CM_COLOC_64BIT_BAR_HIGH),
>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSP0_64BIT_BAR_LOW),
>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSP0_64BIT_BAR_HIGH),
>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSP1_64BIT_BAR_LOW),
>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSP1_64BIT_BAR_HIGH),
>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSP2_64BIT_BAR_LOW),
>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSP2_64BIT_BAR_HIGH),
>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSP3_64BIT_BAR_LOW),
>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSP3_64BIT_BAR_HIGH),
>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSD0_64BIT_BAR_LOW),
>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSD0_64BIT_BAR_HIGH),
>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSD1_64BIT_BAR_LOW),
>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSD1_64BIT_BAR_HIGH),
>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSD2_64BIT_BAR_LOW),
>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSD2_64BIT_BAR_HIGH),
>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSD3_64BIT_BAR_LOW),
>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSD3_64BIT_BAR_HIGH),
>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSD4_64BIT_BAR_LOW),
>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSD4_64BIT_BAR_HIGH),
>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),
>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),
>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE3_64BIT_BAR_LOW),
>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE3_64BIT_BAR_HIGH),
>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE4_64BIT_BAR_LOW),
>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE4_64BIT_BAR_HIGH),
>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE5_64BIT_BAR_LOW),
>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE5_64BIT_BAR_HIGH),
>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE6_64BIT_BAR_LOW),
>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE6_64BIT_BAR_HIGH),
>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE7_64BIT_BAR_LOW),
>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE7_64BIT_BAR_HIGH),
>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_SCLR_64BIT_BAR_LOW),
>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_SCLR_64BIT_BAR_HIGH),
>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_SCLR2_64BIT_BAR_LOW),
>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_SCLR2_64BIT_BAR_HIGH),
>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_IMAGEPASTE_LUMA_64BIT_BAR_LOW),
>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_IMAGEPASTE_LUMA_64BIT_BAR_HIGH),
>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_IMAGEPASTE_CHROMA_64BIT_BAR_LOW),
>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_IMAGEPASTE_CHROMA_64BIT_BAR_HIGH),
>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_PRIVACY_LUMA_64BIT_BAR_LOW),
>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_PRIVACY_LUMA_64BIT_BAR_HIGH),
>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_PRIVACY_CHROMA_64BIT_BAR_LOW),
>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_PRIVACY_CHROMA_64BIT_BAR_HIGH),
>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_STATUS),
>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_CTL),
>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_DATA),
>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_MASK),
>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_PAUSE),
>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW),
>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_VCPU_CACHE_OFFSET0),
>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMI_VCPU_CACHE_VMID),
>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_CLK_EN_VCPU_REPORT),
>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_CTL),
>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_CTL2),
>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_SCRATCH1)
>>> +};
>>> +
>>>   #define NORMALIZE_VCN_REG_OFFSET(offset) \
>>>                  (offset & 0x1FFFF)
>>>
>>> @@ -92,6 +218,8 @@ static int vcn_v4_0_3_sw_init(void *handle)
>>>          struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>>>          struct amdgpu_ring *ring;
>>>          int i, r, vcn_inst;
>>> +       uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_4_0_3);
>>> +       uint32_t *ptr;
>>>
>>>          r = amdgpu_vcn_sw_init(adev);
>>>          if (r)
>>> @@ -159,6 +287,15 @@ static int vcn_v4_0_3_sw_init(void *handle)
>>>                  }
>>>          }
>>>
>>> +       /* Allocate memory for VCN IP Dump buffer */
>>> +       ptr = kcalloc(adev->vcn.num_vcn_inst * reg_count, sizeof(uint32_t), GFP_KERNEL);
>>> +       if (ptr == NULL) {
>>> +               DRM_ERROR("Failed to allocate memory for VCN IP Dump\n");
>>> +               adev->vcn.ip_dump = NULL;
>>> +       } else {
>>> +               adev->vcn.ip_dump = ptr;
>>> +       }
>>> +
>>>          return 0;
>>>   }
>>>
>>> @@ -194,6 +331,8 @@ static int vcn_v4_0_3_sw_fini(void *handle)
>>>
>>>          r = amdgpu_vcn_sw_fini(adev);
>>>
>>> +       kfree(adev->vcn.ip_dump);
>>> +
>>>          return r;
>>>   }
>>>
>>> @@ -1684,6 +1823,35 @@ static void vcn_v4_0_3_set_irq_funcs(struct amdgpu_device *adev)
>>>          adev->vcn.inst->irq.funcs = &vcn_v4_0_3_irq_funcs;
>>>   }
>>>
>>> +static void vcn_v4_0_3_dump_ip_state(void *handle)
>>> +{
>>> +       struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>>> +       int i, j;
>>> +       bool is_powered;
>>> +       uint32_t inst_off;
>>> +       uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_4_0_3);
>>> +
>>> +       if (!adev->vcn.ip_dump)
>>> +               return;
>>> +
>>> +       for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
>>> +               if (adev->vcn.harvest_config & (1 << i))
>>> +                       continue;
>>> +
>>> +               inst_off = i * reg_count;
>>> +               /* mmUVD_POWER_STATUS is always readable and is first element of the array */
>>> +               adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, i, regUVD_POWER_STATUS);
>> I think you need to use the GET_INST() macro to properly handle this.  E.g.,
>> vcn_inst = GET_INST(VCN, i);
>>
>> Alex
>>
>>> +               is_powered = (adev->vcn.ip_dump[inst_off] &
>>> +                               UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
>>> +
>>> +               if (is_powered)
>>> +                       for (j = 1; j < reg_count; j++)
>>> +                               adev->vcn.ip_dump[inst_off + j] =
>>> +                                       RREG32(SOC15_REG_ENTRY_OFFSET_INST(
>>> +                                               vcn_reg_list_4_0_3[j], i));
> VCN 4.0.3 supports DPG. As far as I understand, most of these registers
> are accessed indirectly in DPG mode through indirect SRAM.
>
> Checking UVD power status alone may not be sufficient for direct access.

i am following what windows is following and most of the registers are 
directly access but i agree some might not be.  We are assuming in case 
of a VCN hang it should be in good power state and we should be able to 
read most of the registers. Based on further feedback will do the 
needful but right now the point where we are dumping the registers we 
could not make any change in power state.

Regards
Sunil khatri

>
> Thanks,
> Lijo
>
>>> +       }
>>> +}
>>> +
>>>   static const struct amd_ip_funcs vcn_v4_0_3_ip_funcs = {
>>>          .name = "vcn_v4_0_3",
>>>          .early_init = vcn_v4_0_3_early_init,
>>> @@ -1702,7 +1870,7 @@ static const struct amd_ip_funcs vcn_v4_0_3_ip_funcs = {
>>>          .post_soft_reset = NULL,
>>>          .set_clockgating_state = vcn_v4_0_3_set_clockgating_state,
>>>          .set_powergating_state = vcn_v4_0_3_set_powergating_state,
>>> -       .dump_ip_state = NULL,
>>> +       .dump_ip_state = vcn_v4_0_3_dump_ip_state,
>>>          .print_ip_state = NULL,
>>>   };
>>>
>>> --
>>> 2.34.1
>>>

^ permalink raw reply	[flat|nested] 28+ messages in thread

* Re: [PATCH v1 05/15] drm/amdgpu: add vcn_v4_0_3 ip dump support
  2024-08-08  7:06       ` Khatri, Sunil
@ 2024-08-08  7:14         ` Lazar, Lijo
  2024-08-08  7:29           ` Khatri, Sunil
  0 siblings, 1 reply; 28+ messages in thread
From: Lazar, Lijo @ 2024-08-08  7:14 UTC (permalink / raw)
  To: Khatri, Sunil, Alex Deucher, Sunil Khatri
  Cc: Alex Deucher, Christian König, amd-gfx



On 8/8/2024 12:36 PM, Khatri, Sunil wrote:
> 
> On 8/8/2024 11:20 AM, Lazar, Lijo wrote:
>>
>> On 8/7/2024 2:58 AM, Alex Deucher wrote:
>>> On Tue, Aug 6, 2024 at 4:18 AM Sunil Khatri <sunil.khatri@amd.com>
>>> wrote:
>>>> Add support of vcn ip dump in the devcoredump
>>>> for vcn_v4_0_3.
>>>>
>>>> Signed-off-by: Sunil Khatri <sunil.khatri@amd.com>
>>>> ---
>>>>   drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c | 170
>>>> +++++++++++++++++++++++-
>>>>   1 file changed, 169 insertions(+), 1 deletion(-)
>>>>
>>>> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
>>>> b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
>>>> index 9bae95538b62..dd3baccb2904 100644
>>>> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
>>>> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
>>>> @@ -45,6 +45,132 @@
>>>>   #define VCN_VID_SOC_ADDRESS_2_0                0x1fb00
>>>>   #define VCN1_VID_SOC_ADDRESS_3_0       0x48300
>>>>
>>>> +static const struct amdgpu_hwip_reg_entry vcn_reg_list_4_0_3[] = {
>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_POWER_STATUS),
>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_STATUS),
>>>> +       SOC15_REG_ENTRY_STR(VCN, 0,
>>>> regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
>>>> +       SOC15_REG_ENTRY_STR(VCN, 0,
>>>> regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
>>>> +       SOC15_REG_ENTRY_STR(VCN, 0,
>>>> regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),
>>>> +       SOC15_REG_ENTRY_STR(VCN, 0,
>>>> regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),
>>>> +       SOC15_REG_ENTRY_STR(VCN, 0,
>>>> regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),
>>>> +       SOC15_REG_ENTRY_STR(VCN, 0,
>>>> regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),
>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_VCPU_CACHE_OFFSET0),
>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_VCPU_CACHE_OFFSET1),
>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_VCPU_CACHE_OFFSET2),
>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CONTEXT_ID),
>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_DATA0),
>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_DATA1),
>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_CMD),
>>>> +       SOC15_REG_ENTRY_STR(VCN, 0,
>>>> regUVD_LMI_VCPU_NC1_64BIT_BAR_HIGH),
>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_NC1_64BIT_BAR_LOW),
>>>> +       SOC15_REG_ENTRY_STR(VCN, 0,
>>>> regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH),
>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW),
>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE_VMIDS_MULTI),
>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_NC_VMIDS_MULTI),
>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI),
>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO),
>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI2),
>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO2),
>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI3),
>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO3),
>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI4),
>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO4),
>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR),
>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR),
>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR2),
>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR2),
>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR3),
>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR3),
>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR4),
>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR4),
>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE),
>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE2),
>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE3),
>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_SOFT_RESET),
>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_SOFT_RESET2),
>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CGC_GATE),
>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CGC_STATUS),
>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CGC_CTRL),
>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CGC_CTRL3),
>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_SUVD_CGC_GATE),
>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_SUVD_CGC_STATUS),
>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_SUVD_CGC_CTRL),
>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_SUVD_CGC_GATE2),
>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE3),
>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE4),
>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE4),
>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_SUVD_CGC_STATUS2),
>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_SUVD_CGC_GATE2),
>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_VCPU_CACHE_OFFSET2),
>>>> +       SOC15_REG_ENTRY_STR(VCN, 0,
>>>> regUVD_LMI_MIF_GPGPU_64BIT_BAR_LOW),
>>>> +       SOC15_REG_ENTRY_STR(VCN, 0,
>>>> regUVD_LMI_MIF_GPGPU_64BIT_BAR_HIGH),
>>>> +       SOC15_REG_ENTRY_STR(VCN, 0,
>>>> regUVD_LMI_MIF_CURR_LUMA_64BIT_BAR_LOW),
>>>> +       SOC15_REG_ENTRY_STR(VCN, 0,
>>>> regUVD_LMI_MIF_CURR_LUMA_64BIT_BAR_HIGH),
>>>> +       SOC15_REG_ENTRY_STR(VCN, 0,
>>>> regUVD_LMI_MIF_CURR_CHROMA_64BIT_BAR_LOW),
>>>> +       SOC15_REG_ENTRY_STR(VCN, 0,
>>>> regUVD_LMI_MIF_CURR_CHROMA_64BIT_BAR_HIGH),
>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_DBW_64BIT_BAR_LOW),
>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_DBW_64BIT_BAR_HIGH),
>>>> +       SOC15_REG_ENTRY_STR(VCN, 0,
>>>> regUVD_LMI_MIF_CM_COLOC_64BIT_BAR_LOW),
>>>> +       SOC15_REG_ENTRY_STR(VCN, 0,
>>>> regUVD_LMI_MIF_CM_COLOC_64BIT_BAR_HIGH),
>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSP0_64BIT_BAR_LOW),
>>>> +       SOC15_REG_ENTRY_STR(VCN, 0,
>>>> regUVD_LMI_MIF_BSP0_64BIT_BAR_HIGH),
>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSP1_64BIT_BAR_LOW),
>>>> +       SOC15_REG_ENTRY_STR(VCN, 0,
>>>> regUVD_LMI_MIF_BSP1_64BIT_BAR_HIGH),
>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSP2_64BIT_BAR_LOW),
>>>> +       SOC15_REG_ENTRY_STR(VCN, 0,
>>>> regUVD_LMI_MIF_BSP2_64BIT_BAR_HIGH),
>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSP3_64BIT_BAR_LOW),
>>>> +       SOC15_REG_ENTRY_STR(VCN, 0,
>>>> regUVD_LMI_MIF_BSP3_64BIT_BAR_HIGH),
>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSD0_64BIT_BAR_LOW),
>>>> +       SOC15_REG_ENTRY_STR(VCN, 0,
>>>> regUVD_LMI_MIF_BSD0_64BIT_BAR_HIGH),
>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSD1_64BIT_BAR_LOW),
>>>> +       SOC15_REG_ENTRY_STR(VCN, 0,
>>>> regUVD_LMI_MIF_BSD1_64BIT_BAR_HIGH),
>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSD2_64BIT_BAR_LOW),
>>>> +       SOC15_REG_ENTRY_STR(VCN, 0,
>>>> regUVD_LMI_MIF_BSD2_64BIT_BAR_HIGH),
>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSD3_64BIT_BAR_LOW),
>>>> +       SOC15_REG_ENTRY_STR(VCN, 0,
>>>> regUVD_LMI_MIF_BSD3_64BIT_BAR_HIGH),
>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSD4_64BIT_BAR_LOW),
>>>> +       SOC15_REG_ENTRY_STR(VCN, 0,
>>>> regUVD_LMI_MIF_BSD4_64BIT_BAR_HIGH),
>>>> +       SOC15_REG_ENTRY_STR(VCN, 0,
>>>> regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
>>>> +       SOC15_REG_ENTRY_STR(VCN, 0,
>>>> regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
>>>> +       SOC15_REG_ENTRY_STR(VCN, 0,
>>>> regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),
>>>> +       SOC15_REG_ENTRY_STR(VCN, 0,
>>>> regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),
>>>> +       SOC15_REG_ENTRY_STR(VCN, 0,
>>>> regUVD_LMI_VCPU_CACHE3_64BIT_BAR_LOW),
>>>> +       SOC15_REG_ENTRY_STR(VCN, 0,
>>>> regUVD_LMI_VCPU_CACHE3_64BIT_BAR_HIGH),
>>>> +       SOC15_REG_ENTRY_STR(VCN, 0,
>>>> regUVD_LMI_VCPU_CACHE4_64BIT_BAR_LOW),
>>>> +       SOC15_REG_ENTRY_STR(VCN, 0,
>>>> regUVD_LMI_VCPU_CACHE4_64BIT_BAR_HIGH),
>>>> +       SOC15_REG_ENTRY_STR(VCN, 0,
>>>> regUVD_LMI_VCPU_CACHE5_64BIT_BAR_LOW),
>>>> +       SOC15_REG_ENTRY_STR(VCN, 0,
>>>> regUVD_LMI_VCPU_CACHE5_64BIT_BAR_HIGH),
>>>> +       SOC15_REG_ENTRY_STR(VCN, 0,
>>>> regUVD_LMI_VCPU_CACHE6_64BIT_BAR_LOW),
>>>> +       SOC15_REG_ENTRY_STR(VCN, 0,
>>>> regUVD_LMI_VCPU_CACHE6_64BIT_BAR_HIGH),
>>>> +       SOC15_REG_ENTRY_STR(VCN, 0,
>>>> regUVD_LMI_VCPU_CACHE7_64BIT_BAR_LOW),
>>>> +       SOC15_REG_ENTRY_STR(VCN, 0,
>>>> regUVD_LMI_VCPU_CACHE7_64BIT_BAR_HIGH),
>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_SCLR_64BIT_BAR_LOW),
>>>> +       SOC15_REG_ENTRY_STR(VCN, 0,
>>>> regUVD_LMI_MIF_SCLR_64BIT_BAR_HIGH),
>>>> +       SOC15_REG_ENTRY_STR(VCN, 0,
>>>> regUVD_LMI_MIF_SCLR2_64BIT_BAR_LOW),
>>>> +       SOC15_REG_ENTRY_STR(VCN, 0,
>>>> regUVD_LMI_MIF_SCLR2_64BIT_BAR_HIGH),
>>>> +       SOC15_REG_ENTRY_STR(VCN, 0,
>>>> regUVD_LMI_MIF_IMAGEPASTE_LUMA_64BIT_BAR_LOW),
>>>> +       SOC15_REG_ENTRY_STR(VCN, 0,
>>>> regUVD_LMI_MIF_IMAGEPASTE_LUMA_64BIT_BAR_HIGH),
>>>> +       SOC15_REG_ENTRY_STR(VCN, 0,
>>>> regUVD_LMI_MIF_IMAGEPASTE_CHROMA_64BIT_BAR_LOW),
>>>> +       SOC15_REG_ENTRY_STR(VCN, 0,
>>>> regUVD_LMI_MIF_IMAGEPASTE_CHROMA_64BIT_BAR_HIGH),
>>>> +       SOC15_REG_ENTRY_STR(VCN, 0,
>>>> regUVD_LMI_MIF_PRIVACY_LUMA_64BIT_BAR_LOW),
>>>> +       SOC15_REG_ENTRY_STR(VCN, 0,
>>>> regUVD_LMI_MIF_PRIVACY_LUMA_64BIT_BAR_HIGH),
>>>> +       SOC15_REG_ENTRY_STR(VCN, 0,
>>>> regUVD_LMI_MIF_PRIVACY_CHROMA_64BIT_BAR_LOW),
>>>> +       SOC15_REG_ENTRY_STR(VCN, 0,
>>>> regUVD_LMI_MIF_PRIVACY_CHROMA_64BIT_BAR_HIGH),
>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_STATUS),
>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_CTL),
>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_DATA),
>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_MASK),
>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_PAUSE),
>>>> +       SOC15_REG_ENTRY_STR(VCN, 0,
>>>> regUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW),
>>>> +       SOC15_REG_ENTRY_STR(VCN, 0,
>>>> regUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_VCPU_CACHE_OFFSET0),
>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMI_VCPU_CACHE_VMID),
>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_CLK_EN_VCPU_REPORT),
>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_CTL),
>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_CTL2),
>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_SCRATCH1)
>>>> +};
>>>> +
>>>>   #define NORMALIZE_VCN_REG_OFFSET(offset) \
>>>>                  (offset & 0x1FFFF)
>>>>
>>>> @@ -92,6 +218,8 @@ static int vcn_v4_0_3_sw_init(void *handle)
>>>>          struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>>>>          struct amdgpu_ring *ring;
>>>>          int i, r, vcn_inst;
>>>> +       uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_4_0_3);
>>>> +       uint32_t *ptr;
>>>>
>>>>          r = amdgpu_vcn_sw_init(adev);
>>>>          if (r)
>>>> @@ -159,6 +287,15 @@ static int vcn_v4_0_3_sw_init(void *handle)
>>>>                  }
>>>>          }
>>>>
>>>> +       /* Allocate memory for VCN IP Dump buffer */
>>>> +       ptr = kcalloc(adev->vcn.num_vcn_inst * reg_count,
>>>> sizeof(uint32_t), GFP_KERNEL);
>>>> +       if (ptr == NULL) {
>>>> +               DRM_ERROR("Failed to allocate memory for VCN IP
>>>> Dump\n");
>>>> +               adev->vcn.ip_dump = NULL;
>>>> +       } else {
>>>> +               adev->vcn.ip_dump = ptr;
>>>> +       }
>>>> +
>>>>          return 0;
>>>>   }
>>>>
>>>> @@ -194,6 +331,8 @@ static int vcn_v4_0_3_sw_fini(void *handle)
>>>>
>>>>          r = amdgpu_vcn_sw_fini(adev);
>>>>
>>>> +       kfree(adev->vcn.ip_dump);
>>>> +
>>>>          return r;
>>>>   }
>>>>
>>>> @@ -1684,6 +1823,35 @@ static void vcn_v4_0_3_set_irq_funcs(struct
>>>> amdgpu_device *adev)
>>>>          adev->vcn.inst->irq.funcs = &vcn_v4_0_3_irq_funcs;
>>>>   }
>>>>
>>>> +static void vcn_v4_0_3_dump_ip_state(void *handle)
>>>> +{
>>>> +       struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>>>> +       int i, j;
>>>> +       bool is_powered;
>>>> +       uint32_t inst_off;
>>>> +       uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_4_0_3);
>>>> +
>>>> +       if (!adev->vcn.ip_dump)
>>>> +               return;
>>>> +
>>>> +       for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
>>>> +               if (adev->vcn.harvest_config & (1 << i))
>>>> +                       continue;
>>>> +
>>>> +               inst_off = i * reg_count;
>>>> +               /* mmUVD_POWER_STATUS is always readable and is
>>>> first element of the array */
>>>> +               adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, i,
>>>> regUVD_POWER_STATUS);
>>> I think you need to use the GET_INST() macro to properly handle
>>> this.  E.g.,
>>> vcn_inst = GET_INST(VCN, i);
>>>
>>> Alex
>>>
>>>> +               is_powered = (adev->vcn.ip_dump[inst_off] &
>>>> +                              
>>>> UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
>>>> +
>>>> +               if (is_powered)
>>>> +                       for (j = 1; j < reg_count; j++)
>>>> +                               adev->vcn.ip_dump[inst_off + j] =
>>>> +                                      
>>>> RREG32(SOC15_REG_ENTRY_OFFSET_INST(
>>>> +                                              
>>>> vcn_reg_list_4_0_3[j], i));
>> VCN 4.0.3 supports DPG. As far as I understand, most of these registers
>> are accessed indirectly in DPG mode through indirect SRAM.
>>
>> Checking UVD power status alone may not be sufficient for direct access.
> 
> i am following what windows is following and most of the registers are
> directly access but i agree some might not be.

Whether Windows logic works is the first question other than the
secondary question of value in logging some of those registers.

  We are assuming in case
> of a VCN hang it should be in good power state and we should be able to
> read most of the registers. 

'is_powered ' - It's quite obvious that there is no assumption like that
:). Secondly, when there are multiple instances where only one VCN
instance got hung, and others may not be - this assumption won't hold good.

Thanks,
Lijo

> Based on further feedback will do the
> needful but right now the point where we are dumping the registers we
> could not make any change in power state.
> 
> Regards
> Sunil khatri
> 
>>
>> Thanks,
>> Lijo
>>
>>>> +       }
>>>> +}
>>>> +
>>>>   static const struct amd_ip_funcs vcn_v4_0_3_ip_funcs = {
>>>>          .name = "vcn_v4_0_3",
>>>>          .early_init = vcn_v4_0_3_early_init,
>>>> @@ -1702,7 +1870,7 @@ static const struct amd_ip_funcs
>>>> vcn_v4_0_3_ip_funcs = {
>>>>          .post_soft_reset = NULL,
>>>>          .set_clockgating_state = vcn_v4_0_3_set_clockgating_state,
>>>>          .set_powergating_state = vcn_v4_0_3_set_powergating_state,
>>>> -       .dump_ip_state = NULL,
>>>> +       .dump_ip_state = vcn_v4_0_3_dump_ip_state,
>>>>          .print_ip_state = NULL,
>>>>   };
>>>>
>>>> -- 
>>>> 2.34.1
>>>>

^ permalink raw reply	[flat|nested] 28+ messages in thread

* Re: [PATCH v1 05/15] drm/amdgpu: add vcn_v4_0_3 ip dump support
  2024-08-08  7:14         ` Lazar, Lijo
@ 2024-08-08  7:29           ` Khatri, Sunil
  2024-08-08  9:29             ` Sundararaju, Sathishkumar
  0 siblings, 1 reply; 28+ messages in thread
From: Khatri, Sunil @ 2024-08-08  7:29 UTC (permalink / raw)
  To: Lazar, Lijo, Alex Deucher, Sunil Khatri
  Cc: Alex Deucher, Christian König, amd-gfx


On 8/8/2024 12:44 PM, Lazar, Lijo wrote:
>
> On 8/8/2024 12:36 PM, Khatri, Sunil wrote:
>> On 8/8/2024 11:20 AM, Lazar, Lijo wrote:
>>> On 8/7/2024 2:58 AM, Alex Deucher wrote:
>>>> On Tue, Aug 6, 2024 at 4:18 AM Sunil Khatri <sunil.khatri@amd.com>
>>>> wrote:
>>>>> Add support of vcn ip dump in the devcoredump
>>>>> for vcn_v4_0_3.
>>>>>
>>>>> Signed-off-by: Sunil Khatri <sunil.khatri@amd.com>
>>>>> ---
>>>>>    drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c | 170
>>>>> +++++++++++++++++++++++-
>>>>>    1 file changed, 169 insertions(+), 1 deletion(-)
>>>>>
>>>>> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
>>>>> b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
>>>>> index 9bae95538b62..dd3baccb2904 100644
>>>>> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
>>>>> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
>>>>> @@ -45,6 +45,132 @@
>>>>>    #define VCN_VID_SOC_ADDRESS_2_0                0x1fb00
>>>>>    #define VCN1_VID_SOC_ADDRESS_3_0       0x48300
>>>>>
>>>>> +static const struct amdgpu_hwip_reg_entry vcn_reg_list_4_0_3[] = {
>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_POWER_STATUS),
>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_STATUS),
>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0,
>>>>> regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0,
>>>>> regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0,
>>>>> regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),
>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0,
>>>>> regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),
>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0,
>>>>> regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),
>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0,
>>>>> regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),
>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_VCPU_CACHE_OFFSET0),
>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_VCPU_CACHE_OFFSET1),
>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_VCPU_CACHE_OFFSET2),
>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CONTEXT_ID),
>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_DATA0),
>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_DATA1),
>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_CMD),
>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0,
>>>>> regUVD_LMI_VCPU_NC1_64BIT_BAR_HIGH),
>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_NC1_64BIT_BAR_LOW),
>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0,
>>>>> regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH),
>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW),
>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE_VMIDS_MULTI),
>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_NC_VMIDS_MULTI),
>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI),
>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO),
>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI2),
>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO2),
>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI3),
>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO3),
>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI4),
>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO4),
>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR),
>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR),
>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR2),
>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR2),
>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR3),
>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR3),
>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR4),
>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR4),
>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE),
>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE2),
>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE3),
>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_SOFT_RESET),
>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_SOFT_RESET2),
>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CGC_GATE),
>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CGC_STATUS),
>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CGC_CTRL),
>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CGC_CTRL3),
>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_SUVD_CGC_GATE),
>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_SUVD_CGC_STATUS),
>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_SUVD_CGC_CTRL),
>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_SUVD_CGC_GATE2),
>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE3),
>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE4),
>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE4),
>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_SUVD_CGC_STATUS2),
>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_SUVD_CGC_GATE2),
>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_VCPU_CACHE_OFFSET2),
>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0,
>>>>> regUVD_LMI_MIF_GPGPU_64BIT_BAR_LOW),
>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0,
>>>>> regUVD_LMI_MIF_GPGPU_64BIT_BAR_HIGH),
>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0,
>>>>> regUVD_LMI_MIF_CURR_LUMA_64BIT_BAR_LOW),
>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0,
>>>>> regUVD_LMI_MIF_CURR_LUMA_64BIT_BAR_HIGH),
>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0,
>>>>> regUVD_LMI_MIF_CURR_CHROMA_64BIT_BAR_LOW),
>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0,
>>>>> regUVD_LMI_MIF_CURR_CHROMA_64BIT_BAR_HIGH),
>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_DBW_64BIT_BAR_LOW),
>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_DBW_64BIT_BAR_HIGH),
>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0,
>>>>> regUVD_LMI_MIF_CM_COLOC_64BIT_BAR_LOW),
>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0,
>>>>> regUVD_LMI_MIF_CM_COLOC_64BIT_BAR_HIGH),
>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSP0_64BIT_BAR_LOW),
>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0,
>>>>> regUVD_LMI_MIF_BSP0_64BIT_BAR_HIGH),
>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSP1_64BIT_BAR_LOW),
>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0,
>>>>> regUVD_LMI_MIF_BSP1_64BIT_BAR_HIGH),
>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSP2_64BIT_BAR_LOW),
>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0,
>>>>> regUVD_LMI_MIF_BSP2_64BIT_BAR_HIGH),
>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSP3_64BIT_BAR_LOW),
>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0,
>>>>> regUVD_LMI_MIF_BSP3_64BIT_BAR_HIGH),
>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSD0_64BIT_BAR_LOW),
>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0,
>>>>> regUVD_LMI_MIF_BSD0_64BIT_BAR_HIGH),
>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSD1_64BIT_BAR_LOW),
>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0,
>>>>> regUVD_LMI_MIF_BSD1_64BIT_BAR_HIGH),
>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSD2_64BIT_BAR_LOW),
>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0,
>>>>> regUVD_LMI_MIF_BSD2_64BIT_BAR_HIGH),
>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSD3_64BIT_BAR_LOW),
>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0,
>>>>> regUVD_LMI_MIF_BSD3_64BIT_BAR_HIGH),
>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSD4_64BIT_BAR_LOW),
>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0,
>>>>> regUVD_LMI_MIF_BSD4_64BIT_BAR_HIGH),
>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0,
>>>>> regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0,
>>>>> regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0,
>>>>> regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),
>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0,
>>>>> regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),
>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0,
>>>>> regUVD_LMI_VCPU_CACHE3_64BIT_BAR_LOW),
>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0,
>>>>> regUVD_LMI_VCPU_CACHE3_64BIT_BAR_HIGH),
>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0,
>>>>> regUVD_LMI_VCPU_CACHE4_64BIT_BAR_LOW),
>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0,
>>>>> regUVD_LMI_VCPU_CACHE4_64BIT_BAR_HIGH),
>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0,
>>>>> regUVD_LMI_VCPU_CACHE5_64BIT_BAR_LOW),
>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0,
>>>>> regUVD_LMI_VCPU_CACHE5_64BIT_BAR_HIGH),
>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0,
>>>>> regUVD_LMI_VCPU_CACHE6_64BIT_BAR_LOW),
>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0,
>>>>> regUVD_LMI_VCPU_CACHE6_64BIT_BAR_HIGH),
>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0,
>>>>> regUVD_LMI_VCPU_CACHE7_64BIT_BAR_LOW),
>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0,
>>>>> regUVD_LMI_VCPU_CACHE7_64BIT_BAR_HIGH),
>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_SCLR_64BIT_BAR_LOW),
>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0,
>>>>> regUVD_LMI_MIF_SCLR_64BIT_BAR_HIGH),
>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0,
>>>>> regUVD_LMI_MIF_SCLR2_64BIT_BAR_LOW),
>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0,
>>>>> regUVD_LMI_MIF_SCLR2_64BIT_BAR_HIGH),
>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0,
>>>>> regUVD_LMI_MIF_IMAGEPASTE_LUMA_64BIT_BAR_LOW),
>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0,
>>>>> regUVD_LMI_MIF_IMAGEPASTE_LUMA_64BIT_BAR_HIGH),
>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0,
>>>>> regUVD_LMI_MIF_IMAGEPASTE_CHROMA_64BIT_BAR_LOW),
>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0,
>>>>> regUVD_LMI_MIF_IMAGEPASTE_CHROMA_64BIT_BAR_HIGH),
>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0,
>>>>> regUVD_LMI_MIF_PRIVACY_LUMA_64BIT_BAR_LOW),
>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0,
>>>>> regUVD_LMI_MIF_PRIVACY_LUMA_64BIT_BAR_HIGH),
>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0,
>>>>> regUVD_LMI_MIF_PRIVACY_CHROMA_64BIT_BAR_LOW),
>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0,
>>>>> regUVD_LMI_MIF_PRIVACY_CHROMA_64BIT_BAR_HIGH),
>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_STATUS),
>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_CTL),
>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_DATA),
>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_MASK),
>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_PAUSE),
>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0,
>>>>> regUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW),
>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0,
>>>>> regUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_VCPU_CACHE_OFFSET0),
>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMI_VCPU_CACHE_VMID),
>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_CLK_EN_VCPU_REPORT),
>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_CTL),
>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_CTL2),
>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_SCRATCH1)
>>>>> +};
>>>>> +
>>>>>    #define NORMALIZE_VCN_REG_OFFSET(offset) \
>>>>>                   (offset & 0x1FFFF)
>>>>>
>>>>> @@ -92,6 +218,8 @@ static int vcn_v4_0_3_sw_init(void *handle)
>>>>>           struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>>>>>           struct amdgpu_ring *ring;
>>>>>           int i, r, vcn_inst;
>>>>> +       uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_4_0_3);
>>>>> +       uint32_t *ptr;
>>>>>
>>>>>           r = amdgpu_vcn_sw_init(adev);
>>>>>           if (r)
>>>>> @@ -159,6 +287,15 @@ static int vcn_v4_0_3_sw_init(void *handle)
>>>>>                   }
>>>>>           }
>>>>>
>>>>> +       /* Allocate memory for VCN IP Dump buffer */
>>>>> +       ptr = kcalloc(adev->vcn.num_vcn_inst * reg_count,
>>>>> sizeof(uint32_t), GFP_KERNEL);
>>>>> +       if (ptr == NULL) {
>>>>> +               DRM_ERROR("Failed to allocate memory for VCN IP
>>>>> Dump\n");
>>>>> +               adev->vcn.ip_dump = NULL;
>>>>> +       } else {
>>>>> +               adev->vcn.ip_dump = ptr;
>>>>> +       }
>>>>> +
>>>>>           return 0;
>>>>>    }
>>>>>
>>>>> @@ -194,6 +331,8 @@ static int vcn_v4_0_3_sw_fini(void *handle)
>>>>>
>>>>>           r = amdgpu_vcn_sw_fini(adev);
>>>>>
>>>>> +       kfree(adev->vcn.ip_dump);
>>>>> +
>>>>>           return r;
>>>>>    }
>>>>>
>>>>> @@ -1684,6 +1823,35 @@ static void vcn_v4_0_3_set_irq_funcs(struct
>>>>> amdgpu_device *adev)
>>>>>           adev->vcn.inst->irq.funcs = &vcn_v4_0_3_irq_funcs;
>>>>>    }
>>>>>
>>>>> +static void vcn_v4_0_3_dump_ip_state(void *handle)
>>>>> +{
>>>>> +       struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>>>>> +       int i, j;
>>>>> +       bool is_powered;
>>>>> +       uint32_t inst_off;
>>>>> +       uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_4_0_3);
>>>>> +
>>>>> +       if (!adev->vcn.ip_dump)
>>>>> +               return;
>>>>> +
>>>>> +       for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
>>>>> +               if (adev->vcn.harvest_config & (1 << i))
>>>>> +                       continue;
>>>>> +
>>>>> +               inst_off = i * reg_count;
>>>>> +               /* mmUVD_POWER_STATUS is always readable and is
>>>>> first element of the array */
>>>>> +               adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, i,
>>>>> regUVD_POWER_STATUS);
>>>> I think you need to use the GET_INST() macro to properly handle
>>>> this.  E.g.,
>>>> vcn_inst = GET_INST(VCN, i);
>>>>
>>>> Alex
>>>>
>>>>> +               is_powered = (adev->vcn.ip_dump[inst_off] &
>>>>> +
>>>>> UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
>>>>> +
>>>>> +               if (is_powered)
>>>>> +                       for (j = 1; j < reg_count; j++)
>>>>> +                               adev->vcn.ip_dump[inst_off + j] =
>>>>> +
>>>>> RREG32(SOC15_REG_ENTRY_OFFSET_INST(
>>>>> +
>>>>> vcn_reg_list_4_0_3[j], i));
>>> VCN 4.0.3 supports DPG. As far as I understand, most of these registers
>>> are accessed indirectly in DPG mode through indirect SRAM.
>>>
>>> Checking UVD power status alone may not be sufficient for direct access.
>> i am following what windows is following and most of the registers are
>> directly access but i agree some might not be.
> Whether Windows logic works is the first question other than the
> secondary question of value in logging some of those registers.
True. Cant say but the bare minimum we could do for a starting point was 
the intent. Dumping VCN registers is a challenge due to its dynamic 
power gating controlled by firmware.
based on VCN fw guys probability is in case of VCN hung we might be in 
power up state to read some of the status registers if not all.
>
>    We are assuming in case
>> of a VCN hang it should be in good power state and we should be able to
>> read most of the registers.
> 'is_powered ' - It's quite obvious that there is no assumption like that
> :). Secondly, when there are multiple instances where only one VCN
> instance got hung, and others may not be - this assumption won't hold good.

The principal is we are dumping all the IP's irrespective of who caused 
the hang so no matter what instance causes hang the registers are dumped 
for all. The vcn hang information is captured in the kernel logs

that can be used along with it. Also is_powered is per instance and if 
its powered off we arent going to read the register at all.

Based on the experiments i did in case of hang caused by gfx i found vcn 
to be powered off as there isnt any work load on VCN to keep it up. We 
will improvise on the functionality as we start seeing issues.

> Thanks,
> Lijo
>
>> Based on further feedback will do the
>> needful but right now the point where we are dumping the registers we
>> could not make any change in power state.
>>
>> Regards
>> Sunil khatri
>>
>>> Thanks,
>>> Lijo
>>>
>>>>> +       }
>>>>> +}
>>>>> +
>>>>>    static const struct amd_ip_funcs vcn_v4_0_3_ip_funcs = {
>>>>>           .name = "vcn_v4_0_3",
>>>>>           .early_init = vcn_v4_0_3_early_init,
>>>>> @@ -1702,7 +1870,7 @@ static const struct amd_ip_funcs
>>>>> vcn_v4_0_3_ip_funcs = {
>>>>>           .post_soft_reset = NULL,
>>>>>           .set_clockgating_state = vcn_v4_0_3_set_clockgating_state,
>>>>>           .set_powergating_state = vcn_v4_0_3_set_powergating_state,
>>>>> -       .dump_ip_state = NULL,
>>>>> +       .dump_ip_state = vcn_v4_0_3_dump_ip_state,
>>>>>           .print_ip_state = NULL,
>>>>>    };
>>>>>
>>>>> -- 
>>>>> 2.34.1
>>>>>

^ permalink raw reply	[flat|nested] 28+ messages in thread

* Re: [PATCH v1 05/15] drm/amdgpu: add vcn_v4_0_3 ip dump support
  2024-08-08  7:29           ` Khatri, Sunil
@ 2024-08-08  9:29             ` Sundararaju, Sathishkumar
  0 siblings, 0 replies; 28+ messages in thread
From: Sundararaju, Sathishkumar @ 2024-08-08  9:29 UTC (permalink / raw)
  To: Khatri, Sunil, Lazar, Lijo, Alex Deucher, Sunil Khatri
  Cc: Alex Deucher, Christian König, amd-gfx


if adev->vcn.cur_state == AMD_PG_STATE_UNGATE then vcn is powered on and 
holding vcn.vcn_pg_lock to access it is safe.

And cancelling vcn.idle_work must be the first thing to do, else you can 
run into a vcn power off in the middle of register dump which you want 
to avoid i think.

This is safer check than accessing registers to find out if powered on 
which is asynchronous w.r.t job handling path. I am not aware of all the 
possible states during which ip_dump can be triggered, so ignore if 
above isn't a possible scenario.


Regards,

Sathish

On 8/8/2024 12:59 PM, Khatri, Sunil wrote:
>
> On 8/8/2024 12:44 PM, Lazar, Lijo wrote:
>>
>> On 8/8/2024 12:36 PM, Khatri, Sunil wrote:
>>> On 8/8/2024 11:20 AM, Lazar, Lijo wrote:
>>>> On 8/7/2024 2:58 AM, Alex Deucher wrote:
>>>>> On Tue, Aug 6, 2024 at 4:18 AM Sunil Khatri <sunil.khatri@amd.com>
>>>>> wrote:
>>>>>> Add support of vcn ip dump in the devcoredump
>>>>>> for vcn_v4_0_3.
>>>>>>
>>>>>> Signed-off-by: Sunil Khatri <sunil.khatri@amd.com>
>>>>>> ---
>>>>>>    drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c | 170
>>>>>> +++++++++++++++++++++++-
>>>>>>    1 file changed, 169 insertions(+), 1 deletion(-)
>>>>>>
>>>>>> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
>>>>>> b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
>>>>>> index 9bae95538b62..dd3baccb2904 100644
>>>>>> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
>>>>>> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
>>>>>> @@ -45,6 +45,132 @@
>>>>>>    #define VCN_VID_SOC_ADDRESS_2_0 0x1fb00
>>>>>>    #define VCN1_VID_SOC_ADDRESS_3_0       0x48300
>>>>>>
>>>>>> +static const struct amdgpu_hwip_reg_entry vcn_reg_list_4_0_3[] = {
>>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_POWER_STATUS),
>>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_STATUS),
>>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0,
>>>>>> regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
>>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0,
>>>>>> regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
>>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0,
>>>>>> regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),
>>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0,
>>>>>> regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),
>>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0,
>>>>>> regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),
>>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0,
>>>>>> regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),
>>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_VCPU_CACHE_OFFSET0),
>>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_VCPU_CACHE_OFFSET1),
>>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_VCPU_CACHE_OFFSET2),
>>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CONTEXT_ID),
>>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_DATA0),
>>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_DATA1),
>>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_CMD),
>>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0,
>>>>>> regUVD_LMI_VCPU_NC1_64BIT_BAR_HIGH),
>>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, 
>>>>>> regUVD_LMI_VCPU_NC1_64BIT_BAR_LOW),
>>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0,
>>>>>> regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH),
>>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, 
>>>>>> regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW),
>>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, 
>>>>>> regUVD_LMI_VCPU_CACHE_VMIDS_MULTI),
>>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_NC_VMIDS_MULTI),
>>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI),
>>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO),
>>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI2),
>>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO2),
>>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI3),
>>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO3),
>>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI4),
>>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO4),
>>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR),
>>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR),
>>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR2),
>>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR2),
>>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR3),
>>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR3),
>>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR4),
>>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR4),
>>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE),
>>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE2),
>>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE3),
>>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_SOFT_RESET),
>>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_SOFT_RESET2),
>>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CGC_GATE),
>>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CGC_STATUS),
>>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CGC_CTRL),
>>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CGC_CTRL3),
>>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_SUVD_CGC_GATE),
>>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_SUVD_CGC_STATUS),
>>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_SUVD_CGC_CTRL),
>>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_SUVD_CGC_GATE2),
>>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE3),
>>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE4),
>>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE4),
>>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_SUVD_CGC_STATUS2),
>>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_SUVD_CGC_GATE2),
>>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_VCPU_CACHE_OFFSET2),
>>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0,
>>>>>> regUVD_LMI_MIF_GPGPU_64BIT_BAR_LOW),
>>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0,
>>>>>> regUVD_LMI_MIF_GPGPU_64BIT_BAR_HIGH),
>>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0,
>>>>>> regUVD_LMI_MIF_CURR_LUMA_64BIT_BAR_LOW),
>>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0,
>>>>>> regUVD_LMI_MIF_CURR_LUMA_64BIT_BAR_HIGH),
>>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0,
>>>>>> regUVD_LMI_MIF_CURR_CHROMA_64BIT_BAR_LOW),
>>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0,
>>>>>> regUVD_LMI_MIF_CURR_CHROMA_64BIT_BAR_HIGH),
>>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, 
>>>>>> regUVD_LMI_MIF_DBW_64BIT_BAR_LOW),
>>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, 
>>>>>> regUVD_LMI_MIF_DBW_64BIT_BAR_HIGH),
>>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0,
>>>>>> regUVD_LMI_MIF_CM_COLOC_64BIT_BAR_LOW),
>>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0,
>>>>>> regUVD_LMI_MIF_CM_COLOC_64BIT_BAR_HIGH),
>>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, 
>>>>>> regUVD_LMI_MIF_BSP0_64BIT_BAR_LOW),
>>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0,
>>>>>> regUVD_LMI_MIF_BSP0_64BIT_BAR_HIGH),
>>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, 
>>>>>> regUVD_LMI_MIF_BSP1_64BIT_BAR_LOW),
>>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0,
>>>>>> regUVD_LMI_MIF_BSP1_64BIT_BAR_HIGH),
>>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, 
>>>>>> regUVD_LMI_MIF_BSP2_64BIT_BAR_LOW),
>>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0,
>>>>>> regUVD_LMI_MIF_BSP2_64BIT_BAR_HIGH),
>>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, 
>>>>>> regUVD_LMI_MIF_BSP3_64BIT_BAR_LOW),
>>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0,
>>>>>> regUVD_LMI_MIF_BSP3_64BIT_BAR_HIGH),
>>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, 
>>>>>> regUVD_LMI_MIF_BSD0_64BIT_BAR_LOW),
>>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0,
>>>>>> regUVD_LMI_MIF_BSD0_64BIT_BAR_HIGH),
>>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, 
>>>>>> regUVD_LMI_MIF_BSD1_64BIT_BAR_LOW),
>>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0,
>>>>>> regUVD_LMI_MIF_BSD1_64BIT_BAR_HIGH),
>>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, 
>>>>>> regUVD_LMI_MIF_BSD2_64BIT_BAR_LOW),
>>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0,
>>>>>> regUVD_LMI_MIF_BSD2_64BIT_BAR_HIGH),
>>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, 
>>>>>> regUVD_LMI_MIF_BSD3_64BIT_BAR_LOW),
>>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0,
>>>>>> regUVD_LMI_MIF_BSD3_64BIT_BAR_HIGH),
>>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, 
>>>>>> regUVD_LMI_MIF_BSD4_64BIT_BAR_LOW),
>>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0,
>>>>>> regUVD_LMI_MIF_BSD4_64BIT_BAR_HIGH),
>>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0,
>>>>>> regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
>>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0,
>>>>>> regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
>>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0,
>>>>>> regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),
>>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0,
>>>>>> regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),
>>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0,
>>>>>> regUVD_LMI_VCPU_CACHE3_64BIT_BAR_LOW),
>>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0,
>>>>>> regUVD_LMI_VCPU_CACHE3_64BIT_BAR_HIGH),
>>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0,
>>>>>> regUVD_LMI_VCPU_CACHE4_64BIT_BAR_LOW),
>>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0,
>>>>>> regUVD_LMI_VCPU_CACHE4_64BIT_BAR_HIGH),
>>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0,
>>>>>> regUVD_LMI_VCPU_CACHE5_64BIT_BAR_LOW),
>>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0,
>>>>>> regUVD_LMI_VCPU_CACHE5_64BIT_BAR_HIGH),
>>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0,
>>>>>> regUVD_LMI_VCPU_CACHE6_64BIT_BAR_LOW),
>>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0,
>>>>>> regUVD_LMI_VCPU_CACHE6_64BIT_BAR_HIGH),
>>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0,
>>>>>> regUVD_LMI_VCPU_CACHE7_64BIT_BAR_LOW),
>>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0,
>>>>>> regUVD_LMI_VCPU_CACHE7_64BIT_BAR_HIGH),
>>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, 
>>>>>> regUVD_LMI_MIF_SCLR_64BIT_BAR_LOW),
>>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0,
>>>>>> regUVD_LMI_MIF_SCLR_64BIT_BAR_HIGH),
>>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0,
>>>>>> regUVD_LMI_MIF_SCLR2_64BIT_BAR_LOW),
>>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0,
>>>>>> regUVD_LMI_MIF_SCLR2_64BIT_BAR_HIGH),
>>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0,
>>>>>> regUVD_LMI_MIF_IMAGEPASTE_LUMA_64BIT_BAR_LOW),
>>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0,
>>>>>> regUVD_LMI_MIF_IMAGEPASTE_LUMA_64BIT_BAR_HIGH),
>>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0,
>>>>>> regUVD_LMI_MIF_IMAGEPASTE_CHROMA_64BIT_BAR_LOW),
>>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0,
>>>>>> regUVD_LMI_MIF_IMAGEPASTE_CHROMA_64BIT_BAR_HIGH),
>>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0,
>>>>>> regUVD_LMI_MIF_PRIVACY_LUMA_64BIT_BAR_LOW),
>>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0,
>>>>>> regUVD_LMI_MIF_PRIVACY_LUMA_64BIT_BAR_HIGH),
>>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0,
>>>>>> regUVD_LMI_MIF_PRIVACY_CHROMA_64BIT_BAR_LOW),
>>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0,
>>>>>> regUVD_LMI_MIF_PRIVACY_CHROMA_64BIT_BAR_HIGH),
>>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_STATUS),
>>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_CTL),
>>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_DATA),
>>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_MASK),
>>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_PAUSE),
>>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0,
>>>>>> regUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW),
>>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0,
>>>>>> regUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
>>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_VCPU_CACHE_OFFSET0),
>>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMI_VCPU_CACHE_VMID),
>>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_CLK_EN_VCPU_REPORT),
>>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_CTL),
>>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_CTL2),
>>>>>> +       SOC15_REG_ENTRY_STR(VCN, 0, regUVD_SCRATCH1)
>>>>>> +};
>>>>>> +
>>>>>>    #define NORMALIZE_VCN_REG_OFFSET(offset) \
>>>>>>                   (offset & 0x1FFFF)
>>>>>>
>>>>>> @@ -92,6 +218,8 @@ static int vcn_v4_0_3_sw_init(void *handle)
>>>>>>           struct amdgpu_device *adev = (struct amdgpu_device 
>>>>>> *)handle;
>>>>>>           struct amdgpu_ring *ring;
>>>>>>           int i, r, vcn_inst;
>>>>>> +       uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_4_0_3);
>>>>>> +       uint32_t *ptr;
>>>>>>
>>>>>>           r = amdgpu_vcn_sw_init(adev);
>>>>>>           if (r)
>>>>>> @@ -159,6 +287,15 @@ static int vcn_v4_0_3_sw_init(void *handle)
>>>>>>                   }
>>>>>>           }
>>>>>>
>>>>>> +       /* Allocate memory for VCN IP Dump buffer */
>>>>>> +       ptr = kcalloc(adev->vcn.num_vcn_inst * reg_count,
>>>>>> sizeof(uint32_t), GFP_KERNEL);
>>>>>> +       if (ptr == NULL) {
>>>>>> +               DRM_ERROR("Failed to allocate memory for VCN IP
>>>>>> Dump\n");
>>>>>> +               adev->vcn.ip_dump = NULL;
>>>>>> +       } else {
>>>>>> +               adev->vcn.ip_dump = ptr;
>>>>>> +       }
>>>>>> +
>>>>>>           return 0;
>>>>>>    }
>>>>>>
>>>>>> @@ -194,6 +331,8 @@ static int vcn_v4_0_3_sw_fini(void *handle)
>>>>>>
>>>>>>           r = amdgpu_vcn_sw_fini(adev);
>>>>>>
>>>>>> +       kfree(adev->vcn.ip_dump);
>>>>>> +
>>>>>>           return r;
>>>>>>    }
>>>>>>
>>>>>> @@ -1684,6 +1823,35 @@ static void vcn_v4_0_3_set_irq_funcs(struct
>>>>>> amdgpu_device *adev)
>>>>>>           adev->vcn.inst->irq.funcs = &vcn_v4_0_3_irq_funcs;
>>>>>>    }
>>>>>>
>>>>>> +static void vcn_v4_0_3_dump_ip_state(void *handle)
>>>>>> +{
>>>>>> +       struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>>>>>> +       int i, j;
>>>>>> +       bool is_powered;
>>>>>> +       uint32_t inst_off;
>>>>>> +       uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_4_0_3);
>>>>>> +
>>>>>> +       if (!adev->vcn.ip_dump)
>>>>>> +               return;
>>>>>> +
>>>>>> +       for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
>>>>>> +               if (adev->vcn.harvest_config & (1 << i))
>>>>>> +                       continue;
>>>>>> +
>>>>>> +               inst_off = i * reg_count;
>>>>>> +               /* mmUVD_POWER_STATUS is always readable and is
>>>>>> first element of the array */
>>>>>> +               adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, i,
>>>>>> regUVD_POWER_STATUS);
>>>>> I think you need to use the GET_INST() macro to properly handle
>>>>> this.  E.g.,
>>>>> vcn_inst = GET_INST(VCN, i);
>>>>>
>>>>> Alex
>>>>>
>>>>>> +               is_powered = (adev->vcn.ip_dump[inst_off] &
>>>>>> +
>>>>>> UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
>>>>>> +
>>>>>> +               if (is_powered)
>>>>>> +                       for (j = 1; j < reg_count; j++)
>>>>>> + adev->vcn.ip_dump[inst_off + j] =
>>>>>> +
>>>>>> RREG32(SOC15_REG_ENTRY_OFFSET_INST(
>>>>>> +
>>>>>> vcn_reg_list_4_0_3[j], i));
>>>> VCN 4.0.3 supports DPG. As far as I understand, most of these 
>>>> registers
>>>> are accessed indirectly in DPG mode through indirect SRAM.
>>>>
>>>> Checking UVD power status alone may not be sufficient for direct 
>>>> access.
>>> i am following what windows is following and most of the registers are
>>> directly access but i agree some might not be.
>> Whether Windows logic works is the first question other than the
>> secondary question of value in logging some of those registers.
> True. Cant say but the bare minimum we could do for a starting point 
> was the intent. Dumping VCN registers is a challenge due to its 
> dynamic power gating controlled by firmware.
> based on VCN fw guys probability is in case of VCN hung we might be in 
> power up state to read some of the status registers if not all.
>>
>>    We are assuming in case
>>> of a VCN hang it should be in good power state and we should be able to
>>> read most of the registers.
>> 'is_powered ' - It's quite obvious that there is no assumption like that
>> :). Secondly, when there are multiple instances where only one VCN
>> instance got hung, and others may not be - this assumption won't hold 
>> good.
>
> The principal is we are dumping all the IP's irrespective of who 
> caused the hang so no matter what instance causes hang the registers 
> are dumped for all. The vcn hang information is captured in the kernel 
> logs
>
> that can be used along with it. Also is_powered is per instance and if 
> its powered off we arent going to read the register at all.
>
> Based on the experiments i did in case of hang caused by gfx i found 
> vcn to be powered off as there isnt any work load on VCN to keep it 
> up. We will improvise on the functionality as we start seeing issues.
>
>> Thanks,
>> Lijo
>>
>>> Based on further feedback will do the
>>> needful but right now the point where we are dumping the registers we
>>> could not make any change in power state.
>>>
>>> Regards
>>> Sunil khatri
>>>
>>>> Thanks,
>>>> Lijo
>>>>
>>>>>> +       }
>>>>>> +}
>>>>>> +
>>>>>>    static const struct amd_ip_funcs vcn_v4_0_3_ip_funcs = {
>>>>>>           .name = "vcn_v4_0_3",
>>>>>>           .early_init = vcn_v4_0_3_early_init,
>>>>>> @@ -1702,7 +1870,7 @@ static const struct amd_ip_funcs
>>>>>> vcn_v4_0_3_ip_funcs = {
>>>>>>           .post_soft_reset = NULL,
>>>>>>           .set_clockgating_state = vcn_v4_0_3_set_clockgating_state,
>>>>>>           .set_powergating_state = vcn_v4_0_3_set_powergating_state,
>>>>>> -       .dump_ip_state = NULL,
>>>>>> +       .dump_ip_state = vcn_v4_0_3_dump_ip_state,
>>>>>>           .print_ip_state = NULL,
>>>>>>    };
>>>>>>
>>>>>> -- 
>>>>>> 2.34.1
>>>>>>

^ permalink raw reply	[flat|nested] 28+ messages in thread

* [PATCH v1 06/15] drm/amdgpu: add print support for vcn_v4_0_3 ip dump
  2024-08-06  8:18 [PATCH v1 00/15] VCN IP DUMP support for remaining IP's Sunil Khatri
                   ` (4 preceding siblings ...)
  2024-08-06  8:18 ` [PATCH v1 05/15] drm/amdgpu: add vcn_v4_0_3 ip dump support Sunil Khatri
@ 2024-08-06  8:18 ` Sunil Khatri
  2024-08-06 21:32   ` Alex Deucher
  2024-08-06  8:18 ` [PATCH v1 07/15] drm/amdgpu: add vcn_v4_0_5 ip dump support Sunil Khatri
                   ` (8 subsequent siblings)
  14 siblings, 1 reply; 28+ messages in thread
From: Sunil Khatri @ 2024-08-06  8:18 UTC (permalink / raw)
  To: Alex Deucher, Christian König; +Cc: amd-gfx, Sunil Khatri

Add support for logging the registers in devcoredump
buffer for vcn_v4_0_3.

Signed-off-by: Sunil Khatri <sunil.khatri@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c | 34 ++++++++++++++++++++++++-
 1 file changed, 33 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
index dd3baccb2904..033e5c88527c 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
@@ -1823,6 +1823,38 @@ static void vcn_v4_0_3_set_irq_funcs(struct amdgpu_device *adev)
 	adev->vcn.inst->irq.funcs = &vcn_v4_0_3_irq_funcs;
 }
 
+static void vcn_v4_0_3_print_ip_state(void *handle, struct drm_printer *p)
+{
+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+	int i, j;
+	uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_4_0_3);
+	uint32_t inst_off, is_powered;
+
+	if (!adev->vcn.ip_dump)
+		return;
+
+	drm_printf(p, "num_instances:%d\n", adev->vcn.num_vcn_inst);
+	for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
+		if (adev->vcn.harvest_config & (1 << i)) {
+			drm_printf(p, "\nHarvested Instance:VCN%d Skipping dump\n", i);
+			continue;
+		}
+
+		inst_off = i * reg_count;
+		is_powered = (adev->vcn.ip_dump[inst_off] &
+				UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
+
+		if (is_powered) {
+			drm_printf(p, "\nActive Instance:VCN%d\n", i);
+			for (j = 0; j < reg_count; j++)
+				drm_printf(p, "%-50s \t 0x%08x\n", vcn_reg_list_4_0_3[j].reg_name,
+					   adev->vcn.ip_dump[inst_off + j]);
+		} else {
+			drm_printf(p, "\nInactive Instance:VCN%d\n", i);
+		}
+	}
+}
+
 static void vcn_v4_0_3_dump_ip_state(void *handle)
 {
 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
@@ -1871,7 +1903,7 @@ static const struct amd_ip_funcs vcn_v4_0_3_ip_funcs = {
 	.set_clockgating_state = vcn_v4_0_3_set_clockgating_state,
 	.set_powergating_state = vcn_v4_0_3_set_powergating_state,
 	.dump_ip_state = vcn_v4_0_3_dump_ip_state,
-	.print_ip_state = NULL,
+	.print_ip_state = vcn_v4_0_3_print_ip_state,
 };
 
 const struct amdgpu_ip_block_version vcn_v4_0_3_ip_block = {
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 28+ messages in thread

* Re: [PATCH v1 06/15] drm/amdgpu: add print support for vcn_v4_0_3 ip dump
  2024-08-06  8:18 ` [PATCH v1 06/15] drm/amdgpu: add print support for vcn_v4_0_3 ip dump Sunil Khatri
@ 2024-08-06 21:32   ` Alex Deucher
  2024-08-07  3:37     ` Khatri, Sunil
  0 siblings, 1 reply; 28+ messages in thread
From: Alex Deucher @ 2024-08-06 21:32 UTC (permalink / raw)
  To: Sunil Khatri; +Cc: Alex Deucher, Christian König, amd-gfx

On Tue, Aug 6, 2024 at 4:18 AM Sunil Khatri <sunil.khatri@amd.com> wrote:
>
> Add support for logging the registers in devcoredump
> buffer for vcn_v4_0_3.
>
> Signed-off-by: Sunil Khatri <sunil.khatri@amd.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c | 34 ++++++++++++++++++++++++-
>  1 file changed, 33 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
> index dd3baccb2904..033e5c88527c 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
> @@ -1823,6 +1823,38 @@ static void vcn_v4_0_3_set_irq_funcs(struct amdgpu_device *adev)
>         adev->vcn.inst->irq.funcs = &vcn_v4_0_3_irq_funcs;
>  }
>
> +static void vcn_v4_0_3_print_ip_state(void *handle, struct drm_printer *p)
> +{
> +       struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> +       int i, j;
> +       uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_4_0_3);
> +       uint32_t inst_off, is_powered;
> +
> +       if (!adev->vcn.ip_dump)
> +               return;
> +
> +       drm_printf(p, "num_instances:%d\n", adev->vcn.num_vcn_inst);
> +       for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
> +               if (adev->vcn.harvest_config & (1 << i)) {
> +                       drm_printf(p, "\nHarvested Instance:VCN%d Skipping dump\n", i);
> +                       continue;
> +               }
> +
> +               inst_off = i * reg_count;
> +               is_powered = (adev->vcn.ip_dump[inst_off] &
> +                               UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;

Actually, we shouldn't be checking whether or not VCN is powered up
when we print the results.  We've already stored the registers so we
don't care if VCN is powered at this point or not.  VCN could be
powered down by the time we print this.  It would be better to just
store a flag to determine whether or not we logged the registers in
the first place, then use that to determine whether or not we print
anything.  Same comment for the other VCN print_ip_state callbacks.

Alex

> +
> +               if (is_powered) {
> +                       drm_printf(p, "\nActive Instance:VCN%d\n", i);
> +                       for (j = 0; j < reg_count; j++)
> +                               drm_printf(p, "%-50s \t 0x%08x\n", vcn_reg_list_4_0_3[j].reg_name,
> +                                          adev->vcn.ip_dump[inst_off + j]);
> +               } else {
> +                       drm_printf(p, "\nInactive Instance:VCN%d\n", i);
> +               }
> +       }
> +}
> +
>  static void vcn_v4_0_3_dump_ip_state(void *handle)
>  {
>         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> @@ -1871,7 +1903,7 @@ static const struct amd_ip_funcs vcn_v4_0_3_ip_funcs = {
>         .set_clockgating_state = vcn_v4_0_3_set_clockgating_state,
>         .set_powergating_state = vcn_v4_0_3_set_powergating_state,
>         .dump_ip_state = vcn_v4_0_3_dump_ip_state,
> -       .print_ip_state = NULL,
> +       .print_ip_state = vcn_v4_0_3_print_ip_state,
>  };
>
>  const struct amdgpu_ip_block_version vcn_v4_0_3_ip_block = {
> --
> 2.34.1
>

^ permalink raw reply	[flat|nested] 28+ messages in thread

* Re: [PATCH v1 06/15] drm/amdgpu: add print support for vcn_v4_0_3 ip dump
  2024-08-06 21:32   ` Alex Deucher
@ 2024-08-07  3:37     ` Khatri, Sunil
  2024-08-07  3:41       ` Alex Deucher
  0 siblings, 1 reply; 28+ messages in thread
From: Khatri, Sunil @ 2024-08-07  3:37 UTC (permalink / raw)
  To: Alex Deucher, Sunil Khatri; +Cc: Alex Deucher, Christian König, amd-gfx


On 8/7/2024 3:02 AM, Alex Deucher wrote:
> On Tue, Aug 6, 2024 at 4:18 AM Sunil Khatri <sunil.khatri@amd.com> wrote:
>> Add support for logging the registers in devcoredump
>> buffer for vcn_v4_0_3.
>>
>> Signed-off-by: Sunil Khatri <sunil.khatri@amd.com>
>> ---
>>   drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c | 34 ++++++++++++++++++++++++-
>>   1 file changed, 33 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
>> index dd3baccb2904..033e5c88527c 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
>> @@ -1823,6 +1823,38 @@ static void vcn_v4_0_3_set_irq_funcs(struct amdgpu_device *adev)
>>          adev->vcn.inst->irq.funcs = &vcn_v4_0_3_irq_funcs;
>>   }
>>
>> +static void vcn_v4_0_3_print_ip_state(void *handle, struct drm_printer *p)
>> +{
>> +       struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> +       int i, j;
>> +       uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_4_0_3);
>> +       uint32_t inst_off, is_powered;
>> +
>> +       if (!adev->vcn.ip_dump)
>> +               return;
>> +
>> +       drm_printf(p, "num_instances:%d\n", adev->vcn.num_vcn_inst);
>> +       for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
>> +               if (adev->vcn.harvest_config & (1 << i)) {
>> +                       drm_printf(p, "\nHarvested Instance:VCN%d Skipping dump\n", i);
>> +                       continue;
>> +               }
>> +
>> +               inst_off = i * reg_count;
>> +               is_powered = (adev->vcn.ip_dump[inst_off] &
>> +                               UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
> Actually, we shouldn't be checking whether or not VCN is powered up
> when we print the results.  We've already stored the registers so we
> don't care if VCN is powered at this point or not.  VCN could be
> powered down by the time we print this.  It would be better to just
> store a flag to determine whether or not we logged the registers in
> the first place, then use that to determine whether or not we print
> anything.  Same comment for the other VCN print_ip_state callbacks.
This is exactly the same being done here.

is_powered = (adev->vcn.ip_dump[inst_off] &
+                               UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
The above is already stored at the time of capturing the dump, i am just checking the value to make sure if it was
powered up at the time of dump and if yes then add logs to devcore dump else skip. Its done this way rather than using a variable as there could
be multiple instances of VCN and one may be powered or not so power state is captured for each instance and based on that value only its we are printing or logging in devcoredump.

Regards
Sunil khatri

>
> Alex
>
>> +
>> +               if (is_powered) {
>> +                       drm_printf(p, "\nActive Instance:VCN%d\n", i);
>> +                       for (j = 0; j < reg_count; j++)
>> +                               drm_printf(p, "%-50s \t 0x%08x\n", vcn_reg_list_4_0_3[j].reg_name,
>> +                                          adev->vcn.ip_dump[inst_off + j]);
>> +               } else {
>> +                       drm_printf(p, "\nInactive Instance:VCN%d\n", i);
>> +               }
>> +       }
>> +}
>> +
>>   static void vcn_v4_0_3_dump_ip_state(void *handle)
>>   {
>>          struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>> @@ -1871,7 +1903,7 @@ static const struct amd_ip_funcs vcn_v4_0_3_ip_funcs = {
>>          .set_clockgating_state = vcn_v4_0_3_set_clockgating_state,
>>          .set_powergating_state = vcn_v4_0_3_set_powergating_state,
>>          .dump_ip_state = vcn_v4_0_3_dump_ip_state,
>> -       .print_ip_state = NULL,
>> +       .print_ip_state = vcn_v4_0_3_print_ip_state,
>>   };
>>
>>   const struct amdgpu_ip_block_version vcn_v4_0_3_ip_block = {
>> --
>> 2.34.1
>>

^ permalink raw reply	[flat|nested] 28+ messages in thread

* Re: [PATCH v1 06/15] drm/amdgpu: add print support for vcn_v4_0_3 ip dump
  2024-08-07  3:37     ` Khatri, Sunil
@ 2024-08-07  3:41       ` Alex Deucher
  0 siblings, 0 replies; 28+ messages in thread
From: Alex Deucher @ 2024-08-07  3:41 UTC (permalink / raw)
  To: Khatri, Sunil; +Cc: Sunil Khatri, Alex Deucher, Christian König, amd-gfx

On Tue, Aug 6, 2024 at 11:37 PM Khatri, Sunil <sukhatri@amd.com> wrote:
>
>
> On 8/7/2024 3:02 AM, Alex Deucher wrote:
> > On Tue, Aug 6, 2024 at 4:18 AM Sunil Khatri <sunil.khatri@amd.com> wrote:
> >> Add support for logging the registers in devcoredump
> >> buffer for vcn_v4_0_3.
> >>
> >> Signed-off-by: Sunil Khatri <sunil.khatri@amd.com>
> >> ---
> >>   drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c | 34 ++++++++++++++++++++++++-
> >>   1 file changed, 33 insertions(+), 1 deletion(-)
> >>
> >> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
> >> index dd3baccb2904..033e5c88527c 100644
> >> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
> >> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
> >> @@ -1823,6 +1823,38 @@ static void vcn_v4_0_3_set_irq_funcs(struct amdgpu_device *adev)
> >>          adev->vcn.inst->irq.funcs = &vcn_v4_0_3_irq_funcs;
> >>   }
> >>
> >> +static void vcn_v4_0_3_print_ip_state(void *handle, struct drm_printer *p)
> >> +{
> >> +       struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> >> +       int i, j;
> >> +       uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_4_0_3);
> >> +       uint32_t inst_off, is_powered;
> >> +
> >> +       if (!adev->vcn.ip_dump)
> >> +               return;
> >> +
> >> +       drm_printf(p, "num_instances:%d\n", adev->vcn.num_vcn_inst);
> >> +       for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
> >> +               if (adev->vcn.harvest_config & (1 << i)) {
> >> +                       drm_printf(p, "\nHarvested Instance:VCN%d Skipping dump\n", i);
> >> +                       continue;
> >> +               }
> >> +
> >> +               inst_off = i * reg_count;
> >> +               is_powered = (adev->vcn.ip_dump[inst_off] &
> >> +                               UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
> > Actually, we shouldn't be checking whether or not VCN is powered up
> > when we print the results.  We've already stored the registers so we
> > don't care if VCN is powered at this point or not.  VCN could be
> > powered down by the time we print this.  It would be better to just
> > store a flag to determine whether or not we logged the registers in
> > the first place, then use that to determine whether or not we print
> > anything.  Same comment for the other VCN print_ip_state callbacks.
> This is exactly the same being done here.
>
> is_powered = (adev->vcn.ip_dump[inst_off] &
> +                               UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
> The above is already stored at the time of capturing the dump, i am just checking the value to make sure if it was
> powered up at the time of dump and if yes then add logs to devcore dump else skip. Its done this way rather than using a variable as there could
> be multiple instances of VCN and one may be powered or not so power state is captured for each instance and based on that value only its we are printing or logging in devcoredump.

Ah, yes, you are right.  My brain misread that.

Alex

>
> Regards
> Sunil khatri
>
> >
> > Alex
> >
> >> +
> >> +               if (is_powered) {
> >> +                       drm_printf(p, "\nActive Instance:VCN%d\n", i);
> >> +                       for (j = 0; j < reg_count; j++)
> >> +                               drm_printf(p, "%-50s \t 0x%08x\n", vcn_reg_list_4_0_3[j].reg_name,
> >> +                                          adev->vcn.ip_dump[inst_off + j]);
> >> +               } else {
> >> +                       drm_printf(p, "\nInactive Instance:VCN%d\n", i);
> >> +               }
> >> +       }
> >> +}
> >> +
> >>   static void vcn_v4_0_3_dump_ip_state(void *handle)
> >>   {
> >>          struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> >> @@ -1871,7 +1903,7 @@ static const struct amd_ip_funcs vcn_v4_0_3_ip_funcs = {
> >>          .set_clockgating_state = vcn_v4_0_3_set_clockgating_state,
> >>          .set_powergating_state = vcn_v4_0_3_set_powergating_state,
> >>          .dump_ip_state = vcn_v4_0_3_dump_ip_state,
> >> -       .print_ip_state = NULL,
> >> +       .print_ip_state = vcn_v4_0_3_print_ip_state,
> >>   };
> >>
> >>   const struct amdgpu_ip_block_version vcn_v4_0_3_ip_block = {
> >> --
> >> 2.34.1
> >>

^ permalink raw reply	[flat|nested] 28+ messages in thread

* [PATCH v1 07/15] drm/amdgpu: add vcn_v4_0_5 ip dump support
  2024-08-06  8:18 [PATCH v1 00/15] VCN IP DUMP support for remaining IP's Sunil Khatri
                   ` (5 preceding siblings ...)
  2024-08-06  8:18 ` [PATCH v1 06/15] drm/amdgpu: add print support for vcn_v4_0_3 ip dump Sunil Khatri
@ 2024-08-06  8:18 ` Sunil Khatri
  2024-08-06  8:18 ` [PATCH v1 08/15] drm/amdgpu: add print support for vcn_v4_0_5 ip dump Sunil Khatri
                   ` (7 subsequent siblings)
  14 siblings, 0 replies; 28+ messages in thread
From: Sunil Khatri @ 2024-08-06  8:18 UTC (permalink / raw)
  To: Alex Deucher, Christian König; +Cc: amd-gfx, Sunil Khatri

Add support of vcn ip dump in the devcoredump
for vcn_v4_0_5.

Signed-off-by: Sunil Khatri <sunil.khatri@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c | 169 +++++++++++++++++++++++-
 1 file changed, 168 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
index 8d75061f9f38..27b2f66117e0 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
@@ -52,6 +52,132 @@
 #define RDECODE_MSG_CREATE							0x00000000
 #define RDECODE_MESSAGE_CREATE						0x00000001
 
+static const struct amdgpu_hwip_reg_entry vcn_reg_list_4_0_5[] = {
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_POWER_STATUS),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_STATUS),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_VCPU_CACHE_OFFSET0),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_VCPU_CACHE_OFFSET1),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_VCPU_CACHE_OFFSET2),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CONTEXT_ID),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_DATA0),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_DATA1),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_CMD),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_NC1_64BIT_BAR_HIGH),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_NC1_64BIT_BAR_LOW),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_NC0_64BIT_BAR_LOW),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE_VMIDS_MULTI),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_NC_VMIDS_MULTI),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI2),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO2),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI3),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO3),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI4),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO4),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR2),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR2),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR3),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR3),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR4),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR4),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE2),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE3),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_SOFT_RESET),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_SOFT_RESET2),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CGC_GATE),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CGC_STATUS),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CGC_CTRL),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CGC_CTRL3),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_SUVD_CGC_GATE),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_SUVD_CGC_STATUS),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_SUVD_CGC_CTRL),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_SUVD_CGC_GATE2),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE3),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE4),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE4),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_SUVD_CGC_STATUS2),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_SUVD_CGC_GATE2),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_VCPU_CACHE_OFFSET2),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_GPGPU_64BIT_BAR_LOW),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_GPGPU_64BIT_BAR_HIGH),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_CURR_LUMA_64BIT_BAR_LOW),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_CURR_LUMA_64BIT_BAR_HIGH),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_CURR_CHROMA_64BIT_BAR_LOW),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_CURR_CHROMA_64BIT_BAR_HIGH),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_DBW_64BIT_BAR_LOW),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_DBW_64BIT_BAR_HIGH),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_CM_COLOC_64BIT_BAR_LOW),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_CM_COLOC_64BIT_BAR_HIGH),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSP0_64BIT_BAR_LOW),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSP0_64BIT_BAR_HIGH),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSP1_64BIT_BAR_LOW),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSP1_64BIT_BAR_HIGH),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSP2_64BIT_BAR_LOW),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSP2_64BIT_BAR_HIGH),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSP3_64BIT_BAR_LOW),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSP3_64BIT_BAR_HIGH),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSD0_64BIT_BAR_LOW),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSD0_64BIT_BAR_HIGH),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSD1_64BIT_BAR_LOW),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSD1_64BIT_BAR_HIGH),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSD2_64BIT_BAR_LOW),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSD2_64BIT_BAR_HIGH),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSD3_64BIT_BAR_LOW),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSD3_64BIT_BAR_HIGH),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSD4_64BIT_BAR_LOW),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_BSD4_64BIT_BAR_HIGH),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE3_64BIT_BAR_LOW),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE3_64BIT_BAR_HIGH),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE4_64BIT_BAR_LOW),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE4_64BIT_BAR_HIGH),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE5_64BIT_BAR_LOW),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE5_64BIT_BAR_HIGH),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE6_64BIT_BAR_LOW),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE6_64BIT_BAR_HIGH),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE7_64BIT_BAR_LOW),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_VCPU_CACHE7_64BIT_BAR_HIGH),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_SCLR_64BIT_BAR_LOW),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_SCLR_64BIT_BAR_HIGH),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_SCLR2_64BIT_BAR_LOW),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_SCLR2_64BIT_BAR_HIGH),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_IMAGEPASTE_LUMA_64BIT_BAR_LOW),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_IMAGEPASTE_LUMA_64BIT_BAR_HIGH),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_IMAGEPASTE_CHROMA_64BIT_BAR_LOW),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_IMAGEPASTE_CHROMA_64BIT_BAR_HIGH),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_PRIVACY_LUMA_64BIT_BAR_LOW),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_PRIVACY_LUMA_64BIT_BAR_HIGH),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_PRIVACY_CHROMA_64BIT_BAR_LOW),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_MIF_PRIVACY_CHROMA_64BIT_BAR_HIGH),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_LMI_STATUS),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_CTL),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_DATA),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_MASK),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_PAUSE),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_VCPU_CACHE_OFFSET0),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMI_VCPU_CACHE_VMID),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_CLK_EN_VCPU_REPORT),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_CTL),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_CTL2),
+	SOC15_REG_ENTRY_STR(VCN, 0, regUVD_SCRATCH1)
+};
+
 static int amdgpu_ih_clientid_vcns[] = {
 	SOC15_IH_CLIENTID_VCN,
 	SOC15_IH_CLIENTID_VCN1
@@ -97,6 +223,8 @@ static int vcn_v4_0_5_sw_init(void *handle)
 	struct amdgpu_ring *ring;
 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 	int i, r;
+	uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_4_0_5);
+	uint32_t *ptr;
 
 	r = amdgpu_vcn_sw_init(adev);
 	if (r)
@@ -168,6 +296,14 @@ static int vcn_v4_0_5_sw_init(void *handle)
 	if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)
 		adev->vcn.pause_dpg_mode = vcn_v4_0_5_pause_dpg_mode;
 
+	/* Allocate memory for VCN IP Dump buffer */
+	ptr = kcalloc(adev->vcn.num_vcn_inst * reg_count, sizeof(uint32_t), GFP_KERNEL);
+	if (ptr == NULL) {
+		DRM_ERROR("Failed to allocate memory for VCN IP Dump\n");
+		adev->vcn.ip_dump = NULL;
+	} else {
+		adev->vcn.ip_dump = ptr;
+	}
 	return 0;
 }
 
@@ -207,6 +343,8 @@ static int vcn_v4_0_5_sw_fini(void *handle)
 
 	r = amdgpu_vcn_sw_fini(adev);
 
+	kfree(adev->vcn.ip_dump);
+
 	return r;
 }
 
@@ -1733,6 +1871,35 @@ static void vcn_v4_0_5_set_irq_funcs(struct amdgpu_device *adev)
 	}
 }
 
+static void vcn_v4_0_5_dump_ip_state(void *handle)
+{
+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+	int i, j;
+	bool is_powered;
+	uint32_t inst_off;
+	uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_4_0_5);
+
+	if (!adev->vcn.ip_dump)
+		return;
+
+	for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
+		if (adev->vcn.harvest_config & (1 << i))
+			continue;
+
+		inst_off = i * reg_count;
+		/* mmUVD_POWER_STATUS is always readable and is first element of the array */
+		adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, i, regUVD_POWER_STATUS);
+		is_powered = (adev->vcn.ip_dump[inst_off] &
+				UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
+
+		if (is_powered)
+			for (j = 1; j < reg_count; j++)
+				adev->vcn.ip_dump[inst_off + j] =
+					RREG32(SOC15_REG_ENTRY_OFFSET_INST(
+						vcn_reg_list_4_0_5[j], i));
+	}
+}
+
 static const struct amd_ip_funcs vcn_v4_0_5_ip_funcs = {
 	.name = "vcn_v4_0_5",
 	.early_init = vcn_v4_0_5_early_init,
@@ -1751,7 +1918,7 @@ static const struct amd_ip_funcs vcn_v4_0_5_ip_funcs = {
 	.post_soft_reset = NULL,
 	.set_clockgating_state = vcn_v4_0_5_set_clockgating_state,
 	.set_powergating_state = vcn_v4_0_5_set_powergating_state,
-	.dump_ip_state = NULL,
+	.dump_ip_state = vcn_v4_0_5_dump_ip_state,
 	.print_ip_state = NULL,
 };
 
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 28+ messages in thread

* [PATCH v1 08/15] drm/amdgpu: add print support for vcn_v4_0_5 ip dump
  2024-08-06  8:18 [PATCH v1 00/15] VCN IP DUMP support for remaining IP's Sunil Khatri
                   ` (6 preceding siblings ...)
  2024-08-06  8:18 ` [PATCH v1 07/15] drm/amdgpu: add vcn_v4_0_5 ip dump support Sunil Khatri
@ 2024-08-06  8:18 ` Sunil Khatri
  2024-08-06  8:18 ` [PATCH v1 09/15] drm/amdgpu: add vcn_v1_0 ip dump support Sunil Khatri
                   ` (6 subsequent siblings)
  14 siblings, 0 replies; 28+ messages in thread
From: Sunil Khatri @ 2024-08-06  8:18 UTC (permalink / raw)
  To: Alex Deucher, Christian König; +Cc: amd-gfx, Sunil Khatri

Add support for logging the registers in devcoredump
buffer for vcn_v4_0_5.

Signed-off-by: Sunil Khatri <sunil.khatri@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c | 34 ++++++++++++++++++++++++-
 1 file changed, 33 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
index 27b2f66117e0..f192870d9e5c 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
@@ -1871,6 +1871,38 @@ static void vcn_v4_0_5_set_irq_funcs(struct amdgpu_device *adev)
 	}
 }
 
+static void vcn_v4_0_5_print_ip_state(void *handle, struct drm_printer *p)
+{
+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+	int i, j;
+	uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_4_0_5);
+	uint32_t inst_off, is_powered;
+
+	if (!adev->vcn.ip_dump)
+		return;
+
+	drm_printf(p, "num_instances:%d\n", adev->vcn.num_vcn_inst);
+	for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
+		if (adev->vcn.harvest_config & (1 << i)) {
+			drm_printf(p, "\nHarvested Instance:VCN%d Skipping dump\n", i);
+			continue;
+		}
+
+		inst_off = i * reg_count;
+		is_powered = (adev->vcn.ip_dump[inst_off] &
+				UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
+
+		if (is_powered) {
+			drm_printf(p, "\nActive Instance:VCN%d\n", i);
+			for (j = 0; j < reg_count; j++)
+				drm_printf(p, "%-50s \t 0x%08x\n", vcn_reg_list_4_0_5[j].reg_name,
+					   adev->vcn.ip_dump[inst_off + j]);
+		} else {
+			drm_printf(p, "\nInactive Instance:VCN%d\n", i);
+		}
+	}
+}
+
 static void vcn_v4_0_5_dump_ip_state(void *handle)
 {
 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
@@ -1919,7 +1951,7 @@ static const struct amd_ip_funcs vcn_v4_0_5_ip_funcs = {
 	.set_clockgating_state = vcn_v4_0_5_set_clockgating_state,
 	.set_powergating_state = vcn_v4_0_5_set_powergating_state,
 	.dump_ip_state = vcn_v4_0_5_dump_ip_state,
-	.print_ip_state = NULL,
+	.print_ip_state = vcn_v4_0_5_print_ip_state,
 };
 
 const struct amdgpu_ip_block_version vcn_v4_0_5_ip_block = {
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 28+ messages in thread

* [PATCH v1 09/15] drm/amdgpu: add vcn_v1_0 ip dump support
  2024-08-06  8:18 [PATCH v1 00/15] VCN IP DUMP support for remaining IP's Sunil Khatri
                   ` (7 preceding siblings ...)
  2024-08-06  8:18 ` [PATCH v1 08/15] drm/amdgpu: add print support for vcn_v4_0_5 ip dump Sunil Khatri
@ 2024-08-06  8:18 ` Sunil Khatri
  2024-08-06  8:18 ` [PATCH v1 10/15] drm/amdgpu: add print support for vcn_v1_0 ip dump Sunil Khatri
                   ` (5 subsequent siblings)
  14 siblings, 0 replies; 28+ messages in thread
From: Sunil Khatri @ 2024-08-06  8:18 UTC (permalink / raw)
  To: Alex Deucher, Christian König; +Cc: amd-gfx, Sunil Khatri

Add support of vcn ip dump in the devcoredump
for vcn_v1_0.

Signed-off-by: Sunil Khatri <sunil.khatri@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 95 ++++++++++++++++++++++++++-
 1 file changed, 94 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
index a280b9fecb77..ceaf4b3847a5 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
@@ -45,6 +45,59 @@
 #define mmUVD_REG_XX_MASK_1_0			0x05ac
 #define mmUVD_REG_XX_MASK_1_0_BASE_IDX		1
 
+static const struct amdgpu_hwip_reg_entry vcn_reg_list_1_0[] = {
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_POWER_STATUS),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RBC_RB_RPTR),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RBC_RB_WPTR),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_STATUS),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_CONTEXT_ID),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_GPCOM_VCPU_DATA0),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_GPCOM_VCPU_DATA1),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_GPCOM_VCPU_CMD),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_LMI_RBC_IB_VMID),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_HI),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_LO),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_HI2),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_LO2),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_HI3),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_LO3),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_RPTR),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_RPTR2),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR2),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_RPTR3),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR3),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_SIZE),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_SIZE2),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_SIZE3),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_PGFSM_CONFIG),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_PGFSM_STATUS),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_SOFT_RESET),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_CGC_GATE),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_CGC_STATUS),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_CGC_CTRL),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_SUVD_CGC_GATE),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_SUVD_CGC_STATUS),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_SUVD_CGC_CTRL),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_LO4),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_HI4),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_SIZE4),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_RPTR4),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR4),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_VCPU_CACHE_OFFSET2),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_DPG_VCPU_CACHE_OFFSET0),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_LMI_STATUS),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_SCRATCH1)
+};
+
 static int vcn_v1_0_stop(struct amdgpu_device *adev);
 static void vcn_v1_0_set_dec_ring_funcs(struct amdgpu_device *adev);
 static void vcn_v1_0_set_enc_ring_funcs(struct amdgpu_device *adev);
@@ -90,6 +143,8 @@ static int vcn_v1_0_sw_init(void *handle)
 {
 	struct amdgpu_ring *ring;
 	int i, r;
+	uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_1_0);
+	uint32_t *ptr;
 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
 	/* VCN DEC TRAP */
@@ -161,6 +216,14 @@ static int vcn_v1_0_sw_init(void *handle)
 
 	r = jpeg_v1_0_sw_init(handle);
 
+	/* Allocate memory for VCN IP Dump buffer */
+	ptr = kcalloc(adev->vcn.num_vcn_inst * reg_count, sizeof(uint32_t), GFP_KERNEL);
+	if (ptr == NULL) {
+		DRM_ERROR("Failed to allocate memory for VCN IP Dump\n");
+		adev->vcn.ip_dump = NULL;
+	} else {
+		adev->vcn.ip_dump = ptr;
+	}
 	return r;
 }
 
@@ -184,6 +247,8 @@ static int vcn_v1_0_sw_fini(void *handle)
 
 	r = amdgpu_vcn_sw_fini(adev);
 
+	kfree(adev->vcn.ip_dump);
+
 	return r;
 }
 
@@ -1877,6 +1942,34 @@ void vcn_v1_0_ring_end_use(struct amdgpu_ring *ring)
 	mutex_unlock(&ring->adev->vcn.vcn1_jpeg1_workaround);
 }
 
+static void vcn_v1_0_dump_ip_state(void *handle)
+{
+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+	int i, j;
+	bool is_powered;
+	uint32_t inst_off;
+	uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_1_0);
+
+	if (!adev->vcn.ip_dump)
+		return;
+
+	for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
+		if (adev->vcn.harvest_config & (1 << i))
+			continue;
+
+		inst_off = i * reg_count;
+		/* mmUVD_POWER_STATUS is always readable and is first element of the array */
+		adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, i, mmUVD_POWER_STATUS);
+		is_powered = (adev->vcn.ip_dump[inst_off] &
+				UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
+
+		if (is_powered)
+			for (j = 1; j < reg_count; j++)
+				adev->vcn.ip_dump[inst_off + j] =
+					RREG32(SOC15_REG_ENTRY_OFFSET_INST(vcn_reg_list_1_0[j], i));
+	}
+}
+
 static const struct amd_ip_funcs vcn_v1_0_ip_funcs = {
 	.name = "vcn_v1_0",
 	.early_init = vcn_v1_0_early_init,
@@ -1895,7 +1988,7 @@ static const struct amd_ip_funcs vcn_v1_0_ip_funcs = {
 	.post_soft_reset = NULL /* vcn_v1_0_post_soft_reset */,
 	.set_clockgating_state = vcn_v1_0_set_clockgating_state,
 	.set_powergating_state = vcn_v1_0_set_powergating_state,
-	.dump_ip_state = NULL,
+	.dump_ip_state = vcn_v1_0_dump_ip_state,
 	.print_ip_state = NULL,
 };
 
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 28+ messages in thread

* [PATCH v1 10/15] drm/amdgpu: add print support for vcn_v1_0 ip dump
  2024-08-06  8:18 [PATCH v1 00/15] VCN IP DUMP support for remaining IP's Sunil Khatri
                   ` (8 preceding siblings ...)
  2024-08-06  8:18 ` [PATCH v1 09/15] drm/amdgpu: add vcn_v1_0 ip dump support Sunil Khatri
@ 2024-08-06  8:18 ` Sunil Khatri
  2024-08-06  8:18 ` [PATCH v1 11/15] drm/amdgpu: add vcn_v2_0 ip dump support Sunil Khatri
                   ` (4 subsequent siblings)
  14 siblings, 0 replies; 28+ messages in thread
From: Sunil Khatri @ 2024-08-06  8:18 UTC (permalink / raw)
  To: Alex Deucher, Christian König; +Cc: amd-gfx, Sunil Khatri

Add support for logging the registers in devcoredump
buffer for vcn_v1_0.

Signed-off-by: Sunil Khatri <sunil.khatri@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 34 ++++++++++++++++++++++++++-
 1 file changed, 33 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
index ceaf4b3847a5..ac9c0281762d 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
@@ -1942,6 +1942,38 @@ void vcn_v1_0_ring_end_use(struct amdgpu_ring *ring)
 	mutex_unlock(&ring->adev->vcn.vcn1_jpeg1_workaround);
 }
 
+static void vcn_v1_0_print_ip_state(void *handle, struct drm_printer *p)
+{
+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+	int i, j;
+	uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_1_0);
+	uint32_t inst_off, is_powered;
+
+	if (!adev->vcn.ip_dump)
+		return;
+
+	drm_printf(p, "num_instances:%d\n", adev->vcn.num_vcn_inst);
+	for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
+		if (adev->vcn.harvest_config & (1 << i)) {
+			drm_printf(p, "\nHarvested Instance:VCN%d Skipping dump\n", i);
+			continue;
+		}
+
+		inst_off = i * reg_count;
+		is_powered = (adev->vcn.ip_dump[inst_off] &
+				UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
+
+		if (is_powered) {
+			drm_printf(p, "\nActive Instance:VCN%d\n", i);
+			for (j = 0; j < reg_count; j++)
+				drm_printf(p, "%-50s \t 0x%08x\n", vcn_reg_list_1_0[j].reg_name,
+					   adev->vcn.ip_dump[inst_off + j]);
+		} else {
+			drm_printf(p, "\nInactive Instance:VCN%d\n", i);
+		}
+	}
+}
+
 static void vcn_v1_0_dump_ip_state(void *handle)
 {
 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
@@ -1989,7 +2021,7 @@ static const struct amd_ip_funcs vcn_v1_0_ip_funcs = {
 	.set_clockgating_state = vcn_v1_0_set_clockgating_state,
 	.set_powergating_state = vcn_v1_0_set_powergating_state,
 	.dump_ip_state = vcn_v1_0_dump_ip_state,
-	.print_ip_state = NULL,
+	.print_ip_state = vcn_v1_0_print_ip_state,
 };
 
 /*
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 28+ messages in thread

* [PATCH v1 11/15] drm/amdgpu: add vcn_v2_0 ip dump support
  2024-08-06  8:18 [PATCH v1 00/15] VCN IP DUMP support for remaining IP's Sunil Khatri
                   ` (9 preceding siblings ...)
  2024-08-06  8:18 ` [PATCH v1 10/15] drm/amdgpu: add print support for vcn_v1_0 ip dump Sunil Khatri
@ 2024-08-06  8:18 ` Sunil Khatri
  2024-08-06  8:18 ` [PATCH v1 12/15] drm/amdgpu: add print support for vcn_v2_0 ip dump Sunil Khatri
                   ` (3 subsequent siblings)
  14 siblings, 0 replies; 28+ messages in thread
From: Sunil Khatri @ 2024-08-06  8:18 UTC (permalink / raw)
  To: Alex Deucher, Christian König; +Cc: amd-gfx, Sunil Khatri

Add support of vcn ip dump in the devcoredump
for vcn_v2_0.

Signed-off-by: Sunil Khatri <sunil.khatri@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 111 +++++++++++++++++++++++++-
 1 file changed, 110 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
index d3d096909a7f..062651f87aa7 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
@@ -53,6 +53,74 @@
 #define mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET		0x5a7
 #define mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET			0x1e2
 
+static const struct amdgpu_hwip_reg_entry vcn_reg_list_2_0[] = {
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_POWER_STATUS),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RBC_RB_RPTR),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RBC_RB_WPTR),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_STATUS),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_CONTEXT_ID),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_GPCOM_VCPU_DATA0),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_GPCOM_VCPU_DATA1),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_GPCOM_VCPU_CMD),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_LMI_VCPU_NC1_64BIT_BAR_HIGH),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_LMI_VCPU_NC1_64BIT_BAR_LOW),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_LMI_RBC_IB_VMID),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_LMI_VCPU_CACHE_VMIDS_MULTI),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_LMI_VCPU_NC_VMIDS_MULTI),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_HI),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_LO),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_HI2),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_LO2),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_HI3),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_LO3),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_RPTR),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_RPTR2),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR2),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_RPTR3),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR3),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_SIZE),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_SIZE2),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_SIZE3),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_PGFSM_CONFIG),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_PGFSM_STATUS),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_SOFT_RESET),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_SOFT_RESET2),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_CGC_GATE),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_CGC_STATUS),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_CGC_CTRL),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_SUVD_CGC_GATE),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_SUVD_CGC_STATUS),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_SUVD_CGC_CTRL),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_LO4),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_HI4),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_SIZE4),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_RPTR4),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR4),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_VCPU_CACHE_OFFSET2),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_LMI_VCPU_CACHE3_64BIT_BAR_LOW),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_LMI_VCPU_CACHE3_64BIT_BAR_HIGH),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_LMI_VCPU_CACHE4_64BIT_BAR_LOW),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_LMI_VCPU_CACHE4_64BIT_BAR_HIGH),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_LMI_VCPU_CACHE5_64BIT_BAR_LOW),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_LMI_VCPU_CACHE5_64BIT_BAR_HIGH),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_LMI_VCPU_CACHE6_64BIT_BAR_LOW),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_LMI_VCPU_CACHE6_64BIT_BAR_HIGH),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_LMI_VCPU_CACHE7_64BIT_BAR_LOW),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_LMI_VCPU_CACHE7_64BIT_BAR_HIGH),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_LMI_STATUS),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_SCRATCH1)
+};
+
+
 static void vcn_v2_0_set_dec_ring_funcs(struct amdgpu_device *adev);
 static void vcn_v2_0_set_enc_ring_funcs(struct amdgpu_device *adev);
 static void vcn_v2_0_set_irq_funcs(struct amdgpu_device *adev);
@@ -96,6 +164,8 @@ static int vcn_v2_0_sw_init(void *handle)
 {
 	struct amdgpu_ring *ring;
 	int i, r;
+	uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_2_0);
+	uint32_t *ptr;
 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 	volatile struct amdgpu_fw_shared *fw_shared;
 
@@ -184,6 +254,15 @@ static int vcn_v2_0_sw_init(void *handle)
 	if (amdgpu_vcnfw_log)
 		amdgpu_vcn_fwlog_init(adev->vcn.inst);
 
+	/* Allocate memory for VCN IP Dump buffer */
+	ptr = kcalloc(adev->vcn.num_vcn_inst * reg_count, sizeof(uint32_t), GFP_KERNEL);
+	if (ptr == NULL) {
+		DRM_ERROR("Failed to allocate memory for VCN IP Dump\n");
+		adev->vcn.ip_dump = NULL;
+	} else {
+		adev->vcn.ip_dump = ptr;
+	}
+
 	return 0;
 }
 
@@ -213,6 +292,8 @@ static int vcn_v2_0_sw_fini(void *handle)
 
 	r = amdgpu_vcn_sw_fini(adev);
 
+	kfree(adev->vcn.ip_dump);
+
 	return r;
 }
 
@@ -1985,6 +2066,34 @@ static int vcn_v2_0_start_sriov(struct amdgpu_device *adev)
 	return vcn_v2_0_start_mmsch(adev, &adev->virt.mm_table);
 }
 
+static void vcn_v2_0_dump_ip_state(void *handle)
+{
+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+	int i, j;
+	bool is_powered;
+	uint32_t inst_off;
+	uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_2_0);
+
+	if (!adev->vcn.ip_dump)
+		return;
+
+	for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
+		if (adev->vcn.harvest_config & (1 << i))
+			continue;
+
+		inst_off = i * reg_count;
+		/* mmUVD_POWER_STATUS is always readable and is first element of the array */
+		adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, i, mmUVD_POWER_STATUS);
+		is_powered = (adev->vcn.ip_dump[inst_off] &
+				UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
+
+		if (is_powered)
+			for (j = 1; j < reg_count; j++)
+				adev->vcn.ip_dump[inst_off + j] =
+					RREG32(SOC15_REG_ENTRY_OFFSET_INST(vcn_reg_list_2_0[j], i));
+	}
+}
+
 static const struct amd_ip_funcs vcn_v2_0_ip_funcs = {
 	.name = "vcn_v2_0",
 	.early_init = vcn_v2_0_early_init,
@@ -2003,7 +2112,7 @@ static const struct amd_ip_funcs vcn_v2_0_ip_funcs = {
 	.post_soft_reset = NULL,
 	.set_clockgating_state = vcn_v2_0_set_clockgating_state,
 	.set_powergating_state = vcn_v2_0_set_powergating_state,
-	.dump_ip_state = NULL,
+	.dump_ip_state = vcn_v2_0_dump_ip_state,
 	.print_ip_state = NULL,
 };
 
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 28+ messages in thread

* [PATCH v1 12/15] drm/amdgpu: add print support for vcn_v2_0 ip dump
  2024-08-06  8:18 [PATCH v1 00/15] VCN IP DUMP support for remaining IP's Sunil Khatri
                   ` (10 preceding siblings ...)
  2024-08-06  8:18 ` [PATCH v1 11/15] drm/amdgpu: add vcn_v2_0 ip dump support Sunil Khatri
@ 2024-08-06  8:18 ` Sunil Khatri
  2024-08-06  8:18 ` [PATCH v1 13/15] drm/amdgpu: add vcn_v2_5 ip dump support Sunil Khatri
                   ` (2 subsequent siblings)
  14 siblings, 0 replies; 28+ messages in thread
From: Sunil Khatri @ 2024-08-06  8:18 UTC (permalink / raw)
  To: Alex Deucher, Christian König; +Cc: amd-gfx, Sunil Khatri

Add support for logging the registers in devcoredump
buffer for vcn_v2_0.

Signed-off-by: Sunil Khatri <sunil.khatri@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 34 ++++++++++++++++++++++++++-
 1 file changed, 33 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
index 062651f87aa7..5c7c429f08fd 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
@@ -2066,6 +2066,38 @@ static int vcn_v2_0_start_sriov(struct amdgpu_device *adev)
 	return vcn_v2_0_start_mmsch(adev, &adev->virt.mm_table);
 }
 
+static void vcn_v2_0_print_ip_state(void *handle, struct drm_printer *p)
+{
+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+	int i, j;
+	uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_2_0);
+	uint32_t inst_off, is_powered;
+
+	if (!adev->vcn.ip_dump)
+		return;
+
+	drm_printf(p, "num_instances:%d\n", adev->vcn.num_vcn_inst);
+	for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
+		if (adev->vcn.harvest_config & (1 << i)) {
+			drm_printf(p, "\nHarvested Instance:VCN%d Skipping dump\n", i);
+			continue;
+		}
+
+		inst_off = i * reg_count;
+		is_powered = (adev->vcn.ip_dump[inst_off] &
+				UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
+
+		if (is_powered) {
+			drm_printf(p, "\nActive Instance:VCN%d\n", i);
+			for (j = 0; j < reg_count; j++)
+				drm_printf(p, "%-50s \t 0x%08x\n", vcn_reg_list_2_0[j].reg_name,
+					   adev->vcn.ip_dump[inst_off + j]);
+		} else {
+			drm_printf(p, "\nInactive Instance:VCN%d\n", i);
+		}
+	}
+}
+
 static void vcn_v2_0_dump_ip_state(void *handle)
 {
 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
@@ -2113,7 +2145,7 @@ static const struct amd_ip_funcs vcn_v2_0_ip_funcs = {
 	.set_clockgating_state = vcn_v2_0_set_clockgating_state,
 	.set_powergating_state = vcn_v2_0_set_powergating_state,
 	.dump_ip_state = vcn_v2_0_dump_ip_state,
-	.print_ip_state = NULL,
+	.print_ip_state = vcn_v2_0_print_ip_state,
 };
 
 static const struct amdgpu_ring_funcs vcn_v2_0_dec_ring_vm_funcs = {
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 28+ messages in thread

* [PATCH v1 13/15] drm/amdgpu: add vcn_v2_5 ip dump support
  2024-08-06  8:18 [PATCH v1 00/15] VCN IP DUMP support for remaining IP's Sunil Khatri
                   ` (11 preceding siblings ...)
  2024-08-06  8:18 ` [PATCH v1 12/15] drm/amdgpu: add print support for vcn_v2_0 ip dump Sunil Khatri
@ 2024-08-06  8:18 ` Sunil Khatri
  2024-08-06  8:18 ` [PATCH v1 14/15] drm/amdgpu: add print support for vcn_v2_5 ip dump Sunil Khatri
  2024-08-06  8:18 ` [PATCH v1 15/15] drm/amdgpu: add vcn ip dump support for vcn_v2_6 Sunil Khatri
  14 siblings, 0 replies; 28+ messages in thread
From: Sunil Khatri @ 2024-08-06  8:18 UTC (permalink / raw)
  To: Alex Deucher, Christian König; +Cc: amd-gfx, Sunil Khatri

Add support of vcn ip dump in the devcoredump
for vcn_v2_5.

Signed-off-by: Sunil Khatri <sunil.khatri@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 110 +++++++++++++++++++++++++-
 1 file changed, 109 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
index 96f60c303161..724176c1c352 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
@@ -55,6 +55,73 @@
 
 #define VCN25_MAX_HW_INSTANCES_ARCTURUS			2
 
+static const struct amdgpu_hwip_reg_entry vcn_reg_list_2_5[] = {
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_POWER_STATUS),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RBC_RB_RPTR),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RBC_RB_WPTR),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_STATUS),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_CONTEXT_ID),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_GPCOM_VCPU_DATA0),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_GPCOM_VCPU_DATA1),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_GPCOM_VCPU_CMD),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_LMI_VCPU_NC1_64BIT_BAR_HIGH),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_LMI_VCPU_NC1_64BIT_BAR_LOW),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_LMI_RBC_IB_VMID),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_LMI_VCPU_CACHE_VMIDS_MULTI),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_LMI_VCPU_NC_VMIDS_MULTI),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_HI),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_LO),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_HI2),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_LO2),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_HI3),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_LO3),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_RPTR),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_RPTR2),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR2),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_RPTR3),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR3),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_SIZE),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_SIZE2),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_SIZE3),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_PGFSM_CONFIG),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_PGFSM_STATUS),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_SOFT_RESET),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_SOFT_RESET2),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_CGC_GATE),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_CGC_STATUS),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_CGC_CTRL),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_SUVD_CGC_GATE),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_SUVD_CGC_STATUS),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_SUVD_CGC_CTRL),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_LO4),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_HI4),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_SIZE4),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_RPTR4),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR4),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_VCPU_CACHE_OFFSET2),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_LMI_VCPU_CACHE3_64BIT_BAR_LOW),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_LMI_VCPU_CACHE3_64BIT_BAR_HIGH),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_LMI_VCPU_CACHE4_64BIT_BAR_LOW),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_LMI_VCPU_CACHE4_64BIT_BAR_HIGH),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_LMI_VCPU_CACHE5_64BIT_BAR_LOW),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_LMI_VCPU_CACHE5_64BIT_BAR_HIGH),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_LMI_VCPU_CACHE6_64BIT_BAR_LOW),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_LMI_VCPU_CACHE6_64BIT_BAR_HIGH),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_LMI_VCPU_CACHE7_64BIT_BAR_LOW),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_LMI_VCPU_CACHE7_64BIT_BAR_HIGH),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_LMI_STATUS),
+	SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_SCRATCH1)
+};
+
 static void vcn_v2_5_set_dec_ring_funcs(struct amdgpu_device *adev);
 static void vcn_v2_5_set_enc_ring_funcs(struct amdgpu_device *adev);
 static void vcn_v2_5_set_irq_funcs(struct amdgpu_device *adev);
@@ -122,6 +189,8 @@ static int vcn_v2_5_sw_init(void *handle)
 {
 	struct amdgpu_ring *ring;
 	int i, j, r;
+	uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_2_5);
+	uint32_t *ptr;
 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
 	for (j = 0; j < adev->vcn.num_vcn_inst; j++) {
@@ -241,6 +310,15 @@ static int vcn_v2_5_sw_init(void *handle)
 	if (r)
 		return r;
 
+	/* Allocate memory for VCN IP Dump buffer */
+	ptr = kcalloc(adev->vcn.num_vcn_inst * reg_count, sizeof(uint32_t), GFP_KERNEL);
+	if (ptr == NULL) {
+		DRM_ERROR("Failed to allocate memory for VCN IP Dump\n");
+		adev->vcn.ip_dump = NULL;
+	} else {
+		adev->vcn.ip_dump = ptr;
+	}
+
 	return 0;
 }
 
@@ -277,6 +355,8 @@ static int vcn_v2_5_sw_fini(void *handle)
 
 	r = amdgpu_vcn_sw_fini(adev);
 
+	kfree(adev->vcn.ip_dump);
+
 	return r;
 }
 
@@ -1876,6 +1956,34 @@ static void vcn_v2_5_set_irq_funcs(struct amdgpu_device *adev)
 	}
 }
 
+static void vcn_v2_5_dump_ip_state(void *handle)
+{
+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+	int i, j;
+	bool is_powered;
+	uint32_t inst_off;
+	uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_2_5);
+
+	if (!adev->vcn.ip_dump)
+		return;
+
+	for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
+		if (adev->vcn.harvest_config & (1 << i))
+			continue;
+
+		inst_off = i * reg_count;
+		/* mmUVD_POWER_STATUS is always readable and is first element of the array */
+		adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, i, mmUVD_POWER_STATUS);
+		is_powered = (adev->vcn.ip_dump[inst_off] &
+				UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
+
+		if (is_powered)
+			for (j = 1; j < reg_count; j++)
+				adev->vcn.ip_dump[inst_off + j] =
+					RREG32(SOC15_REG_ENTRY_OFFSET_INST(vcn_reg_list_2_5[j], i));
+	}
+}
+
 static const struct amd_ip_funcs vcn_v2_5_ip_funcs = {
 	.name = "vcn_v2_5",
 	.early_init = vcn_v2_5_early_init,
@@ -1894,7 +2002,7 @@ static const struct amd_ip_funcs vcn_v2_5_ip_funcs = {
 	.post_soft_reset = NULL,
 	.set_clockgating_state = vcn_v2_5_set_clockgating_state,
 	.set_powergating_state = vcn_v2_5_set_powergating_state,
-	.dump_ip_state = NULL,
+	.dump_ip_state = vcn_v2_5_dump_ip_state,
 	.print_ip_state = NULL,
 };
 
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 28+ messages in thread

* [PATCH v1 14/15] drm/amdgpu: add print support for vcn_v2_5 ip dump
  2024-08-06  8:18 [PATCH v1 00/15] VCN IP DUMP support for remaining IP's Sunil Khatri
                   ` (12 preceding siblings ...)
  2024-08-06  8:18 ` [PATCH v1 13/15] drm/amdgpu: add vcn_v2_5 ip dump support Sunil Khatri
@ 2024-08-06  8:18 ` Sunil Khatri
  2024-08-06  8:18 ` [PATCH v1 15/15] drm/amdgpu: add vcn ip dump support for vcn_v2_6 Sunil Khatri
  14 siblings, 0 replies; 28+ messages in thread
From: Sunil Khatri @ 2024-08-06  8:18 UTC (permalink / raw)
  To: Alex Deucher, Christian König; +Cc: amd-gfx, Sunil Khatri

Add support for logging the registers in devcoredump
buffer for vcn_v2_5.

Signed-off-by: Sunil Khatri <sunil.khatri@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 34 ++++++++++++++++++++++++++-
 1 file changed, 33 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
index 724176c1c352..fdbf56a0e46e 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
@@ -1956,6 +1956,38 @@ static void vcn_v2_5_set_irq_funcs(struct amdgpu_device *adev)
 	}
 }
 
+static void vcn_v2_5_print_ip_state(void *handle, struct drm_printer *p)
+{
+	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+	int i, j;
+	uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_2_5);
+	uint32_t inst_off, is_powered;
+
+	if (!adev->vcn.ip_dump)
+		return;
+
+	drm_printf(p, "num_instances:%d\n", adev->vcn.num_vcn_inst);
+	for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
+		if (adev->vcn.harvest_config & (1 << i)) {
+			drm_printf(p, "\nHarvested Instance:VCN%d Skipping dump\n", i);
+			continue;
+		}
+
+		inst_off = i * reg_count;
+		is_powered = (adev->vcn.ip_dump[inst_off] &
+				UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1;
+
+		if (is_powered) {
+			drm_printf(p, "\nActive Instance:VCN%d\n", i);
+			for (j = 0; j < reg_count; j++)
+				drm_printf(p, "%-50s \t 0x%08x\n", vcn_reg_list_2_5[j].reg_name,
+					   adev->vcn.ip_dump[inst_off + j]);
+		} else {
+			drm_printf(p, "\nInactive Instance:VCN%d\n", i);
+		}
+	}
+}
+
 static void vcn_v2_5_dump_ip_state(void *handle)
 {
 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
@@ -2003,7 +2035,7 @@ static const struct amd_ip_funcs vcn_v2_5_ip_funcs = {
 	.set_clockgating_state = vcn_v2_5_set_clockgating_state,
 	.set_powergating_state = vcn_v2_5_set_powergating_state,
 	.dump_ip_state = vcn_v2_5_dump_ip_state,
-	.print_ip_state = NULL,
+	.print_ip_state = vcn_v2_5_print_ip_state,
 };
 
 static const struct amd_ip_funcs vcn_v2_6_ip_funcs = {
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 28+ messages in thread

* [PATCH v1 15/15] drm/amdgpu: add vcn ip dump support for vcn_v2_6
  2024-08-06  8:18 [PATCH v1 00/15] VCN IP DUMP support for remaining IP's Sunil Khatri
                   ` (13 preceding siblings ...)
  2024-08-06  8:18 ` [PATCH v1 14/15] drm/amdgpu: add print support for vcn_v2_5 ip dump Sunil Khatri
@ 2024-08-06  8:18 ` Sunil Khatri
  2024-08-07  4:00   ` Alex Deucher
  14 siblings, 1 reply; 28+ messages in thread
From: Sunil Khatri @ 2024-08-06  8:18 UTC (permalink / raw)
  To: Alex Deucher, Christian König; +Cc: amd-gfx, Sunil Khatri

Add support for logging the registers in devcoredump
buffer for vcn_v2_6.

Signed-off-by: Sunil Khatri <sunil.khatri@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
index fdbf56a0e46e..d3e00c0bb608 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
@@ -2056,8 +2056,8 @@ static const struct amd_ip_funcs vcn_v2_6_ip_funcs = {
         .post_soft_reset = NULL,
         .set_clockgating_state = vcn_v2_5_set_clockgating_state,
         .set_powergating_state = vcn_v2_5_set_powergating_state,
-	.dump_ip_state = NULL,
-	.print_ip_state = NULL,
+	.dump_ip_state = vcn_v2_5_dump_ip_state,
+	.print_ip_state = vcn_v2_5_print_ip_state,
 };
 
 const struct amdgpu_ip_block_version vcn_v2_5_ip_block =
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 28+ messages in thread

* Re: [PATCH v1 15/15] drm/amdgpu: add vcn ip dump support for vcn_v2_6
  2024-08-06  8:18 ` [PATCH v1 15/15] drm/amdgpu: add vcn ip dump support for vcn_v2_6 Sunil Khatri
@ 2024-08-07  4:00   ` Alex Deucher
  0 siblings, 0 replies; 28+ messages in thread
From: Alex Deucher @ 2024-08-07  4:00 UTC (permalink / raw)
  To: Sunil Khatri; +Cc: Alex Deucher, Christian König, amd-gfx

The patches other than 4.0.3 are:
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
I think 4.0.3 needs the GET_INST() fix.

Alex

On Tue, Aug 6, 2024 at 4:18 AM Sunil Khatri <sunil.khatri@amd.com> wrote:
>
> Add support for logging the registers in devcoredump
> buffer for vcn_v2_6.
>
> Signed-off-by: Sunil Khatri <sunil.khatri@amd.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
> index fdbf56a0e46e..d3e00c0bb608 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
> @@ -2056,8 +2056,8 @@ static const struct amd_ip_funcs vcn_v2_6_ip_funcs = {
>          .post_soft_reset = NULL,
>          .set_clockgating_state = vcn_v2_5_set_clockgating_state,
>          .set_powergating_state = vcn_v2_5_set_powergating_state,
> -       .dump_ip_state = NULL,
> -       .print_ip_state = NULL,
> +       .dump_ip_state = vcn_v2_5_dump_ip_state,
> +       .print_ip_state = vcn_v2_5_print_ip_state,
>  };
>
>  const struct amdgpu_ip_block_version vcn_v2_5_ip_block =
> --
> 2.34.1
>

^ permalink raw reply	[flat|nested] 28+ messages in thread

end of thread, other threads:[~2024-08-08  9:29 UTC | newest]

Thread overview: 28+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2024-08-06  8:18 [PATCH v1 00/15] VCN IP DUMP support for remaining IP's Sunil Khatri
2024-08-06  8:18 ` [PATCH v1 01/15] drm/amdgpu: add vcn_v5_0 ip dump support Sunil Khatri
2024-08-06  8:18 ` [PATCH v1 02/15] drm/amdgpu: add print support for vcn_v5_0 ip dump Sunil Khatri
2024-08-06  8:18 ` [PATCH v1 03/15] drm/amdgpu: add vcn_v4_0 ip dump support Sunil Khatri
2024-08-06  8:18 ` [PATCH v1 04/15] drm/amdgpu: add print support for vcn_v4_0 ip dump Sunil Khatri
2024-08-06  8:18 ` [PATCH v1 05/15] drm/amdgpu: add vcn_v4_0_3 ip dump support Sunil Khatri
2024-08-06 21:28   ` Alex Deucher
2024-08-07  3:47     ` Khatri, Sunil
2024-08-07  3:51       ` Alex Deucher
2024-08-08  5:50     ` Lazar, Lijo
2024-08-08  7:06       ` Khatri, Sunil
2024-08-08  7:14         ` Lazar, Lijo
2024-08-08  7:29           ` Khatri, Sunil
2024-08-08  9:29             ` Sundararaju, Sathishkumar
2024-08-06  8:18 ` [PATCH v1 06/15] drm/amdgpu: add print support for vcn_v4_0_3 ip dump Sunil Khatri
2024-08-06 21:32   ` Alex Deucher
2024-08-07  3:37     ` Khatri, Sunil
2024-08-07  3:41       ` Alex Deucher
2024-08-06  8:18 ` [PATCH v1 07/15] drm/amdgpu: add vcn_v4_0_5 ip dump support Sunil Khatri
2024-08-06  8:18 ` [PATCH v1 08/15] drm/amdgpu: add print support for vcn_v4_0_5 ip dump Sunil Khatri
2024-08-06  8:18 ` [PATCH v1 09/15] drm/amdgpu: add vcn_v1_0 ip dump support Sunil Khatri
2024-08-06  8:18 ` [PATCH v1 10/15] drm/amdgpu: add print support for vcn_v1_0 ip dump Sunil Khatri
2024-08-06  8:18 ` [PATCH v1 11/15] drm/amdgpu: add vcn_v2_0 ip dump support Sunil Khatri
2024-08-06  8:18 ` [PATCH v1 12/15] drm/amdgpu: add print support for vcn_v2_0 ip dump Sunil Khatri
2024-08-06  8:18 ` [PATCH v1 13/15] drm/amdgpu: add vcn_v2_5 ip dump support Sunil Khatri
2024-08-06  8:18 ` [PATCH v1 14/15] drm/amdgpu: add print support for vcn_v2_5 ip dump Sunil Khatri
2024-08-06  8:18 ` [PATCH v1 15/15] drm/amdgpu: add vcn ip dump support for vcn_v2_6 Sunil Khatri
2024-08-07  4:00   ` Alex Deucher

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