* [PATCH] Revert "drm/amd/display: Tune min clk values for MPO for RV"
@ 2021-01-18 11:03 Pratik Vishwakarma
2021-01-18 13:22 ` Wu, Hersen
2021-01-18 15:23 ` Harry Wentland
0 siblings, 2 replies; 3+ messages in thread
From: Pratik Vishwakarma @ 2021-01-18 11:03 UTC (permalink / raw)
To: hersenxs.wu, amd-gfx
This reverts commit 6f3fca64cfb91fedf9b34ea27b2581e88d48c9b2.
Flash line issue when MPO enabled on idle screen was fixed by
commit 9d03bb102028 ("drm/amd/display: disable dcn10 pipe split by default")
This patch is no more required
Signed-off-by: Pratik Vishwakarma <Pratik.Vishwakarma@amd.com>
---
.../display/dc/clk_mgr/dcn10/rv1_clk_mgr.c | 30 ++-----------------
1 file changed, 3 insertions(+), 27 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c
index 75b8240ed059..e133edc587d3 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c
@@ -187,17 +187,6 @@ static void ramp_up_dispclk_with_dpp(
clk_mgr->base.clks.max_supported_dppclk_khz = new_clocks->max_supported_dppclk_khz;
}
-static bool is_mpo_enabled(struct dc_state *context)
-{
- int i;
-
- for (i = 0; i < context->stream_count; i++) {
- if (context->stream_status[i].plane_count > 1)
- return true;
- }
- return false;
-}
-
static void rv1_update_clocks(struct clk_mgr *clk_mgr_base,
struct dc_state *context,
bool safe_to_lower)
@@ -295,22 +284,9 @@ static void rv1_update_clocks(struct clk_mgr *clk_mgr_base,
if (pp_smu->set_hard_min_fclk_by_freq &&
pp_smu->set_hard_min_dcfclk_by_freq &&
pp_smu->set_min_deep_sleep_dcfclk) {
- // Only increase clocks when display is active and MPO is enabled
- if (display_count && is_mpo_enabled(context)) {
- pp_smu->set_hard_min_fclk_by_freq(&pp_smu->pp_smu,
- ((new_clocks->fclk_khz / 1000) * 101) / 100);
- pp_smu->set_hard_min_dcfclk_by_freq(&pp_smu->pp_smu,
- ((new_clocks->dcfclk_khz / 1000) * 101) / 100);
- pp_smu->set_min_deep_sleep_dcfclk(&pp_smu->pp_smu,
- (new_clocks->dcfclk_deep_sleep_khz + 999) / 1000);
- } else {
- pp_smu->set_hard_min_fclk_by_freq(&pp_smu->pp_smu,
- new_clocks->fclk_khz / 1000);
- pp_smu->set_hard_min_dcfclk_by_freq(&pp_smu->pp_smu,
- new_clocks->dcfclk_khz / 1000);
- pp_smu->set_min_deep_sleep_dcfclk(&pp_smu->pp_smu,
- (new_clocks->dcfclk_deep_sleep_khz + 999) / 1000);
- }
+ pp_smu->set_hard_min_fclk_by_freq(&pp_smu->pp_smu, new_clocks->fclk_khz / 1000);
+ pp_smu->set_hard_min_dcfclk_by_freq(&pp_smu->pp_smu, new_clocks->dcfclk_khz / 1000);
+ pp_smu->set_min_deep_sleep_dcfclk(&pp_smu->pp_smu, (new_clocks->dcfclk_deep_sleep_khz + 999) / 1000);
}
}
}
--
2.25.1
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^ permalink raw reply related [flat|nested] 3+ messages in thread* RE: [PATCH] Revert "drm/amd/display: Tune min clk values for MPO for RV"
2021-01-18 11:03 [PATCH] Revert "drm/amd/display: Tune min clk values for MPO for RV" Pratik Vishwakarma
@ 2021-01-18 13:22 ` Wu, Hersen
2021-01-18 15:23 ` Harry Wentland
1 sibling, 0 replies; 3+ messages in thread
From: Wu, Hersen @ 2021-01-18 13:22 UTC (permalink / raw)
To: Vishwakarma, Pratik, amd-gfx@lists.freedesktop.org
[AMD Official Use Only - Internal Distribution Only]
Reviewed-by: Hersen Wu <hersenxs.wu@amd.com>
-----Original Message-----
From: Vishwakarma, Pratik <Pratik.Vishwakarma@amd.com>
Sent: Monday, January 18, 2021 6:04 AM
To: Wu, Hersen <hersenxs.wu@amd.com>; amd-gfx@lists.freedesktop.org
Cc: Vishwakarma, Pratik <Pratik.Vishwakarma@amd.com>
Subject: [PATCH] Revert "drm/amd/display: Tune min clk values for MPO for RV"
This reverts commit 6f3fca64cfb91fedf9b34ea27b2581e88d48c9b2.
Flash line issue when MPO enabled on idle screen was fixed by commit 9d03bb102028 ("drm/amd/display: disable dcn10 pipe split by default")
This patch is no more required
Signed-off-by: Pratik Vishwakarma <Pratik.Vishwakarma@amd.com>
---
.../display/dc/clk_mgr/dcn10/rv1_clk_mgr.c | 30 ++-----------------
1 file changed, 3 insertions(+), 27 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c
index 75b8240ed059..e133edc587d3 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c
@@ -187,17 +187,6 @@ static void ramp_up_dispclk_with_dpp(
clk_mgr->base.clks.max_supported_dppclk_khz = new_clocks->max_supported_dppclk_khz;
}
-static bool is_mpo_enabled(struct dc_state *context) -{
- int i;
-
- for (i = 0; i < context->stream_count; i++) {
- if (context->stream_status[i].plane_count > 1)
- return true;
- }
- return false;
-}
-
static void rv1_update_clocks(struct clk_mgr *clk_mgr_base,
struct dc_state *context,
bool safe_to_lower)
@@ -295,22 +284,9 @@ static void rv1_update_clocks(struct clk_mgr *clk_mgr_base,
if (pp_smu->set_hard_min_fclk_by_freq &&
pp_smu->set_hard_min_dcfclk_by_freq &&
pp_smu->set_min_deep_sleep_dcfclk) {
- // Only increase clocks when display is active and MPO is enabled
- if (display_count && is_mpo_enabled(context)) {
- pp_smu->set_hard_min_fclk_by_freq(&pp_smu->pp_smu,
- ((new_clocks->fclk_khz / 1000) * 101) / 100);
- pp_smu->set_hard_min_dcfclk_by_freq(&pp_smu->pp_smu,
- ((new_clocks->dcfclk_khz / 1000) * 101) / 100);
- pp_smu->set_min_deep_sleep_dcfclk(&pp_smu->pp_smu,
- (new_clocks->dcfclk_deep_sleep_khz + 999) / 1000);
- } else {
- pp_smu->set_hard_min_fclk_by_freq(&pp_smu->pp_smu,
- new_clocks->fclk_khz / 1000);
- pp_smu->set_hard_min_dcfclk_by_freq(&pp_smu->pp_smu,
- new_clocks->dcfclk_khz / 1000);
- pp_smu->set_min_deep_sleep_dcfclk(&pp_smu->pp_smu,
- (new_clocks->dcfclk_deep_sleep_khz + 999) / 1000);
- }
+ pp_smu->set_hard_min_fclk_by_freq(&pp_smu->pp_smu, new_clocks->fclk_khz / 1000);
+ pp_smu->set_hard_min_dcfclk_by_freq(&pp_smu->pp_smu, new_clocks->dcfclk_khz / 1000);
+ pp_smu->set_min_deep_sleep_dcfclk(&pp_smu->pp_smu,
+(new_clocks->dcfclk_deep_sleep_khz + 999) / 1000);
}
}
}
--
2.25.1
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^ permalink raw reply related [flat|nested] 3+ messages in thread* Re: [PATCH] Revert "drm/amd/display: Tune min clk values for MPO for RV"
2021-01-18 11:03 [PATCH] Revert "drm/amd/display: Tune min clk values for MPO for RV" Pratik Vishwakarma
2021-01-18 13:22 ` Wu, Hersen
@ 2021-01-18 15:23 ` Harry Wentland
1 sibling, 0 replies; 3+ messages in thread
From: Harry Wentland @ 2021-01-18 15:23 UTC (permalink / raw)
To: Pratik Vishwakarma, hersenxs.wu, amd-gfx
On 2021-01-18 6:03 a.m., Pratik Vishwakarma wrote:
> This reverts commit 6f3fca64cfb91fedf9b34ea27b2581e88d48c9b2.
> Flash line issue when MPO enabled on idle screen was fixed by
> commit 9d03bb102028 ("drm/amd/display: disable dcn10 pipe split by default")
>
> This patch is no more required
Do you have additional details? I'm curious how/where this was fixed, or
why this is not required anymore.
Harry
>
> Signed-off-by: Pratik Vishwakarma <Pratik.Vishwakarma@amd.com>
> ---
> .../display/dc/clk_mgr/dcn10/rv1_clk_mgr.c | 30 ++-----------------
> 1 file changed, 3 insertions(+), 27 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c
> index 75b8240ed059..e133edc587d3 100644
> --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c
> +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c
> @@ -187,17 +187,6 @@ static void ramp_up_dispclk_with_dpp(
> clk_mgr->base.clks.max_supported_dppclk_khz = new_clocks->max_supported_dppclk_khz;
> }
>
> -static bool is_mpo_enabled(struct dc_state *context)
> -{
> - int i;
> -
> - for (i = 0; i < context->stream_count; i++) {
> - if (context->stream_status[i].plane_count > 1)
> - return true;
> - }
> - return false;
> -}
> -
> static void rv1_update_clocks(struct clk_mgr *clk_mgr_base,
> struct dc_state *context,
> bool safe_to_lower)
> @@ -295,22 +284,9 @@ static void rv1_update_clocks(struct clk_mgr *clk_mgr_base,
> if (pp_smu->set_hard_min_fclk_by_freq &&
> pp_smu->set_hard_min_dcfclk_by_freq &&
> pp_smu->set_min_deep_sleep_dcfclk) {
> - // Only increase clocks when display is active and MPO is enabled
> - if (display_count && is_mpo_enabled(context)) {
> - pp_smu->set_hard_min_fclk_by_freq(&pp_smu->pp_smu,
> - ((new_clocks->fclk_khz / 1000) * 101) / 100);
> - pp_smu->set_hard_min_dcfclk_by_freq(&pp_smu->pp_smu,
> - ((new_clocks->dcfclk_khz / 1000) * 101) / 100);
> - pp_smu->set_min_deep_sleep_dcfclk(&pp_smu->pp_smu,
> - (new_clocks->dcfclk_deep_sleep_khz + 999) / 1000);
> - } else {
> - pp_smu->set_hard_min_fclk_by_freq(&pp_smu->pp_smu,
> - new_clocks->fclk_khz / 1000);
> - pp_smu->set_hard_min_dcfclk_by_freq(&pp_smu->pp_smu,
> - new_clocks->dcfclk_khz / 1000);
> - pp_smu->set_min_deep_sleep_dcfclk(&pp_smu->pp_smu,
> - (new_clocks->dcfclk_deep_sleep_khz + 999) / 1000);
> - }
> + pp_smu->set_hard_min_fclk_by_freq(&pp_smu->pp_smu, new_clocks->fclk_khz / 1000);
> + pp_smu->set_hard_min_dcfclk_by_freq(&pp_smu->pp_smu, new_clocks->dcfclk_khz / 1000);
> + pp_smu->set_min_deep_sleep_dcfclk(&pp_smu->pp_smu, (new_clocks->dcfclk_deep_sleep_khz + 999) / 1000);
> }
> }
> }
>
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^ permalink raw reply [flat|nested] 3+ messages in thread
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2021-01-18 11:03 [PATCH] Revert "drm/amd/display: Tune min clk values for MPO for RV" Pratik Vishwakarma
2021-01-18 13:22 ` Wu, Hersen
2021-01-18 15:23 ` Harry Wentland
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