* [PATCH] drm/amdgpu: Fix KIQ hang on bare metal for device unbind/bind back.
@ 2018-03-28 12:37 Andrey Grodzovsky
[not found] ` <1522240658-2648-1-git-send-email-andrey.grodzovsky-5C7GfCeVMHo@public.gmane.org>
0 siblings, 1 reply; 6+ messages in thread
From: Andrey Grodzovsky @ 2018-03-28 12:37 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Alexander.Deucher-5C7GfCeVMHo, Andrey Grodzovsky,
Pixel.Ding-5C7GfCeVMHo, Rex.Zhu-5C7GfCeVMHo
Problem: When unbind and then bind back the device KIQ hangs on Vega
after mapping KCQs request.
Fix: Adding deinitialzie code from CAIL during HW fini solves the
hang.
Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 52 ++++++++++++++++++++++++++++++++++-
1 file changed, 51 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 1ae3de1..fd13065 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -2757,6 +2757,45 @@ static int gfx_v9_0_kiq_init_register(struct amdgpu_ring *ring)
return 0;
}
+static int gfx_v9_0_kiq_fini_register(struct amdgpu_ring *ring)
+{
+ struct amdgpu_device *adev = ring->adev;
+ int j;
+
+ /* disable the queue if it's active */
+ if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) {
+
+ WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1);
+
+ for (j = 0; j < adev->usec_timeout; j++) {
+ if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1))
+ break;
+ udelay(1);
+ }
+
+ if (adev->usec_timeout == AMDGPU_MAX_USEC_TIMEOUT) {
+ DRM_DEBUG("KIQ dequeue request failed.\n");
+
+ WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, 0);
+ }
+
+ /* Manual disable if dequeue request times out */
+ WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST,
+ 0);
+ }
+
+ WREG32_SOC15(GC, 0, mmCP_HQD_IQ_TIMER, 0);
+ WREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL, 0);
+ WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE, 0);
+ WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 0x40000000);
+ WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 0);
+ WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR, 0);
+ WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI, 0);
+ WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO, 0);
+
+ return 0;
+}
+
static int gfx_v9_0_kiq_init_queue(struct amdgpu_ring *ring)
{
struct amdgpu_device *adev = ring->adev;
@@ -3010,7 +3049,6 @@ static int gfx_v9_0_kcq_disable(struct amdgpu_ring *kiq_ring,struct amdgpu_ring
return r;
}
-
static int gfx_v9_0_hw_fini(void *handle)
{
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
@@ -3033,6 +3071,18 @@ static int gfx_v9_0_hw_fini(void *handle)
WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0);
return 0;
}
+
+ /* Use deinitialize sequence from CAIL when unbinding device from driver,
+ * otherwise KIQ is hanging when binding back
+ */
+ if (!adev->in_gpu_reset && !adev->gfx.in_suspend) {
+ soc15_grbm_select(adev, adev->gfx.kiq.ring.me,
+ adev->gfx.kiq.ring.pipe,
+ adev->gfx.kiq.ring.queue, 0);
+ gfx_v9_0_kiq_fini_register(&adev->gfx.kiq.ring);
+ soc15_grbm_select(adev, 0, 0, 0, 0);
+ }
+
gfx_v9_0_cp_enable(adev, false);
gfx_v9_0_rlc_stop(adev);
--
2.7.4
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH] drm/amdgpu: Fix KIQ hang on bare metal for device unbind/bind back.
[not found] ` <1522240658-2648-1-git-send-email-andrey.grodzovsky-5C7GfCeVMHo@public.gmane.org>
@ 2018-03-28 14:09 ` Alex Deucher
2018-03-31 11:05 ` Liu, Monk
2018-03-31 11:09 ` Liu, Monk
2 siblings, 0 replies; 6+ messages in thread
From: Alex Deucher @ 2018-03-28 14:09 UTC (permalink / raw)
To: Andrey Grodzovsky; +Cc: Deucher, Alexander, Pixel Ding, Rex Zhu, amd-gfx list
On Wed, Mar 28, 2018 at 8:37 AM, Andrey Grodzovsky
<andrey.grodzovsky@amd.com> wrote:
> Problem: When unbind and then bind back the device KIQ hangs on Vega
> after mapping KCQs request.
>
> Fix: Adding deinitialzie code from CAIL during HW fini solves the
> hang.
>
> Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 52 ++++++++++++++++++++++++++++++++++-
> 1 file changed, 51 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> index 1ae3de1..fd13065 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> @@ -2757,6 +2757,45 @@ static int gfx_v9_0_kiq_init_register(struct amdgpu_ring *ring)
> return 0;
> }
>
> +static int gfx_v9_0_kiq_fini_register(struct amdgpu_ring *ring)
> +{
> + struct amdgpu_device *adev = ring->adev;
> + int j;
> +
> + /* disable the queue if it's active */
> + if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) {
> +
> + WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1);
> +
> + for (j = 0; j < adev->usec_timeout; j++) {
> + if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1))
> + break;
> + udelay(1);
> + }
> +
> + if (adev->usec_timeout == AMDGPU_MAX_USEC_TIMEOUT) {
> + DRM_DEBUG("KIQ dequeue request failed.\n");
> +
> + WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, 0);
> + }
> +
> + /* Manual disable if dequeue request times out */
> + WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST,
> + 0);
> + }
> +
> + WREG32_SOC15(GC, 0, mmCP_HQD_IQ_TIMER, 0);
> + WREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL, 0);
> + WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE, 0);
> + WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 0x40000000);
> + WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 0);
> + WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR, 0);
> + WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI, 0);
> + WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO, 0);
> +
> + return 0;
> +}
> +
> static int gfx_v9_0_kiq_init_queue(struct amdgpu_ring *ring)
> {
> struct amdgpu_device *adev = ring->adev;
> @@ -3010,7 +3049,6 @@ static int gfx_v9_0_kcq_disable(struct amdgpu_ring *kiq_ring,struct amdgpu_ring
> return r;
> }
>
> -
> static int gfx_v9_0_hw_fini(void *handle)
> {
> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
> @@ -3033,6 +3071,18 @@ static int gfx_v9_0_hw_fini(void *handle)
> WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0);
> return 0;
> }
> +
> + /* Use deinitialize sequence from CAIL when unbinding device from driver,
> + * otherwise KIQ is hanging when binding back
> + */
> + if (!adev->in_gpu_reset && !adev->gfx.in_suspend) {
You need to take the srbm_mutex before using soc15_grbm_select().
WIth that fixed:
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
> + soc15_grbm_select(adev, adev->gfx.kiq.ring.me,
> + adev->gfx.kiq.ring.pipe,
> + adev->gfx.kiq.ring.queue, 0);
> + gfx_v9_0_kiq_fini_register(&adev->gfx.kiq.ring);
> + soc15_grbm_select(adev, 0, 0, 0, 0);
> + }
> +
> gfx_v9_0_cp_enable(adev, false);
> gfx_v9_0_rlc_stop(adev);
>
> --
> 2.7.4
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 6+ messages in thread
* RE: [PATCH] drm/amdgpu: Fix KIQ hang on bare metal for device unbind/bind back.
[not found] ` <1522240658-2648-1-git-send-email-andrey.grodzovsky-5C7GfCeVMHo@public.gmane.org>
2018-03-28 14:09 ` Alex Deucher
@ 2018-03-31 11:05 ` Liu, Monk
[not found] ` <BLUPR12MB044980331171FE27298FD39684A00-7LeqcoF/hwpTIQvHjXdJlwdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
2018-03-31 11:09 ` Liu, Monk
2 siblings, 1 reply; 6+ messages in thread
From: Liu, Monk @ 2018-03-31 11:05 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
Cc: Deucher, Alexander, Grodzovsky, Andrey, Ding, Pixel, Zhu, Rex
+ WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1);
+
+ for (j = 0; j < adev->usec_timeout; j++) {
+ if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1))
+ break;
+ udelay(1);
+ }
+
+ if (adev->usec_timeout == AMDGPU_MAX_USEC_TIMEOUT) {
+ DRM_DEBUG("KIQ dequeue request failed.\n");
+
+ WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, 0);
+ }
I don't understand why you compare adev->usec_timeout ? shouldn't it be j ?
/Monk
-----Original Message-----
From: amd-gfx [mailto:amd-gfx-bounces@lists.freedesktop.org] On Behalf Of Andrey Grodzovsky
Sent: 2018年3月28日 20:38
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander <Alexander.Deucher@amd.com>; Grodzovsky, Andrey <Andrey.Grodzovsky@amd.com>; Ding, Pixel <Pixel.Ding@amd.com>; Zhu, Rex <Rex.Zhu@amd.com>
Subject: [PATCH] drm/amdgpu: Fix KIQ hang on bare metal for device unbind/bind back.
Problem: When unbind and then bind back the device KIQ hangs on Vega after mapping KCQs request.
Fix: Adding deinitialzie code from CAIL during HW fini solves the hang.
Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 52 ++++++++++++++++++++++++++++++++++-
1 file changed, 51 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 1ae3de1..fd13065 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -2757,6 +2757,45 @@ static int gfx_v9_0_kiq_init_register(struct amdgpu_ring *ring)
return 0;
}
+static int gfx_v9_0_kiq_fini_register(struct amdgpu_ring *ring) {
+ struct amdgpu_device *adev = ring->adev;
+ int j;
+
+ /* disable the queue if it's active */
+ if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) {
+
+ WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1);
+
+ for (j = 0; j < adev->usec_timeout; j++) {
+ if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1))
+ break;
+ udelay(1);
+ }
+
+ if (adev->usec_timeout == AMDGPU_MAX_USEC_TIMEOUT) {
+ DRM_DEBUG("KIQ dequeue request failed.\n");
+
+ WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, 0);
+ }
+
+ /* Manual disable if dequeue request times out */
+ WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST,
+ 0);
+ }
+
+ WREG32_SOC15(GC, 0, mmCP_HQD_IQ_TIMER, 0);
+ WREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL, 0);
+ WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE, 0);
+ WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 0x40000000);
+ WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 0);
+ WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR, 0);
+ WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI, 0);
+ WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO, 0);
+
+ return 0;
+}
+
static int gfx_v9_0_kiq_init_queue(struct amdgpu_ring *ring) {
struct amdgpu_device *adev = ring->adev; @@ -3010,7 +3049,6 @@ static int gfx_v9_0_kcq_disable(struct amdgpu_ring *kiq_ring,struct amdgpu_ring
return r;
}
-
static int gfx_v9_0_hw_fini(void *handle) {
struct amdgpu_device *adev = (struct amdgpu_device *)handle; @@ -3033,6 +3071,18 @@ static int gfx_v9_0_hw_fini(void *handle)
WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0);
return 0;
}
+
+ /* Use deinitialize sequence from CAIL when unbinding device from driver,
+ * otherwise KIQ is hanging when binding back
+ */
+ if (!adev->in_gpu_reset && !adev->gfx.in_suspend) {
+ soc15_grbm_select(adev, adev->gfx.kiq.ring.me,
+ adev->gfx.kiq.ring.pipe,
+ adev->gfx.kiq.ring.queue, 0);
+ gfx_v9_0_kiq_fini_register(&adev->gfx.kiq.ring);
+ soc15_grbm_select(adev, 0, 0, 0, 0);
+ }
+
gfx_v9_0_cp_enable(adev, false);
gfx_v9_0_rlc_stop(adev);
--
2.7.4
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 6+ messages in thread
* RE: [PATCH] drm/amdgpu: Fix KIQ hang on bare metal for device unbind/bind back.
[not found] ` <1522240658-2648-1-git-send-email-andrey.grodzovsky-5C7GfCeVMHo@public.gmane.org>
2018-03-28 14:09 ` Alex Deucher
2018-03-31 11:05 ` Liu, Monk
@ 2018-03-31 11:09 ` Liu, Monk
[not found] ` <BLUPR12MB0449BA46452663601FC2959984A00-7LeqcoF/hwpTIQvHjXdJlwdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
2 siblings, 1 reply; 6+ messages in thread
From: Liu, Monk @ 2018-03-31 11:09 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
Cc: Deucher, Alexander, Grodzovsky, Andrey, Ding, Pixel, Zhu, Rex
+ if (adev->usec_timeout == AMDGPU_MAX_USEC_TIMEOUT) {
+ DRM_DEBUG("KIQ dequeue request failed.\n");
+
+ WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, 0);
+ }
+
+ /* Manual disable if dequeue request times out */
+ WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST,
+ 0);
You said "manually disable if dequeue request time out, but looks the logic is you always
Run this anyway
/Monk
-----Original Message-----
From: amd-gfx [mailto:amd-gfx-bounces@lists.freedesktop.org] On Behalf Of Andrey Grodzovsky
Sent: 2018年3月28日 20:38
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander <Alexander.Deucher@amd.com>; Grodzovsky, Andrey <Andrey.Grodzovsky@amd.com>; Ding, Pixel <Pixel.Ding@amd.com>; Zhu, Rex <Rex.Zhu@amd.com>
Subject: [PATCH] drm/amdgpu: Fix KIQ hang on bare metal for device unbind/bind back.
Problem: When unbind and then bind back the device KIQ hangs on Vega after mapping KCQs request.
Fix: Adding deinitialzie code from CAIL during HW fini solves the hang.
Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 52 ++++++++++++++++++++++++++++++++++-
1 file changed, 51 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 1ae3de1..fd13065 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -2757,6 +2757,45 @@ static int gfx_v9_0_kiq_init_register(struct amdgpu_ring *ring)
return 0;
}
+static int gfx_v9_0_kiq_fini_register(struct amdgpu_ring *ring) {
+ struct amdgpu_device *adev = ring->adev;
+ int j;
+
+ /* disable the queue if it's active */
+ if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) {
+
+ WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1);
+
+ for (j = 0; j < adev->usec_timeout; j++) {
+ if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1))
+ break;
+ udelay(1);
+ }
+
+ if (adev->usec_timeout == AMDGPU_MAX_USEC_TIMEOUT) {
+ DRM_DEBUG("KIQ dequeue request failed.\n");
+
+ WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, 0);
+ }
+
+ /* Manual disable if dequeue request times out */
+ WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST,
+ 0);
+ }
+
+ WREG32_SOC15(GC, 0, mmCP_HQD_IQ_TIMER, 0);
+ WREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL, 0);
+ WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE, 0);
+ WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 0x40000000);
+ WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 0);
+ WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR, 0);
+ WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI, 0);
+ WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO, 0);
+
+ return 0;
+}
+
static int gfx_v9_0_kiq_init_queue(struct amdgpu_ring *ring) {
struct amdgpu_device *adev = ring->adev; @@ -3010,7 +3049,6 @@ static int gfx_v9_0_kcq_disable(struct amdgpu_ring *kiq_ring,struct amdgpu_ring
return r;
}
-
static int gfx_v9_0_hw_fini(void *handle) {
struct amdgpu_device *adev = (struct amdgpu_device *)handle; @@ -3033,6 +3071,18 @@ static int gfx_v9_0_hw_fini(void *handle)
WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0);
return 0;
}
+
+ /* Use deinitialize sequence from CAIL when unbinding device from driver,
+ * otherwise KIQ is hanging when binding back
+ */
+ if (!adev->in_gpu_reset && !adev->gfx.in_suspend) {
+ soc15_grbm_select(adev, adev->gfx.kiq.ring.me,
+ adev->gfx.kiq.ring.pipe,
+ adev->gfx.kiq.ring.queue, 0);
+ gfx_v9_0_kiq_fini_register(&adev->gfx.kiq.ring);
+ soc15_grbm_select(adev, 0, 0, 0, 0);
+ }
+
gfx_v9_0_cp_enable(adev, false);
gfx_v9_0_rlc_stop(adev);
--
2.7.4
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH] drm/amdgpu: Fix KIQ hang on bare metal for device unbind/bind back.
[not found] ` <BLUPR12MB044980331171FE27298FD39684A00-7LeqcoF/hwpTIQvHjXdJlwdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
@ 2018-04-02 13:57 ` Andrey Grodzovsky
0 siblings, 0 replies; 6+ messages in thread
From: Andrey Grodzovsky @ 2018-04-02 13:57 UTC (permalink / raw)
To: Liu, Monk,
amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
Cc: Deucher, Alexander, Ding, Pixel, Zhu, Rex
Yep, a typo, will fix.
Andrey
On 03/31/2018 07:05 AM, Liu, Monk wrote:
> + WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1);
> +
> + for (j = 0; j < adev->usec_timeout; j++) {
> + if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1))
> + break;
> + udelay(1);
> + }
> +
> + if (adev->usec_timeout == AMDGPU_MAX_USEC_TIMEOUT) {
> + DRM_DEBUG("KIQ dequeue request failed.\n");
> +
> + WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, 0);
> + }
>
>
> I don't understand why you compare adev->usec_timeout ? shouldn't it be j ?
>
> /Monk
>
> -----Original Message-----
> From: amd-gfx [mailto:amd-gfx-bounces@lists.freedesktop.org] On Behalf Of Andrey Grodzovsky
> Sent: 2018年3月28日 20:38
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander <Alexander.Deucher@amd.com>; Grodzovsky, Andrey <Andrey.Grodzovsky@amd.com>; Ding, Pixel <Pixel.Ding@amd.com>; Zhu, Rex <Rex.Zhu@amd.com>
> Subject: [PATCH] drm/amdgpu: Fix KIQ hang on bare metal for device unbind/bind back.
>
> Problem: When unbind and then bind back the device KIQ hangs on Vega after mapping KCQs request.
>
> Fix: Adding deinitialzie code from CAIL during HW fini solves the hang.
>
> Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 52 ++++++++++++++++++++++++++++++++++-
> 1 file changed, 51 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> index 1ae3de1..fd13065 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> @@ -2757,6 +2757,45 @@ static int gfx_v9_0_kiq_init_register(struct amdgpu_ring *ring)
> return 0;
> }
>
> +static int gfx_v9_0_kiq_fini_register(struct amdgpu_ring *ring) {
> + struct amdgpu_device *adev = ring->adev;
> + int j;
> +
> + /* disable the queue if it's active */
> + if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) {
> +
> + WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1);
> +
> + for (j = 0; j < adev->usec_timeout; j++) {
> + if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1))
> + break;
> + udelay(1);
> + }
> +
> + if (adev->usec_timeout == AMDGPU_MAX_USEC_TIMEOUT) {
> + DRM_DEBUG("KIQ dequeue request failed.\n");
> +
> + WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, 0);
> + }
> +
> + /* Manual disable if dequeue request times out */
> + WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST,
> + 0);
> + }
> +
> + WREG32_SOC15(GC, 0, mmCP_HQD_IQ_TIMER, 0);
> + WREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL, 0);
> + WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE, 0);
> + WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 0x40000000);
> + WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 0);
> + WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR, 0);
> + WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI, 0);
> + WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO, 0);
> +
> + return 0;
> +}
> +
> static int gfx_v9_0_kiq_init_queue(struct amdgpu_ring *ring) {
> struct amdgpu_device *adev = ring->adev; @@ -3010,7 +3049,6 @@ static int gfx_v9_0_kcq_disable(struct amdgpu_ring *kiq_ring,struct amdgpu_ring
> return r;
> }
>
> -
> static int gfx_v9_0_hw_fini(void *handle) {
> struct amdgpu_device *adev = (struct amdgpu_device *)handle; @@ -3033,6 +3071,18 @@ static int gfx_v9_0_hw_fini(void *handle)
> WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0);
> return 0;
> }
> +
> + /* Use deinitialize sequence from CAIL when unbinding device from driver,
> + * otherwise KIQ is hanging when binding back
> + */
> + if (!adev->in_gpu_reset && !adev->gfx.in_suspend) {
> + soc15_grbm_select(adev, adev->gfx.kiq.ring.me,
> + adev->gfx.kiq.ring.pipe,
> + adev->gfx.kiq.ring.queue, 0);
> + gfx_v9_0_kiq_fini_register(&adev->gfx.kiq.ring);
> + soc15_grbm_select(adev, 0, 0, 0, 0);
> + }
> +
> gfx_v9_0_cp_enable(adev, false);
> gfx_v9_0_rlc_stop(adev);
>
> --
> 2.7.4
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] drm/amdgpu: Fix KIQ hang on bare metal for device unbind/bind back.
[not found] ` <BLUPR12MB0449BA46452663601FC2959984A00-7LeqcoF/hwpTIQvHjXdJlwdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
@ 2018-04-02 14:00 ` Andrey Grodzovsky
0 siblings, 0 replies; 6+ messages in thread
From: Andrey Grodzovsky @ 2018-04-02 14:00 UTC (permalink / raw)
To: Liu, Monk,
amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
Cc: Deucher, Alexander, Ding, Pixel, Zhu, Rex
Another mistake, the comment is displaced, will fix to.
Thanks,
Andrey
On 03/31/2018 07:09 AM, Liu, Monk wrote:
> + if (adev->usec_timeout == AMDGPU_MAX_USEC_TIMEOUT) {
> + DRM_DEBUG("KIQ dequeue request failed.\n");
> +
> + WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, 0);
> + }
> +
> + /* Manual disable if dequeue request times out */
> + WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST,
> + 0);
>
> You said "manually disable if dequeue request time out, but looks the logic is you always
> Run this anyway
>
> /Monk
>
> -----Original Message-----
> From: amd-gfx [mailto:amd-gfx-bounces@lists.freedesktop.org] On Behalf Of Andrey Grodzovsky
> Sent: 2018年3月28日 20:38
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander <Alexander.Deucher@amd.com>; Grodzovsky, Andrey <Andrey.Grodzovsky@amd.com>; Ding, Pixel <Pixel.Ding@amd.com>; Zhu, Rex <Rex.Zhu@amd.com>
> Subject: [PATCH] drm/amdgpu: Fix KIQ hang on bare metal for device unbind/bind back.
>
> Problem: When unbind and then bind back the device KIQ hangs on Vega after mapping KCQs request.
>
> Fix: Adding deinitialzie code from CAIL during HW fini solves the hang.
>
> Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 52 ++++++++++++++++++++++++++++++++++-
> 1 file changed, 51 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> index 1ae3de1..fd13065 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> @@ -2757,6 +2757,45 @@ static int gfx_v9_0_kiq_init_register(struct amdgpu_ring *ring)
> return 0;
> }
>
> +static int gfx_v9_0_kiq_fini_register(struct amdgpu_ring *ring) {
> + struct amdgpu_device *adev = ring->adev;
> + int j;
> +
> + /* disable the queue if it's active */
> + if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) {
> +
> + WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1);
> +
> + for (j = 0; j < adev->usec_timeout; j++) {
> + if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1))
> + break;
> + udelay(1);
> + }
> +
> + if (adev->usec_timeout == AMDGPU_MAX_USEC_TIMEOUT) {
> + DRM_DEBUG("KIQ dequeue request failed.\n");
> +
> + WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, 0);
> + }
> +
> + /* Manual disable if dequeue request times out */
> + WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST,
> + 0);
> + }
> +
> + WREG32_SOC15(GC, 0, mmCP_HQD_IQ_TIMER, 0);
> + WREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL, 0);
> + WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE, 0);
> + WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 0x40000000);
> + WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 0);
> + WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR, 0);
> + WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI, 0);
> + WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO, 0);
> +
> + return 0;
> +}
> +
> static int gfx_v9_0_kiq_init_queue(struct amdgpu_ring *ring) {
> struct amdgpu_device *adev = ring->adev; @@ -3010,7 +3049,6 @@ static int gfx_v9_0_kcq_disable(struct amdgpu_ring *kiq_ring,struct amdgpu_ring
> return r;
> }
>
> -
> static int gfx_v9_0_hw_fini(void *handle) {
> struct amdgpu_device *adev = (struct amdgpu_device *)handle; @@ -3033,6 +3071,18 @@ static int gfx_v9_0_hw_fini(void *handle)
> WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0);
> return 0;
> }
> +
> + /* Use deinitialize sequence from CAIL when unbinding device from driver,
> + * otherwise KIQ is hanging when binding back
> + */
> + if (!adev->in_gpu_reset && !adev->gfx.in_suspend) {
> + soc15_grbm_select(adev, adev->gfx.kiq.ring.me,
> + adev->gfx.kiq.ring.pipe,
> + adev->gfx.kiq.ring.queue, 0);
> + gfx_v9_0_kiq_fini_register(&adev->gfx.kiq.ring);
> + soc15_grbm_select(adev, 0, 0, 0, 0);
> + }
> +
> gfx_v9_0_cp_enable(adev, false);
> gfx_v9_0_rlc_stop(adev);
>
> --
> 2.7.4
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2018-04-02 14:00 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz follow: Atom feed
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2018-03-28 12:37 [PATCH] drm/amdgpu: Fix KIQ hang on bare metal for device unbind/bind back Andrey Grodzovsky
[not found] ` <1522240658-2648-1-git-send-email-andrey.grodzovsky-5C7GfCeVMHo@public.gmane.org>
2018-03-28 14:09 ` Alex Deucher
2018-03-31 11:05 ` Liu, Monk
[not found] ` <BLUPR12MB044980331171FE27298FD39684A00-7LeqcoF/hwpTIQvHjXdJlwdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
2018-04-02 13:57 ` Andrey Grodzovsky
2018-03-31 11:09 ` Liu, Monk
[not found] ` <BLUPR12MB0449BA46452663601FC2959984A00-7LeqcoF/hwpTIQvHjXdJlwdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
2018-04-02 14:00 ` Andrey Grodzovsky
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