* [PATCH v2 1/6] drm/amd/pm: Update metrics tbl struct for smu_v_13.0.6
@ 2025-01-22 9:55 Asad Kamal
2025-01-22 9:55 ` [PATCH v2 2/6] drm/amd/pm: Add metrics table header for smu_v13_0_12 Asad Kamal
` (4 more replies)
0 siblings, 5 replies; 8+ messages in thread
From: Asad Kamal @ 2025-01-22 9:55 UTC (permalink / raw)
To: amd-gfx, lijo.lazar
Cc: le.ma, hawking.zhang, shiwu.zhang, Asad.Kamal, alexander.deucher
Update metrics table struct name for smu_v_13.0.6 and keep
it as version
Signed-off-by: Asad Kamal <asad.kamal@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
---
.../pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h | 6 +-
.../drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c | 56 +++++++++----------
2 files changed, 32 insertions(+), 30 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h
index 274b3e1cc4fb..ff9f7d4e11df 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h
@@ -129,6 +129,7 @@ typedef enum {
#define SMU_METRICS_TABLE_VERSION 0xF
+// Unified metrics table for smu_v13_0_6
typedef struct __attribute__((packed, aligned(4))) {
uint32_t AccumulationCounter;
@@ -241,8 +242,9 @@ typedef struct __attribute__((packed, aligned(4))) {
//Total App Clock Counter
uint64_t GfxclkBelowHostLimitAcc[8];
-} MetricsTableX_t;
+} MetricsTableV0_t;
+// Metrics table for smu_v13_0_6 APUS
typedef struct __attribute__((packed, aligned(4))) {
uint32_t AccumulationCounter;
@@ -333,7 +335,7 @@ typedef struct __attribute__((packed, aligned(4))) {
// VCN/JPEG ACTIVITY
uint32_t VcnBusy[4];
uint32_t JpegBusy[32];
-} MetricsTableA_t;
+} MetricsTableV1_t;
#define SMU_VF_METRICS_TABLE_VERSION 0x5
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
index fa11e30bff24..dbfab5d503b5 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
@@ -273,7 +273,7 @@ struct PPTable_t {
#define SMUQ10_FRAC(x) ((x) & 0x3ff)
#define SMUQ10_ROUND(x) ((SMUQ10_TO_UINT(x)) + ((SMUQ10_FRAC(x)) >= 0x200))
#define GET_METRIC_FIELD(field, flag) ((flag) ?\
- (metrics_a->field) : (metrics_x->field))
+ (metrics_v1->field) : (metrics_v0->field))
struct smu_v13_0_6_dpm_map {
enum smu_clk_type clk_type;
@@ -514,7 +514,7 @@ static int smu_v13_0_6_tables_init(struct smu_context *smu)
PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS,
- max(sizeof(MetricsTableX_t), sizeof(MetricsTableA_t)),
+ max(sizeof(MetricsTableV0_t), sizeof(MetricsTableV1_t)),
PAGE_SIZE,
AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT);
@@ -522,8 +522,8 @@ static int smu_v13_0_6_tables_init(struct smu_context *smu)
PAGE_SIZE,
AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT);
- smu_table->metrics_table = kzalloc(max(sizeof(MetricsTableX_t),
- sizeof(MetricsTableA_t)), GFP_KERNEL);
+ smu_table->metrics_table = kzalloc(max(sizeof(MetricsTableV0_t),
+ sizeof(MetricsTableV1_t)), GFP_KERNEL);
if (!smu_table->metrics_table)
return -ENOMEM;
smu_table->metrics_time = 0;
@@ -753,8 +753,8 @@ static ssize_t smu_v13_0_6_get_pm_metrics(struct smu_context *smu,
static int smu_v13_0_6_setup_driver_pptable(struct smu_context *smu)
{
struct smu_table_context *smu_table = &smu->smu_table;
- MetricsTableX_t *metrics_x = (MetricsTableX_t *)smu_table->metrics_table;
- MetricsTableA_t *metrics_a = (MetricsTableA_t *)smu_table->metrics_table;
+ MetricsTableV0_t *metrics_v0 = (MetricsTableV0_t *)smu_table->metrics_table;
+ MetricsTableV1_t *metrics_v1 = (MetricsTableV1_t *)smu_table->metrics_table;
struct PPTable_t *pptable =
(struct PPTable_t *)smu_table->driver_pptable;
bool flag = !smu_v13_0_6_cap_supported(smu, SMU_CAP(UNI_METRICS));
@@ -1128,8 +1128,8 @@ static int smu_v13_0_6_get_smu_metrics_data(struct smu_context *smu,
uint32_t *value)
{
struct smu_table_context *smu_table = &smu->smu_table;
- MetricsTableX_t *metrics_x = (MetricsTableX_t *)smu_table->metrics_table;
- MetricsTableA_t *metrics_a = (MetricsTableA_t *)smu_table->metrics_table;
+ MetricsTableV0_t *metrics_v0 = (MetricsTableV0_t *)smu_table->metrics_table;
+ MetricsTableV1_t *metrics_v1 = (MetricsTableV1_t *)smu_table->metrics_table;
bool flag = !smu_v13_0_6_cap_supported(smu, SMU_CAP(UNI_METRICS));
struct amdgpu_device *adev = smu->adev;
int ret = 0;
@@ -2479,21 +2479,21 @@ static ssize_t smu_v13_0_6_get_gpu_metrics(struct smu_context *smu, void **table
bool flag = !smu_v13_0_6_cap_supported(smu, SMU_CAP(UNI_METRICS));
int ret = 0, xcc_id, inst, i, j, k, idx;
struct amdgpu_device *adev = smu->adev;
- MetricsTableX_t *metrics_x;
- MetricsTableA_t *metrics_a;
+ MetricsTableV0_t *metrics_v0;
+ MetricsTableV1_t *metrics_v1;
struct amdgpu_xcp *xcp;
u16 link_width_level;
u32 inst_mask;
bool per_inst;
- metrics_x = kzalloc(max(sizeof(MetricsTableX_t), sizeof(MetricsTableA_t)), GFP_KERNEL);
- ret = smu_v13_0_6_get_metrics_table(smu, metrics_x, true);
+ metrics_v0 = kzalloc(max(sizeof(MetricsTableV0_t), sizeof(MetricsTableV1_t)), GFP_KERNEL);
+ ret = smu_v13_0_6_get_metrics_table(smu, metrics_v0, true);
if (ret) {
- kfree(metrics_x);
+ kfree(metrics_v0);
return ret;
}
- metrics_a = (MetricsTableA_t *)metrics_x;
+ metrics_v1 = (MetricsTableV1_t *)metrics_v0;
smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 7);
@@ -2559,9 +2559,9 @@ static ssize_t smu_v13_0_6_get_gpu_metrics(struct smu_context *smu, void **table
* for pf from registers
*/
if (smu_v13_0_6_cap_supported(smu, SMU_CAP(PCIE_METRICS))) {
- gpu_metrics->pcie_link_width = metrics_x->PCIeLinkWidth;
+ gpu_metrics->pcie_link_width = metrics_v0->PCIeLinkWidth;
gpu_metrics->pcie_link_speed =
- pcie_gen_to_speed(metrics_x->PCIeLinkSpeed);
+ pcie_gen_to_speed(metrics_v0->PCIeLinkSpeed);
} else if (!amdgpu_sriov_vf(adev)) {
link_width_level = smu_v13_0_6_get_current_pcie_link_width_level(smu);
if (link_width_level > MAX_LINK_WIDTH)
@@ -2574,22 +2574,22 @@ static ssize_t smu_v13_0_6_get_gpu_metrics(struct smu_context *smu, void **table
}
gpu_metrics->pcie_bandwidth_acc =
- SMUQ10_ROUND(metrics_x->PcieBandwidthAcc[0]);
+ SMUQ10_ROUND(metrics_v0->PcieBandwidthAcc[0]);
gpu_metrics->pcie_bandwidth_inst =
- SMUQ10_ROUND(metrics_x->PcieBandwidth[0]);
+ SMUQ10_ROUND(metrics_v0->PcieBandwidth[0]);
gpu_metrics->pcie_l0_to_recov_count_acc =
- metrics_x->PCIeL0ToRecoveryCountAcc;
+ metrics_v0->PCIeL0ToRecoveryCountAcc;
gpu_metrics->pcie_replay_count_acc =
- metrics_x->PCIenReplayAAcc;
+ metrics_v0->PCIenReplayAAcc;
gpu_metrics->pcie_replay_rover_count_acc =
- metrics_x->PCIenReplayARolloverCountAcc;
+ metrics_v0->PCIenReplayARolloverCountAcc;
gpu_metrics->pcie_nak_sent_count_acc =
- metrics_x->PCIeNAKSentCountAcc;
+ metrics_v0->PCIeNAKSentCountAcc;
gpu_metrics->pcie_nak_rcvd_count_acc =
- metrics_x->PCIeNAKReceivedCountAcc;
+ metrics_v0->PCIeNAKReceivedCountAcc;
if (smu_v13_0_6_cap_supported(smu, SMU_CAP(OTHER_END_METRICS)))
gpu_metrics->pcie_lc_perf_other_end_recovery =
- metrics_x->PCIeOtherEndRecoveryAcc;
+ metrics_v0->PCIeOtherEndRecoveryAcc;
}
@@ -2639,14 +2639,14 @@ static ssize_t smu_v13_0_6_get_gpu_metrics(struct smu_context *smu, void **table
for_each_inst(k, inst_mask) {
inst = GET_INST(GC, k);
gpu_metrics->xcp_stats[i].gfx_busy_inst[idx] =
- SMUQ10_ROUND(metrics_x->GfxBusy[inst]);
+ SMUQ10_ROUND(metrics_v0->GfxBusy[inst]);
gpu_metrics->xcp_stats[i].gfx_busy_acc[idx] =
- SMUQ10_ROUND(metrics_x->GfxBusyAcc[inst]);
+ SMUQ10_ROUND(metrics_v0->GfxBusyAcc[inst]);
if (smu_v13_0_6_cap_supported(
smu, SMU_CAP(HST_LIMIT_METRICS)))
gpu_metrics->xcp_stats[i].gfx_below_host_limit_acc[idx] =
- SMUQ10_ROUND(metrics_x->GfxclkBelowHostLimitAcc
+ SMUQ10_ROUND(metrics_v0->GfxclkBelowHostLimitAcc
[inst]);
idx++;
}
@@ -2659,7 +2659,7 @@ static ssize_t smu_v13_0_6_get_gpu_metrics(struct smu_context *smu, void **table
gpu_metrics->firmware_timestamp = GET_METRIC_FIELD(Timestamp, flag);
*table = (void *)gpu_metrics;
- kfree(metrics_x);
+ kfree(metrics_v0);
return sizeof(*gpu_metrics);
}
--
2.46.0
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH v2 2/6] drm/amd/pm: Add metrics table header for smu_v13_0_12
2025-01-22 9:55 [PATCH v2 1/6] drm/amd/pm: Update metrics tbl struct for smu_v_13.0.6 Asad Kamal
@ 2025-01-22 9:55 ` Asad Kamal
2025-01-22 9:55 ` [PATCH v2 3/6] drm/amd/pm: Add SMUv13.0.12 PPT interface Asad Kamal
` (3 subsequent siblings)
4 siblings, 0 replies; 8+ messages in thread
From: Asad Kamal @ 2025-01-22 9:55 UTC (permalink / raw)
To: amd-gfx, lijo.lazar
Cc: le.ma, hawking.zhang, shiwu.zhang, Asad.Kamal, alexander.deucher
Add metrics table header for smu_v13_0_12 as metrics version V2
Signed-off-by: Asad Kamal <asad.kamal@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
---
.../pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h | 109 ++++++++++++++++++
1 file changed, 109 insertions(+)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h
index ff9f7d4e11df..f8ed45857878 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h
@@ -337,6 +337,115 @@ typedef struct __attribute__((packed, aligned(4))) {
uint32_t JpegBusy[32];
} MetricsTableV1_t;
+// Metrics table for smu_v13_0_12
+typedef struct __attribute__((packed, aligned(4))) {
+ uint64_t AccumulationCounter;
+
+ //TEMPERATURE
+ uint32_t MaxSocketTemperature;
+ uint32_t MaxVrTemperature;
+ uint32_t MaxHbmTemperature;
+ uint64_t MaxSocketTemperatureAcc;
+ uint64_t MaxVrTemperatureAcc;
+ uint64_t MaxHbmTemperatureAcc;
+
+ //POWER
+ uint32_t SocketPowerLimit;
+ uint32_t MaxSocketPowerLimit;
+ uint32_t SocketPower;
+
+ //ENERGY
+ uint64_t Timestamp;
+ uint64_t SocketEnergyAcc;
+ uint64_t CcdEnergyAcc;
+ uint64_t XcdEnergyAcc;
+ uint64_t AidEnergyAcc;
+ uint64_t HbmEnergyAcc;
+
+ //FREQUENCY
+ uint32_t GfxclkFrequencyLimit;
+ uint32_t FclkFrequency;
+ uint32_t UclkFrequency;
+ uint32_t SocclkFrequency[4];
+ uint32_t VclkFrequency[4];
+ uint32_t DclkFrequency[4];
+ uint32_t LclkFrequency[4];
+ uint64_t GfxclkFrequencyAcc[8];
+
+ //FREQUENCY RANGE
+ uint32_t MaxGfxclkFrequency;
+ uint32_t MinGfxclkFrequency;
+ uint32_t FclkFrequencyTable[4];
+ uint32_t UclkFrequencyTable[4];
+ uint32_t SocclkFrequencyTable[4];
+ uint32_t VclkFrequencyTable[4];
+ uint32_t DclkFrequencyTable[4];
+ uint32_t LclkFrequencyTable[4];
+ uint32_t MaxLclkDpmRange;
+ uint32_t MinLclkDpmRange;
+
+ //XGMI
+ uint32_t XgmiWidth;
+ uint32_t XgmiBitrate;
+ uint64_t XgmiReadBandwidthAcc[8];
+ uint64_t XgmiWriteBandwidthAcc[8];
+
+ //ACTIVITY
+ uint32_t SocketGfxBusy;
+ uint32_t DramBandwidthUtilization;
+ uint64_t SocketC0ResidencyAcc;
+ uint64_t SocketGfxBusyAcc;
+ uint64_t DramBandwidthAcc;
+ uint32_t MaxDramBandwidth;
+ uint64_t DramBandwidthUtilizationAcc;
+ uint64_t PcieBandwidthAcc[4];
+
+ //THROTTLERS
+ uint32_t ProchotResidencyAcc;
+ uint32_t PptResidencyAcc;
+ uint32_t SocketThmResidencyAcc;
+ uint32_t VrThmResidencyAcc;
+ uint32_t HbmThmResidencyAcc;
+ uint32_t GfxLockXCDMak;
+
+ // New Items at end to maintain driver compatibility
+ uint32_t GfxclkFrequency[8];
+
+ //PSNs
+ uint64_t PublicSerialNumber_AID[4];
+ uint64_t PublicSerialNumber_XCD[8];
+
+ //XGMI Data tranfser size
+ uint64_t XgmiReadDataSizeAcc[8];//in KByte
+ uint64_t XgmiWriteDataSizeAcc[8];//in KByte
+
+ //PCIE BW Data and error count
+ uint32_t PcieBandwidth[4];
+ uint32_t PCIeL0ToRecoveryCountAcc; // The Pcie counter itself is accumulated
+ uint32_t PCIenReplayAAcc; // The Pcie counter itself is accumulated
+ uint32_t PCIenReplayARolloverCountAcc; // The Pcie counter itself is accumulated
+ uint32_t PCIeNAKSentCountAcc; // The Pcie counter itself is accumulated
+ uint32_t PCIeNAKReceivedCountAcc; // The Pcie counter itself is accumulated
+
+ // VCN/JPEG ACTIVITY
+ uint32_t VcnBusy[4];
+ uint32_t JpegBusy[32];
+
+ // PCIE LINK Speed and width
+ uint32_t PCIeLinkSpeed;
+ uint32_t PCIeLinkWidth;
+
+ // PER XCD ACTIVITY
+ uint32_t GfxBusy[8];
+ uint64_t GfxBusyAcc[8];
+
+ //PCIE BW Data and error count
+ uint32_t PCIeOtherEndRecoveryAcc; // The Pcie counter itself is accumulated
+
+ //Total App Clock Counter
+ uint64_t GfxclkBelowHostLimitAcc[8];
+} MetricsTableV2_t;
+
#define SMU_VF_METRICS_TABLE_VERSION 0x5
typedef struct __attribute__((packed, aligned(4))) {
--
2.46.0
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH v2 3/6] drm/amd/pm: Add SMUv13.0.12 PPT interface
2025-01-22 9:55 [PATCH v2 1/6] drm/amd/pm: Update metrics tbl struct for smu_v_13.0.6 Asad Kamal
2025-01-22 9:55 ` [PATCH v2 2/6] drm/amd/pm: Add metrics table header for smu_v13_0_12 Asad Kamal
@ 2025-01-22 9:55 ` Asad Kamal
2025-01-22 9:55 ` [PATCH v2 4/6] drm/amd/pm: Add metrics support for smuv13.0.12 Asad Kamal
` (2 subsequent siblings)
4 siblings, 0 replies; 8+ messages in thread
From: Asad Kamal @ 2025-01-22 9:55 UTC (permalink / raw)
To: amd-gfx, lijo.lazar
Cc: le.ma, hawking.zhang, shiwu.zhang, Asad.Kamal, alexander.deucher
Add SMUv13.0.12 PPT interface to fetch dpm features
Signed-off-by: Asad Kamal <asad.kamal@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
---
.../pm/swsmu/inc/pmfw_if/smu_v13_0_12_pmfw.h | 138 ++++++++++++++++++
drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h | 2 +
drivers/gpu/drm/amd/pm/swsmu/smu13/Makefile | 2 +-
.../drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c | 101 +++++++++++++
.../drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c | 6 +-
5 files changed, 247 insertions(+), 2 deletions(-)
create mode 100644 drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_12_pmfw.h
create mode 100644 drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c
diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_12_pmfw.h b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_12_pmfw.h
new file mode 100644
index 000000000000..4a1256d29d62
--- /dev/null
+++ b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_12_pmfw.h
@@ -0,0 +1,138 @@
+/*
+ * Copyright 2021 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+#ifndef SMU_13_0_12_PMFW_H
+#define SMU_13_0_12_PMFW_H
+
+#define NUM_VCLK_DPM_LEVELS 4
+#define NUM_DCLK_DPM_LEVELS 4
+#define NUM_SOCCLK_DPM_LEVELS 4
+#define NUM_LCLK_DPM_LEVELS 4
+#define NUM_UCLK_DPM_LEVELS 4
+#define NUM_FCLK_DPM_LEVELS 4
+#define NUM_XGMI_DPM_LEVELS 2
+#define NUM_CXL_BITRATES 4
+#define NUM_PCIE_BITRATES 4
+#define NUM_XGMI_BITRATES 4
+#define NUM_XGMI_WIDTHS 3
+#define NUM_TDP_GROUPS 4
+#define NUM_SOC_P2S_TABLES 6
+#define NUM_GFX_P2S_TABLES 8
+#define NUM_PSM_DIDT_THRESHOLDS 3
+
+typedef enum {
+/*0*/ FEATURE_DATA_CALCULATION = 0,
+/*1*/ FEATURE_DPM_FCLK = 1,
+/*2*/ FEATURE_DPM_GFXCLK = 2,
+/*3*/ FEATURE_DPM_LCLK = 3,
+/*4*/ FEATURE_DPM_SOCCLK = 4,
+/*5*/ FEATURE_DPM_UCLK = 5,
+/*6*/ FEATURE_DPM_VCN = 6,
+/*7*/ FEATURE_DPM_XGMI = 7,
+/*8*/ FEATURE_DS_FCLK = 8,
+/*9*/ FEATURE_DS_GFXCLK = 9,
+/*10*/ FEATURE_DS_LCLK = 10,
+/*11*/ FEATURE_DS_MP0CLK = 11,
+/*12*/ FEATURE_DS_MP1CLK = 12,
+/*13*/ FEATURE_DS_MPIOCLK = 13,
+/*14*/ FEATURE_DS_SOCCLK = 14,
+/*15*/ FEATURE_DS_VCN = 15,
+/*16*/ FEATURE_APCC_DFLL = 16,
+/*17*/ FEATURE_APCC_PLUS = 17,
+/*18*/ FEATURE_PPT = 18,
+/*19*/ FEATURE_TDC = 19,
+/*20*/ FEATURE_THERMAL = 20,
+/*21*/ FEATURE_SOC_PCC = 21,
+/*22*/ FEATURE_PROCHOT = 22,
+/*23*/ FEATURE_FDD_AID_HBM = 23,
+/*24*/ FEATURE_FDD_AID_SOC = 24,
+/*25*/ FEATURE_FDD_XCD_EDC = 25,
+/*26*/ FEATURE_FDD_XCD_XVMIN = 26,
+/*27*/ FEATURE_FW_CTF = 27,
+/*28*/ FEATURE_SMU_CG = 28,
+/*29*/ FEATURE_PSI7 = 29,
+/*30*/ FEATURE_XGMI_PER_LINK_PWR_DOWN = 30,
+/*31*/ FEATURE_SOC_DC_RTC = 31,
+/*32*/ FEATURE_GFX_DC_RTC = 32,
+/*33*/ FEATURE_DVM_MIN_PSM = 33,
+/*34*/ FEATURE_PRC = 34,
+/*35*/ FEATURE_PSM_SQ_THROTTLER = 35,
+/*36*/ FEATURE_PIT = 36,
+/*37*/ FEATURE_DVO = 37,
+/*38*/ FEATURE_XVMINORPSM_CLKSTOP_DS = 38,
+
+/*39*/ NUM_FEATURES = 39
+} FEATURE_LIST_e;
+
+//enum for MPIO PCIe gen speed msgs
+typedef enum {
+ PCIE_LINK_SPEED_INDEX_TABLE_GEN1,
+ PCIE_LINK_SPEED_INDEX_TABLE_GEN2,
+ PCIE_LINK_SPEED_INDEX_TABLE_GEN3,
+ PCIE_LINK_SPEED_INDEX_TABLE_GEN4,
+ PCIE_LINK_SPEED_INDEX_TABLE_GEN4_ESM,
+ PCIE_LINK_SPEED_INDEX_TABLE_GEN5,
+ PCIE_LINK_SPEED_INDEX_TABLE_COUNT
+} PCIE_LINK_SPEED_INDEX_TABLE_e;
+
+typedef enum {
+ GFX_GUARDBAND_OFFSET_0,
+ GFX_GUARDBAND_OFFSET_1,
+ GFX_GUARDBAND_OFFSET_2,
+ GFX_GUARDBAND_OFFSET_3,
+ GFX_GUARDBAND_OFFSET_4,
+ GFX_GUARDBAND_OFFSET_5,
+ GFX_GUARDBAND_OFFSET_6,
+ GFX_GUARDBAND_OFFSET_7,
+ GFX_GUARDBAND_OFFSET_COUNT
+} GFX_GUARDBAND_OFFSET_e;
+
+typedef enum {
+ GFX_DVM_MARGINHI_0,
+ GFX_DVM_MARGINHI_1,
+ GFX_DVM_MARGINHI_2,
+ GFX_DVM_MARGINHI_3,
+ GFX_DVM_MARGINHI_4,
+ GFX_DVM_MARGINHI_5,
+ GFX_DVM_MARGINHI_6,
+ GFX_DVM_MARGINHI_7,
+ GFX_DVM_MARGINLO_0,
+ GFX_DVM_MARGINLO_1,
+ GFX_DVM_MARGINLO_2,
+ GFX_DVM_MARGINLO_3,
+ GFX_DVM_MARGINLO_4,
+ GFX_DVM_MARGINLO_5,
+ GFX_DVM_MARGINLO_6,
+ GFX_DVM_MARGINLO_7,
+ GFX_DVM_MARGIN_COUNT
+} GFX_DVM_MARGIN_e;
+
+#define SMU_VF_METRICS_TABLE_VERSION 0x3
+
+typedef struct __attribute__((packed, aligned(4))) {
+ uint32_t AccumulationCounter;
+ uint32_t InstGfxclk_TargFreq;
+ uint64_t AccGfxclk_TargFreq;
+ uint64_t AccGfxRsmuDpm_Busy;
+} VfMetricsTable_t;
+
+#endif
diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h
index 8d4a96e23326..31166974746f 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h
@@ -306,5 +306,7 @@ int smu_v13_0_get_boot_freq_by_index(struct smu_context *smu,
uint32_t *value);
void smu_v13_0_interrupt_work(struct smu_context *smu);
+bool smu_v13_0_12_is_dpm_running(struct smu_context *smu);
+extern const struct cmn2asic_mapping smu_v13_0_12_feature_mask_map[];
#endif
#endif
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/Makefile b/drivers/gpu/drm/amd/pm/swsmu/smu13/Makefile
index 7f3493b6c53c..51f1fa9789ab 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/Makefile
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/Makefile
@@ -24,7 +24,7 @@
# It provides the smu management services for the driver.
SMU13_MGR = smu_v13_0.o aldebaran_ppt.o yellow_carp_ppt.o smu_v13_0_0_ppt.o smu_v13_0_4_ppt.o \
- smu_v13_0_5_ppt.o smu_v13_0_7_ppt.o smu_v13_0_6_ppt.o
+ smu_v13_0_5_ppt.o smu_v13_0_7_ppt.o smu_v13_0_6_ppt.o smu_v13_0_12_ppt.o
AMD_SWSMU_SMU13MGR = $(addprefix $(AMD_SWSMU_PATH)/smu13/,$(SMU13_MGR))
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c
new file mode 100644
index 000000000000..86852e738837
--- /dev/null
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_12_ppt.c
@@ -0,0 +1,101 @@
+/*
+ * Copyright 2021 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#define SWSMU_CODE_LAYER_L2
+
+#include <linux/firmware.h>
+#include "amdgpu.h"
+#include "amdgpu_smu.h"
+#include "smu_v13_0_12_pmfw.h"
+#include "smu_v13_0_6_ppt.h"
+#include "smu_v13_0.h"
+#include "amdgpu_xgmi.h"
+#include <linux/pci.h>
+#include "smu_cmn.h"
+
+#undef MP1_Public
+#undef smnMP1_FIRMWARE_FLAGS
+
+/*
+ * DO NOT use these for err/warn/info/debug messages.
+ * Use dev_err, dev_warn, dev_info and dev_dbg instead.
+ * They are more MGPU friendly.
+ */
+#undef pr_err
+#undef pr_warn
+#undef pr_info
+#undef pr_debug
+
+#define SMU_13_0_12_FEA_MAP(smu_feature, smu_13_0_12_feature) \
+ [smu_feature] = { 1, (smu_13_0_12_feature) }
+
+#define FEATURE_MASK(feature) (1ULL << feature)
+#define SMC_DPM_FEATURE \
+ (FEATURE_MASK(FEATURE_DATA_CALCULATION) | \
+ FEATURE_MASK(FEATURE_DPM_GFXCLK) | FEATURE_MASK(FEATURE_DPM_FCLK))
+
+const struct cmn2asic_mapping smu_v13_0_12_feature_mask_map[SMU_FEATURE_COUNT] = {
+ SMU_13_0_12_FEA_MAP(SMU_FEATURE_DATA_CALCULATIONS_BIT, FEATURE_DATA_CALCULATION),
+ SMU_13_0_12_FEA_MAP(SMU_FEATURE_DPM_GFXCLK_BIT, FEATURE_DPM_GFXCLK),
+ SMU_13_0_12_FEA_MAP(SMU_FEATURE_DPM_FCLK_BIT, FEATURE_DPM_FCLK),
+ SMU_13_0_12_FEA_MAP(SMU_FEATURE_DS_GFXCLK_BIT, FEATURE_DS_GFXCLK),
+ SMU_13_0_12_FEA_MAP(SMU_FEATURE_DS_SOCCLK_BIT, FEATURE_DS_SOCCLK),
+ SMU_13_0_12_FEA_MAP(SMU_FEATURE_DS_LCLK_BIT, FEATURE_DS_LCLK),
+ SMU_13_0_12_FEA_MAP(SMU_FEATURE_DS_FCLK_BIT, FEATURE_DS_FCLK),
+ SMU_13_0_12_FEA_MAP(SMU_FEATURE_PPT_BIT, FEATURE_PPT),
+ SMU_13_0_12_FEA_MAP(SMU_FEATURE_TDC_BIT, FEATURE_TDC),
+ SMU_13_0_12_FEA_MAP(SMU_FEATURE_APCC_DFLL_BIT, FEATURE_APCC_DFLL),
+ SMU_13_0_12_FEA_MAP(SMU_FEATURE_MP1_CG_BIT, FEATURE_SMU_CG),
+ SMU_13_0_12_FEA_MAP(SMU_FEATURE_FW_CTF_BIT, FEATURE_FW_CTF),
+ SMU_13_0_12_FEA_MAP(SMU_FEATURE_THERMAL_BIT, FEATURE_THERMAL),
+ SMU_13_0_12_FEA_MAP(SMU_FEATURE_SOC_PCC_BIT, FEATURE_SOC_PCC),
+ SMU_13_0_12_FEA_MAP(SMU_FEATURE_XGMI_PER_LINK_PWR_DWN_BIT, FEATURE_XGMI_PER_LINK_PWR_DOWN),
+};
+
+static int smu_v13_0_12_get_enabled_mask(struct smu_context *smu,
+ uint64_t *feature_mask)
+{
+ int ret;
+
+ ret = smu_cmn_get_enabled_mask(smu, feature_mask);
+
+ if (ret == -EIO) {
+ *feature_mask = 0;
+ ret = 0;
+ }
+
+ return ret;
+}
+
+bool smu_v13_0_12_is_dpm_running(struct smu_context *smu)
+{
+ int ret;
+ uint64_t feature_enabled;
+
+ ret = smu_v13_0_12_get_enabled_mask(smu, &feature_enabled);
+
+ if (ret)
+ return false;
+
+ return !!(feature_enabled & SMC_DPM_FEATURE);
+}
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
index dbfab5d503b5..d4a159bb5a65 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
@@ -2193,6 +2193,9 @@ static bool smu_v13_0_6_is_dpm_running(struct smu_context *smu)
int ret;
uint64_t feature_enabled;
+ if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 12))
+ return smu_v13_0_12_is_dpm_running(smu);
+
ret = smu_v13_0_6_get_enabled_mask(smu, &feature_enabled);
if (ret)
@@ -3564,7 +3567,8 @@ void smu_v13_0_6_set_ppt_funcs(struct smu_context *smu)
smu->ppt_funcs = &smu_v13_0_6_ppt_funcs;
smu->message_map = smu_v13_0_6_message_map;
smu->clock_map = smu_v13_0_6_clk_map;
- smu->feature_map = smu_v13_0_6_feature_mask_map;
+ smu->feature_map = (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 12)) ?
+ smu_v13_0_12_feature_mask_map : smu_v13_0_6_feature_mask_map;
smu->table_map = smu_v13_0_6_table_map;
smu->smc_driver_if_version = SMU13_0_6_DRIVER_IF_VERSION;
smu->smc_fw_caps |= SMU_FW_CAP_RAS_PRI;
--
2.46.0
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH v2 4/6] drm/amd/pm: Add metrics support for smuv13.0.12
2025-01-22 9:55 [PATCH v2 1/6] drm/amd/pm: Update metrics tbl struct for smu_v_13.0.6 Asad Kamal
2025-01-22 9:55 ` [PATCH v2 2/6] drm/amd/pm: Add metrics table header for smu_v13_0_12 Asad Kamal
2025-01-22 9:55 ` [PATCH v2 3/6] drm/amd/pm: Add SMUv13.0.12 PPT interface Asad Kamal
@ 2025-01-22 9:55 ` Asad Kamal
2025-01-22 11:23 ` Lazar, Lijo
2025-01-22 9:55 ` [PATCH v2 5/6] drm/amd/pm: Skip showing MCLK_OD level Asad Kamal
2025-01-22 9:55 ` [PATCH v2 6/6] drm/amd/pm: Update pm attr for gc_9_5_0 Asad Kamal
4 siblings, 1 reply; 8+ messages in thread
From: Asad Kamal @ 2025-01-22 9:55 UTC (permalink / raw)
To: amd-gfx, lijo.lazar
Cc: le.ma, hawking.zhang, shiwu.zhang, Asad.Kamal, alexander.deucher
Add metrics table support for smuv13.0.12 to
fetch data from metrics version v2
v2: Update get metric field and get metric size macro (Lijo)
Signed-off-by: Asad Kamal <asad.kamal@amd.com>
---
.../drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c | 186 ++++++++++--------
.../drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.h | 8 +
2 files changed, 113 insertions(+), 81 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
index d4a159bb5a65..72c18b1635c0 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
@@ -105,7 +105,6 @@ MODULE_FIRMWARE("amdgpu/smu_13_0_14.bin");
enum smu_v13_0_6_caps {
SMU_CAP(DPM),
- SMU_CAP(UNI_METRICS),
SMU_CAP(DPM_POLICY),
SMU_CAP(OTHER_END_METRICS),
SMU_CAP(SET_UCLK_MAX),
@@ -272,8 +271,13 @@ struct PPTable_t {
#define SMUQ10_TO_UINT(x) ((x) >> 10)
#define SMUQ10_FRAC(x) ((x) & 0x3ff)
#define SMUQ10_ROUND(x) ((SMUQ10_TO_UINT(x)) + ((SMUQ10_FRAC(x)) >= 0x200))
-#define GET_METRIC_FIELD(field, flag) ((flag) ?\
- (metrics_v1->field) : (metrics_v0->field))
+#define GET_GPU_METRIC_FIELD(field, version) ((version == METRICS_VERSION_V0) ?\
+ (metrics_v0->field) : (metrics_v2->field))
+#define GET_METRIC_FIELD(field, version) ((version == METRICS_VERSION_V1) ?\
+ (metrics_v1->field) : GET_GPU_METRIC_FIELD(field, version))
+#define METRICS_TABLE_SIZE (max3(sizeof(MetricsTableV0_t),\
+ sizeof(MetricsTableV1_t),\
+ sizeof(MetricsTableV2_t)))
struct smu_v13_0_6_dpm_map {
enum smu_clk_type clk_type;
@@ -282,6 +286,18 @@ struct smu_v13_0_6_dpm_map {
uint32_t *freq_table;
};
+static inline int smu_v13_0_6_get_metrics_version(struct smu_context *smu)
+{
+ if ((smu->adev->flags & AMD_IS_APU) &&
+ smu->smc_fw_version <= 0x4556900)
+ return METRICS_VERSION_V1;
+ else if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) ==
+ IP_VERSION(13, 0, 12))
+ return METRICS_VERSION_V2;
+
+ return METRICS_VERSION_V0;
+}
+
static inline void smu_v13_0_6_cap_set(struct smu_context *smu,
enum smu_v13_0_6_caps cap)
{
@@ -309,7 +325,6 @@ static inline bool smu_v13_0_6_cap_supported(struct smu_context *smu,
static void smu_v13_0_14_init_caps(struct smu_context *smu)
{
enum smu_v13_0_6_caps default_cap_list[] = { SMU_CAP(DPM),
- SMU_CAP(UNI_METRICS),
SMU_CAP(SET_UCLK_MAX),
SMU_CAP(DPM_POLICY),
SMU_CAP(PCIE_METRICS),
@@ -335,12 +350,14 @@ static void smu_v13_0_14_init_caps(struct smu_context *smu)
static void smu_v13_0_12_init_caps(struct smu_context *smu)
{
enum smu_v13_0_6_caps default_cap_list[] = { SMU_CAP(DPM),
- SMU_CAP(UNI_METRICS),
SMU_CAP(PCIE_METRICS),
SMU_CAP(CTF_LIMIT),
SMU_CAP(MCA_DEBUG_MODE),
SMU_CAP(RMA_MSG),
- SMU_CAP(ACA_SYND) };
+ SMU_CAP(ACA_SYND),
+ SMU_CAP(OTHER_END_METRICS),
+ SMU_CAP(HST_LIMIT_METRICS),
+ SMU_CAP(PER_INST_METRICS) };
uint32_t fw_ver = smu->smc_fw_version;
for (int i = 0; i < ARRAY_SIZE(default_cap_list); i++)
@@ -356,7 +373,6 @@ static void smu_v13_0_12_init_caps(struct smu_context *smu)
static void smu_v13_0_6_init_caps(struct smu_context *smu)
{
enum smu_v13_0_6_caps default_cap_list[] = { SMU_CAP(DPM),
- SMU_CAP(UNI_METRICS),
SMU_CAP(SET_UCLK_MAX),
SMU_CAP(DPM_POLICY),
SMU_CAP(PCIE_METRICS),
@@ -382,8 +398,6 @@ static void smu_v13_0_6_init_caps(struct smu_context *smu)
smu_v13_0_6_cap_clear(smu, SMU_CAP(RMA_MSG));
smu_v13_0_6_cap_clear(smu, SMU_CAP(ACA_SYND));
- if (fw_ver <= 0x4556900)
- smu_v13_0_6_cap_clear(smu, SMU_CAP(UNI_METRICS));
if (fw_ver >= 0x04556F00)
smu_v13_0_6_cap_set(smu, SMU_CAP(HST_LIMIT_METRICS));
if (fw_ver >= 0x04556A00)
@@ -514,7 +528,7 @@ static int smu_v13_0_6_tables_init(struct smu_context *smu)
PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS,
- max(sizeof(MetricsTableV0_t), sizeof(MetricsTableV1_t)),
+ METRICS_TABLE_SIZE,
PAGE_SIZE,
AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT);
@@ -522,8 +536,7 @@ static int smu_v13_0_6_tables_init(struct smu_context *smu)
PAGE_SIZE,
AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT);
- smu_table->metrics_table = kzalloc(max(sizeof(MetricsTableV0_t),
- sizeof(MetricsTableV1_t)), GFP_KERNEL);
+ smu_table->metrics_table = kzalloc(METRICS_TABLE_SIZE, GFP_KERNEL);
if (!smu_table->metrics_table)
return -ENOMEM;
smu_table->metrics_time = 0;
@@ -755,9 +768,10 @@ static int smu_v13_0_6_setup_driver_pptable(struct smu_context *smu)
struct smu_table_context *smu_table = &smu->smu_table;
MetricsTableV0_t *metrics_v0 = (MetricsTableV0_t *)smu_table->metrics_table;
MetricsTableV1_t *metrics_v1 = (MetricsTableV1_t *)smu_table->metrics_table;
+ MetricsTableV2_t *metrics_v2 = (MetricsTableV2_t *)smu_table->metrics_table;
struct PPTable_t *pptable =
(struct PPTable_t *)smu_table->driver_pptable;
- bool flag = !smu_v13_0_6_cap_supported(smu, SMU_CAP(UNI_METRICS));
+ int version = smu_v13_0_6_get_metrics_version(smu);
int ret, i, retry = 100;
uint32_t table_version;
@@ -769,7 +783,7 @@ static int smu_v13_0_6_setup_driver_pptable(struct smu_context *smu)
return ret;
/* Ensure that metrics have been updated */
- if (GET_METRIC_FIELD(AccumulationCounter, flag))
+ if (GET_METRIC_FIELD(AccumulationCounter, version))
break;
usleep_range(1000, 1100);
@@ -786,29 +800,30 @@ static int smu_v13_0_6_setup_driver_pptable(struct smu_context *smu)
table_version;
pptable->MaxSocketPowerLimit =
- SMUQ10_ROUND(GET_METRIC_FIELD(MaxSocketPowerLimit, flag));
+ SMUQ10_ROUND(GET_METRIC_FIELD(MaxSocketPowerLimit, version));
pptable->MaxGfxclkFrequency =
- SMUQ10_ROUND(GET_METRIC_FIELD(MaxGfxclkFrequency, flag));
+ SMUQ10_ROUND(GET_METRIC_FIELD(MaxGfxclkFrequency, version));
pptable->MinGfxclkFrequency =
- SMUQ10_ROUND(GET_METRIC_FIELD(MinGfxclkFrequency, flag));
+ SMUQ10_ROUND(GET_METRIC_FIELD(MinGfxclkFrequency, version));
for (i = 0; i < 4; ++i) {
pptable->FclkFrequencyTable[i] =
- SMUQ10_ROUND(GET_METRIC_FIELD(FclkFrequencyTable, flag)[i]);
+ SMUQ10_ROUND(GET_METRIC_FIELD(FclkFrequencyTable, version)[i]);
pptable->UclkFrequencyTable[i] =
- SMUQ10_ROUND(GET_METRIC_FIELD(UclkFrequencyTable, flag)[i]);
+ SMUQ10_ROUND(GET_METRIC_FIELD(UclkFrequencyTable, version)[i]);
pptable->SocclkFrequencyTable[i] = SMUQ10_ROUND(
- GET_METRIC_FIELD(SocclkFrequencyTable, flag)[i]);
+ GET_METRIC_FIELD(SocclkFrequencyTable, version)[i]);
pptable->VclkFrequencyTable[i] =
- SMUQ10_ROUND(GET_METRIC_FIELD(VclkFrequencyTable, flag)[i]);
+ SMUQ10_ROUND(GET_METRIC_FIELD(VclkFrequencyTable, version)[i]);
pptable->DclkFrequencyTable[i] =
- SMUQ10_ROUND(GET_METRIC_FIELD(DclkFrequencyTable, flag)[i]);
+ SMUQ10_ROUND(GET_METRIC_FIELD(DclkFrequencyTable, version)[i]);
pptable->LclkFrequencyTable[i] =
- SMUQ10_ROUND(GET_METRIC_FIELD(LclkFrequencyTable, flag)[i]);
+ SMUQ10_ROUND(GET_METRIC_FIELD(LclkFrequencyTable, version)[i]);
}
/* use AID0 serial number by default */
- pptable->PublicSerialNumber_AID = GET_METRIC_FIELD(PublicSerialNumber_AID, flag)[0];
+ pptable->PublicSerialNumber_AID =
+ GET_METRIC_FIELD(PublicSerialNumber_AID, version)[0];
pptable->Init = true;
}
@@ -1130,7 +1145,8 @@ static int smu_v13_0_6_get_smu_metrics_data(struct smu_context *smu,
struct smu_table_context *smu_table = &smu->smu_table;
MetricsTableV0_t *metrics_v0 = (MetricsTableV0_t *)smu_table->metrics_table;
MetricsTableV1_t *metrics_v1 = (MetricsTableV1_t *)smu_table->metrics_table;
- bool flag = !smu_v13_0_6_cap_supported(smu, SMU_CAP(UNI_METRICS));
+ MetricsTableV2_t *metrics_v2 = (MetricsTableV2_t *)smu_table->metrics_table;
+ int version = smu_v13_0_6_get_metrics_version(smu);
struct amdgpu_device *adev = smu->adev;
int ret = 0;
int xcc_id;
@@ -1145,50 +1161,50 @@ static int smu_v13_0_6_get_smu_metrics_data(struct smu_context *smu,
case METRICS_AVERAGE_GFXCLK:
if (smu_v13_0_6_cap_supported(smu, SMU_CAP(DPM))) {
xcc_id = GET_INST(GC, 0);
- *value = SMUQ10_ROUND(GET_METRIC_FIELD(GfxclkFrequency, flag)[xcc_id]);
+ *value = SMUQ10_ROUND(GET_METRIC_FIELD(GfxclkFrequency, version)[xcc_id]);
} else {
*value = 0;
}
break;
case METRICS_CURR_SOCCLK:
case METRICS_AVERAGE_SOCCLK:
- *value = SMUQ10_ROUND(GET_METRIC_FIELD(SocclkFrequency, flag)[0]);
+ *value = SMUQ10_ROUND(GET_METRIC_FIELD(SocclkFrequency, version)[0]);
break;
case METRICS_CURR_UCLK:
case METRICS_AVERAGE_UCLK:
- *value = SMUQ10_ROUND(GET_METRIC_FIELD(UclkFrequency, flag));
+ *value = SMUQ10_ROUND(GET_METRIC_FIELD(UclkFrequency, version));
break;
case METRICS_CURR_VCLK:
- *value = SMUQ10_ROUND(GET_METRIC_FIELD(VclkFrequency, flag)[0]);
+ *value = SMUQ10_ROUND(GET_METRIC_FIELD(VclkFrequency, version)[0]);
break;
case METRICS_CURR_DCLK:
- *value = SMUQ10_ROUND(GET_METRIC_FIELD(DclkFrequency, flag)[0]);
+ *value = SMUQ10_ROUND(GET_METRIC_FIELD(DclkFrequency, version)[0]);
break;
case METRICS_CURR_FCLK:
- *value = SMUQ10_ROUND(GET_METRIC_FIELD(FclkFrequency, flag));
+ *value = SMUQ10_ROUND(GET_METRIC_FIELD(FclkFrequency, version));
break;
case METRICS_AVERAGE_GFXACTIVITY:
- *value = SMUQ10_ROUND(GET_METRIC_FIELD(SocketGfxBusy, flag));
+ *value = SMUQ10_ROUND(GET_METRIC_FIELD(SocketGfxBusy, version));
break;
case METRICS_AVERAGE_MEMACTIVITY:
- *value = SMUQ10_ROUND(GET_METRIC_FIELD(DramBandwidthUtilization, flag));
+ *value = SMUQ10_ROUND(GET_METRIC_FIELD(DramBandwidthUtilization, version));
break;
case METRICS_CURR_SOCKETPOWER:
- *value = SMUQ10_ROUND(GET_METRIC_FIELD(SocketPower, flag)) << 8;
+ *value = SMUQ10_ROUND(GET_METRIC_FIELD(SocketPower, version)) << 8;
break;
case METRICS_TEMPERATURE_HOTSPOT:
- *value = SMUQ10_ROUND(GET_METRIC_FIELD(MaxSocketTemperature, flag)) *
+ *value = SMUQ10_ROUND(GET_METRIC_FIELD(MaxSocketTemperature, version)) *
SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
break;
case METRICS_TEMPERATURE_MEM:
- *value = SMUQ10_ROUND(GET_METRIC_FIELD(MaxHbmTemperature, flag)) *
+ *value = SMUQ10_ROUND(GET_METRIC_FIELD(MaxHbmTemperature, version)) *
SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
break;
/* This is the max of all VRs and not just SOC VR.
* No need to define another data type for the same.
*/
case METRICS_TEMPERATURE_VRSOC:
- *value = SMUQ10_ROUND(GET_METRIC_FIELD(MaxVrTemperature, flag)) *
+ *value = SMUQ10_ROUND(GET_METRIC_FIELD(MaxVrTemperature, version)) *
SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
break;
default:
@@ -2479,17 +2495,18 @@ static ssize_t smu_v13_0_6_get_gpu_metrics(struct smu_context *smu, void **table
struct smu_table_context *smu_table = &smu->smu_table;
struct gpu_metrics_v1_7 *gpu_metrics =
(struct gpu_metrics_v1_7 *)smu_table->gpu_metrics_table;
- bool flag = !smu_v13_0_6_cap_supported(smu, SMU_CAP(UNI_METRICS));
+ int version = smu_v13_0_6_get_metrics_version(smu);
int ret = 0, xcc_id, inst, i, j, k, idx;
struct amdgpu_device *adev = smu->adev;
MetricsTableV0_t *metrics_v0;
MetricsTableV1_t *metrics_v1;
+ MetricsTableV2_t *metrics_v2;
struct amdgpu_xcp *xcp;
u16 link_width_level;
u32 inst_mask;
bool per_inst;
- metrics_v0 = kzalloc(max(sizeof(MetricsTableV0_t), sizeof(MetricsTableV1_t)), GFP_KERNEL);
+ metrics_v0 = kzalloc(METRICS_TABLE_SIZE, GFP_KERNEL);
ret = smu_v13_0_6_get_metrics_table(smu, metrics_v0, true);
if (ret) {
kfree(metrics_v0);
@@ -2497,64 +2514,69 @@ static ssize_t smu_v13_0_6_get_gpu_metrics(struct smu_context *smu, void **table
}
metrics_v1 = (MetricsTableV1_t *)metrics_v0;
+ metrics_v2 = (MetricsTableV2_t *)metrics_v0;
smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 7);
gpu_metrics->temperature_hotspot =
- SMUQ10_ROUND(GET_METRIC_FIELD(MaxSocketTemperature, flag));
+ SMUQ10_ROUND(GET_METRIC_FIELD(MaxSocketTemperature, version));
/* Individual HBM stack temperature is not reported */
gpu_metrics->temperature_mem =
- SMUQ10_ROUND(GET_METRIC_FIELD(MaxHbmTemperature, flag));
+ SMUQ10_ROUND(GET_METRIC_FIELD(MaxHbmTemperature, version));
/* Reports max temperature of all voltage rails */
gpu_metrics->temperature_vrsoc =
- SMUQ10_ROUND(GET_METRIC_FIELD(MaxVrTemperature, flag));
+ SMUQ10_ROUND(GET_METRIC_FIELD(MaxVrTemperature, version));
gpu_metrics->average_gfx_activity =
- SMUQ10_ROUND(GET_METRIC_FIELD(SocketGfxBusy, flag));
+ SMUQ10_ROUND(GET_METRIC_FIELD(SocketGfxBusy, version));
gpu_metrics->average_umc_activity =
- SMUQ10_ROUND(GET_METRIC_FIELD(DramBandwidthUtilization, flag));
+ SMUQ10_ROUND(GET_METRIC_FIELD(DramBandwidthUtilization, version));
gpu_metrics->mem_max_bandwidth =
- SMUQ10_ROUND(GET_METRIC_FIELD(MaxDramBandwidth, flag));
+ SMUQ10_ROUND(GET_METRIC_FIELD(MaxDramBandwidth, version));
gpu_metrics->curr_socket_power =
- SMUQ10_ROUND(GET_METRIC_FIELD(SocketPower, flag));
+ SMUQ10_ROUND(GET_METRIC_FIELD(SocketPower, version));
/* Energy counter reported in 15.259uJ (2^-16) units */
- gpu_metrics->energy_accumulator = GET_METRIC_FIELD(SocketEnergyAcc, flag);
+ gpu_metrics->energy_accumulator = GET_METRIC_FIELD(SocketEnergyAcc, version);
for (i = 0; i < MAX_GFX_CLKS; i++) {
xcc_id = GET_INST(GC, i);
if (xcc_id >= 0)
gpu_metrics->current_gfxclk[i] =
- SMUQ10_ROUND(GET_METRIC_FIELD(GfxclkFrequency, flag)[xcc_id]);
+ SMUQ10_ROUND(GET_METRIC_FIELD(GfxclkFrequency, version)[xcc_id]);
if (i < MAX_CLKS) {
gpu_metrics->current_socclk[i] =
- SMUQ10_ROUND(GET_METRIC_FIELD(SocclkFrequency, flag)[i]);
+ SMUQ10_ROUND(GET_METRIC_FIELD(SocclkFrequency, version)[i]);
inst = GET_INST(VCN, i);
if (inst >= 0) {
gpu_metrics->current_vclk0[i] =
- SMUQ10_ROUND(GET_METRIC_FIELD(VclkFrequency, flag)[inst]);
+ SMUQ10_ROUND(GET_METRIC_FIELD(VclkFrequency,
+ version)[inst]);
gpu_metrics->current_dclk0[i] =
- SMUQ10_ROUND(GET_METRIC_FIELD(DclkFrequency, flag)[inst]);
+ SMUQ10_ROUND(GET_METRIC_FIELD(DclkFrequency,
+ version)[inst]);
}
}
}
- gpu_metrics->current_uclk = SMUQ10_ROUND(GET_METRIC_FIELD(UclkFrequency, flag));
+ gpu_metrics->current_uclk = SMUQ10_ROUND(GET_METRIC_FIELD(UclkFrequency, version));
/* Total accumulated cycle counter */
- gpu_metrics->accumulation_counter = GET_METRIC_FIELD(AccumulationCounter, flag);
+ gpu_metrics->accumulation_counter = GET_METRIC_FIELD(AccumulationCounter, version);
/* Accumulated throttler residencies */
- gpu_metrics->prochot_residency_acc = GET_METRIC_FIELD(ProchotResidencyAcc, flag);
- gpu_metrics->ppt_residency_acc = GET_METRIC_FIELD(PptResidencyAcc, flag);
- gpu_metrics->socket_thm_residency_acc = GET_METRIC_FIELD(SocketThmResidencyAcc, flag);
- gpu_metrics->vr_thm_residency_acc = GET_METRIC_FIELD(VrThmResidencyAcc, flag);
- gpu_metrics->hbm_thm_residency_acc = GET_METRIC_FIELD(HbmThmResidencyAcc, flag);
+ gpu_metrics->prochot_residency_acc = GET_METRIC_FIELD(ProchotResidencyAcc, version);
+ gpu_metrics->ppt_residency_acc = GET_METRIC_FIELD(PptResidencyAcc, version);
+ gpu_metrics->socket_thm_residency_acc = GET_METRIC_FIELD(SocketThmResidencyAcc, version);
+ gpu_metrics->vr_thm_residency_acc = GET_METRIC_FIELD(VrThmResidencyAcc, version);
+ gpu_metrics->hbm_thm_residency_acc =
+ GET_METRIC_FIELD(HbmThmResidencyAcc, version);
/* Clock Lock Status. Each bit corresponds to each GFXCLK instance */
- gpu_metrics->gfxclk_lock_status = GET_METRIC_FIELD(GfxLockXCDMak, flag) >> GET_INST(GC, 0);
+ gpu_metrics->gfxclk_lock_status = GET_METRIC_FIELD(GfxLockXCDMak,
+ version) >> GET_INST(GC, 0);
if (!(adev->flags & AMD_IS_APU)) {
/*Check smu version, PCIE link speed and width will be reported from pmfw metric
@@ -2562,9 +2584,9 @@ static ssize_t smu_v13_0_6_get_gpu_metrics(struct smu_context *smu, void **table
* for pf from registers
*/
if (smu_v13_0_6_cap_supported(smu, SMU_CAP(PCIE_METRICS))) {
- gpu_metrics->pcie_link_width = metrics_v0->PCIeLinkWidth;
+ gpu_metrics->pcie_link_width = GET_GPU_METRIC_FIELD(PCIeLinkWidth, version);
gpu_metrics->pcie_link_speed =
- pcie_gen_to_speed(metrics_v0->PCIeLinkSpeed);
+ pcie_gen_to_speed(GET_GPU_METRIC_FIELD(PCIeLinkSpeed, version));
} else if (!amdgpu_sriov_vf(adev)) {
link_width_level = smu_v13_0_6_get_current_pcie_link_width_level(smu);
if (link_width_level > MAX_LINK_WIDTH)
@@ -2577,37 +2599,37 @@ static ssize_t smu_v13_0_6_get_gpu_metrics(struct smu_context *smu, void **table
}
gpu_metrics->pcie_bandwidth_acc =
- SMUQ10_ROUND(metrics_v0->PcieBandwidthAcc[0]);
+ SMUQ10_ROUND(GET_GPU_METRIC_FIELD(PcieBandwidthAcc, version)[0]);
gpu_metrics->pcie_bandwidth_inst =
- SMUQ10_ROUND(metrics_v0->PcieBandwidth[0]);
+ SMUQ10_ROUND(GET_GPU_METRIC_FIELD(PcieBandwidth, version)[0]);
gpu_metrics->pcie_l0_to_recov_count_acc =
- metrics_v0->PCIeL0ToRecoveryCountAcc;
+ GET_GPU_METRIC_FIELD(PCIeL0ToRecoveryCountAcc, version);
gpu_metrics->pcie_replay_count_acc =
- metrics_v0->PCIenReplayAAcc;
+ GET_GPU_METRIC_FIELD(PCIenReplayAAcc, version);
gpu_metrics->pcie_replay_rover_count_acc =
- metrics_v0->PCIenReplayARolloverCountAcc;
+ GET_GPU_METRIC_FIELD(PCIenReplayARolloverCountAcc, version);
gpu_metrics->pcie_nak_sent_count_acc =
- metrics_v0->PCIeNAKSentCountAcc;
+ GET_GPU_METRIC_FIELD(PCIeNAKSentCountAcc, version);
gpu_metrics->pcie_nak_rcvd_count_acc =
- metrics_v0->PCIeNAKReceivedCountAcc;
+ GET_GPU_METRIC_FIELD(PCIeNAKReceivedCountAcc, version);
if (smu_v13_0_6_cap_supported(smu, SMU_CAP(OTHER_END_METRICS)))
gpu_metrics->pcie_lc_perf_other_end_recovery =
- metrics_v0->PCIeOtherEndRecoveryAcc;
+ GET_GPU_METRIC_FIELD(PCIeOtherEndRecoveryAcc, version);
}
gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
gpu_metrics->gfx_activity_acc =
- SMUQ10_ROUND(GET_METRIC_FIELD(SocketGfxBusyAcc, flag));
+ SMUQ10_ROUND(GET_METRIC_FIELD(SocketGfxBusyAcc, version));
gpu_metrics->mem_activity_acc =
- SMUQ10_ROUND(GET_METRIC_FIELD(DramBandwidthUtilizationAcc, flag));
+ SMUQ10_ROUND(GET_METRIC_FIELD(DramBandwidthUtilizationAcc, version));
for (i = 0; i < NUM_XGMI_LINKS; i++) {
gpu_metrics->xgmi_read_data_acc[i] =
- SMUQ10_ROUND(GET_METRIC_FIELD(XgmiReadDataSizeAcc, flag)[i]);
+ SMUQ10_ROUND(GET_METRIC_FIELD(XgmiReadDataSizeAcc, version)[i]);
gpu_metrics->xgmi_write_data_acc[i] =
- SMUQ10_ROUND(GET_METRIC_FIELD(XgmiWriteDataSizeAcc, flag)[i]);
+ SMUQ10_ROUND(GET_METRIC_FIELD(XgmiWriteDataSizeAcc, version)[i]);
ret = amdgpu_get_xgmi_link_status(adev, i);
if (ret >= 0)
gpu_metrics->xgmi_link_status[i] = ret;
@@ -2627,11 +2649,11 @@ static ssize_t smu_v13_0_6_get_gpu_metrics(struct smu_context *smu, void **table
for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) {
gpu_metrics->xcp_stats[i].jpeg_busy
[(idx * adev->jpeg.num_jpeg_rings) + j] =
- SMUQ10_ROUND(GET_METRIC_FIELD(JpegBusy, flag)
+ SMUQ10_ROUND(GET_METRIC_FIELD(JpegBusy, version)
[(inst * adev->jpeg.num_jpeg_rings) + j]);
}
gpu_metrics->xcp_stats[i].vcn_busy[idx] =
- SMUQ10_ROUND(GET_METRIC_FIELD(VcnBusy, flag)[inst]);
+ SMUQ10_ROUND(GET_METRIC_FIELD(VcnBusy, version)[inst]);
idx++;
}
@@ -2642,24 +2664,26 @@ static ssize_t smu_v13_0_6_get_gpu_metrics(struct smu_context *smu, void **table
for_each_inst(k, inst_mask) {
inst = GET_INST(GC, k);
gpu_metrics->xcp_stats[i].gfx_busy_inst[idx] =
- SMUQ10_ROUND(metrics_v0->GfxBusy[inst]);
+ SMUQ10_ROUND(GET_GPU_METRIC_FIELD(GfxBusy, version)[inst]);
gpu_metrics->xcp_stats[i].gfx_busy_acc[idx] =
- SMUQ10_ROUND(metrics_v0->GfxBusyAcc[inst]);
+ SMUQ10_ROUND(GET_GPU_METRIC_FIELD(GfxBusyAcc,
+ version)[inst]);
if (smu_v13_0_6_cap_supported(
smu, SMU_CAP(HST_LIMIT_METRICS)))
gpu_metrics->xcp_stats[i].gfx_below_host_limit_acc[idx] =
- SMUQ10_ROUND(metrics_v0->GfxclkBelowHostLimitAcc
+ SMUQ10_ROUND(GET_GPU_METRIC_FIELD
+ (GfxclkBelowHostLimitAcc, version)
[inst]);
idx++;
}
}
}
- gpu_metrics->xgmi_link_width = SMUQ10_ROUND(GET_METRIC_FIELD(XgmiWidth, flag));
- gpu_metrics->xgmi_link_speed = SMUQ10_ROUND(GET_METRIC_FIELD(XgmiBitrate, flag));
+ gpu_metrics->xgmi_link_width = SMUQ10_ROUND(GET_METRIC_FIELD(XgmiWidth, version));
+ gpu_metrics->xgmi_link_speed = SMUQ10_ROUND(GET_METRIC_FIELD(XgmiBitrate, version));
- gpu_metrics->firmware_timestamp = GET_METRIC_FIELD(Timestamp, flag);
+ gpu_metrics->firmware_timestamp = GET_METRIC_FIELD(Timestamp, version);
*table = (void *)gpu_metrics;
kfree(metrics_v0);
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.h b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.h
index f0fa42a645c0..717fe669882e 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.h
@@ -27,6 +27,14 @@
#define SMU_13_0_6_UMD_PSTATE_SOCCLK_LEVEL 0x4
#define SMU_13_0_6_UMD_PSTATE_MCLK_LEVEL 0x2
+typedef enum {
+/*0*/ METRICS_VERSION_V0 = 0,
+/*1*/ METRICS_VERSION_V1 = 1,
+/*2*/ METRICS_VERSION_V2 = 2,
+
+/*3*/ NUM_METRICS = 3
+} METRICS_LIST_e;
+
extern void smu_v13_0_6_set_ppt_funcs(struct smu_context *smu);
#endif
--
2.46.0
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH v2 5/6] drm/amd/pm: Skip showing MCLK_OD level
2025-01-22 9:55 [PATCH v2 1/6] drm/amd/pm: Update metrics tbl struct for smu_v_13.0.6 Asad Kamal
` (2 preceding siblings ...)
2025-01-22 9:55 ` [PATCH v2 4/6] drm/amd/pm: Add metrics support for smuv13.0.12 Asad Kamal
@ 2025-01-22 9:55 ` Asad Kamal
2025-01-22 9:55 ` [PATCH v2 6/6] drm/amd/pm: Update pm attr for gc_9_5_0 Asad Kamal
4 siblings, 0 replies; 8+ messages in thread
From: Asad Kamal @ 2025-01-22 9:55 UTC (permalink / raw)
To: amd-gfx, lijo.lazar
Cc: le.ma, hawking.zhang, shiwu.zhang, Asad.Kamal, alexander.deucher
Skip showing MCLK_OD level if setting UCLK MAX is not supported
Signed-off-by: Asad Kamal <asad.kamal@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
---
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
index 72c18b1635c0..cf313da88607 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
@@ -1368,6 +1368,9 @@ static int smu_v13_0_6_print_clk_levels(struct smu_context *smu,
break;
case SMU_OD_MCLK:
+ if (!smu_v13_0_6_cap_supported(smu, SMU_CAP(SET_UCLK_MAX)))
+ return 0;
+
size += sysfs_emit_at(buf, size, "%s:\n", "OD_MCLK");
size += sysfs_emit_at(buf, size, "0: %uMhz\n1: %uMhz\n",
pstate_table->uclk_pstate.curr.min,
--
2.46.0
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH v2 6/6] drm/amd/pm: Update pm attr for gc_9_5_0
2025-01-22 9:55 [PATCH v2 1/6] drm/amd/pm: Update metrics tbl struct for smu_v_13.0.6 Asad Kamal
` (3 preceding siblings ...)
2025-01-22 9:55 ` [PATCH v2 5/6] drm/amd/pm: Skip showing MCLK_OD level Asad Kamal
@ 2025-01-22 9:55 ` Asad Kamal
2025-01-24 6:39 ` Zhang, Hawking
4 siblings, 1 reply; 8+ messages in thread
From: Asad Kamal @ 2025-01-22 9:55 UTC (permalink / raw)
To: amd-gfx, lijo.lazar
Cc: le.ma, hawking.zhang, shiwu.zhang, Asad.Kamal, alexander.deucher
Update power management & clk attributes for gc_v_9_5_0
Signed-off-by: Asad Kamal <asad.kamal@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
---
drivers/gpu/drm/amd/pm/amdgpu_pm.c | 27 ++++++++++++++++++---------
1 file changed, 18 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
index e8ae7681bf0a..0aca0803514e 100644
--- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
@@ -2006,9 +2006,10 @@ static int pp_od_clk_voltage_attr_update(struct amdgpu_device *adev, struct amdg
return 0;
}
- /* Enable pp_od_clk_voltage node for gc 9.4.3 SRIOV/BM support */
+ /* Enable pp_od_clk_voltage node for gc 9.4.3, 9.4.4, 9.5.0 SRIOV/BM support */
if (gc_ver == IP_VERSION(9, 4, 3) ||
- gc_ver == IP_VERSION(9, 4, 4)) {
+ gc_ver == IP_VERSION(9, 4, 4) ||
+ gc_ver == IP_VERSION(9, 5, 0)) {
if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev))
*states = ATTR_STATE_UNSUPPORTED;
return 0;
@@ -2087,7 +2088,8 @@ static int pp_dpm_clk_default_attr_update(struct amdgpu_device *adev, struct amd
gc_ver == IP_VERSION(11, 0, 2) ||
gc_ver == IP_VERSION(11, 0, 3) ||
gc_ver == IP_VERSION(9, 4, 3) ||
- gc_ver == IP_VERSION(9, 4, 4)))
+ gc_ver == IP_VERSION(9, 4, 4) ||
+ gc_ver == IP_VERSION(9, 5, 0)))
*states = ATTR_STATE_UNSUPPORTED;
} else if (DEVICE_ATTR_IS(pp_dpm_vclk1)) {
if (!((gc_ver == IP_VERSION(10, 3, 1) ||
@@ -2109,7 +2111,8 @@ static int pp_dpm_clk_default_attr_update(struct amdgpu_device *adev, struct amd
gc_ver == IP_VERSION(11, 0, 2) ||
gc_ver == IP_VERSION(11, 0, 3) ||
gc_ver == IP_VERSION(9, 4, 3) ||
- gc_ver == IP_VERSION(9, 4, 4)))
+ gc_ver == IP_VERSION(9, 4, 4) ||
+ gc_ver == IP_VERSION(9, 5, 0)))
*states = ATTR_STATE_UNSUPPORTED;
} else if (DEVICE_ATTR_IS(pp_dpm_dclk1)) {
if (!((gc_ver == IP_VERSION(10, 3, 1) ||
@@ -2120,7 +2123,8 @@ static int pp_dpm_clk_default_attr_update(struct amdgpu_device *adev, struct amd
} else if (DEVICE_ATTR_IS(pp_dpm_pcie)) {
if (gc_ver == IP_VERSION(9, 4, 2) ||
gc_ver == IP_VERSION(9, 4, 3) ||
- gc_ver == IP_VERSION(9, 4, 4))
+ gc_ver == IP_VERSION(9, 4, 4) ||
+ gc_ver == IP_VERSION(9, 5, 0))
*states = ATTR_STATE_UNSUPPORTED;
}
@@ -2416,6 +2420,7 @@ static int default_attr_update(struct amdgpu_device *adev, struct amdgpu_device_
case IP_VERSION(9, 4, 2):
case IP_VERSION(9, 4, 3):
case IP_VERSION(9, 4, 4):
+ case IP_VERSION(9, 5, 0):
case IP_VERSION(10, 3, 0):
case IP_VERSION(11, 0, 0):
case IP_VERSION(11, 0, 1):
@@ -3530,7 +3535,8 @@ static umode_t hwmon_attributes_visible(struct kobject *kobj,
/* Skip crit temp on APU */
if ((((adev->flags & AMD_IS_APU) && (adev->family >= AMDGPU_FAMILY_CZ)) ||
- (gc_ver == IP_VERSION(9, 4, 3) || gc_ver == IP_VERSION(9, 4, 4))) &&
+ (gc_ver == IP_VERSION(9, 4, 3) || gc_ver == IP_VERSION(9, 4, 4) ||
+ gc_ver == IP_VERSION(9, 5, 0))) &&
(attr == &sensor_dev_attr_temp1_crit.dev_attr.attr ||
attr == &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr))
return 0;
@@ -3605,7 +3611,8 @@ static umode_t hwmon_attributes_visible(struct kobject *kobj,
if ((adev->family == AMDGPU_FAMILY_SI || /* not implemented yet */
adev->family == AMDGPU_FAMILY_KV || /* not implemented yet */
(gc_ver == IP_VERSION(9, 4, 3) ||
- gc_ver == IP_VERSION(9, 4, 4))) &&
+ gc_ver == IP_VERSION(9, 4, 4) ||
+ gc_ver == IP_VERSION(9, 5, 0))) &&
(attr == &sensor_dev_attr_in0_input.dev_attr.attr ||
attr == &sensor_dev_attr_in0_label.dev_attr.attr))
return 0;
@@ -3613,7 +3620,8 @@ static umode_t hwmon_attributes_visible(struct kobject *kobj,
/* only APUs other than gc 9,4,3 have vddnb */
if ((!(adev->flags & AMD_IS_APU) ||
(gc_ver == IP_VERSION(9, 4, 3) ||
- gc_ver == IP_VERSION(9, 4, 4))) &&
+ gc_ver == IP_VERSION(9, 4, 4) ||
+ gc_ver == IP_VERSION(9, 5, 0))) &&
(attr == &sensor_dev_attr_in1_input.dev_attr.attr ||
attr == &sensor_dev_attr_in1_label.dev_attr.attr))
return 0;
@@ -3636,7 +3644,8 @@ static umode_t hwmon_attributes_visible(struct kobject *kobj,
/* hotspot temperature for gc 9,4,3*/
if (gc_ver == IP_VERSION(9, 4, 3) ||
- gc_ver == IP_VERSION(9, 4, 4)) {
+ gc_ver == IP_VERSION(9, 4, 4) ||
+ gc_ver == IP_VERSION(9, 5, 0)) {
if (attr == &sensor_dev_attr_temp1_input.dev_attr.attr ||
attr == &sensor_dev_attr_temp1_emergency.dev_attr.attr ||
attr == &sensor_dev_attr_temp1_label.dev_attr.attr)
--
2.46.0
^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH v2 4/6] drm/amd/pm: Add metrics support for smuv13.0.12
2025-01-22 9:55 ` [PATCH v2 4/6] drm/amd/pm: Add metrics support for smuv13.0.12 Asad Kamal
@ 2025-01-22 11:23 ` Lazar, Lijo
0 siblings, 0 replies; 8+ messages in thread
From: Lazar, Lijo @ 2025-01-22 11:23 UTC (permalink / raw)
To: Asad Kamal, amd-gfx; +Cc: le.ma, hawking.zhang, shiwu.zhang, alexander.deucher
On 1/22/2025 3:25 PM, Asad Kamal wrote:
> Add metrics table support for smuv13.0.12 to
> fetch data from metrics version v2
>
> v2: Update get metric field and get metric size macro (Lijo)
>
> Signed-off-by: Asad Kamal <asad.kamal@amd.com>
Series is -
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Thanks,
Lijo
> ---
> .../drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c | 186 ++++++++++--------
> .../drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.h | 8 +
> 2 files changed, 113 insertions(+), 81 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
> index d4a159bb5a65..72c18b1635c0 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
> @@ -105,7 +105,6 @@ MODULE_FIRMWARE("amdgpu/smu_13_0_14.bin");
>
> enum smu_v13_0_6_caps {
> SMU_CAP(DPM),
> - SMU_CAP(UNI_METRICS),
> SMU_CAP(DPM_POLICY),
> SMU_CAP(OTHER_END_METRICS),
> SMU_CAP(SET_UCLK_MAX),
> @@ -272,8 +271,13 @@ struct PPTable_t {
> #define SMUQ10_TO_UINT(x) ((x) >> 10)
> #define SMUQ10_FRAC(x) ((x) & 0x3ff)
> #define SMUQ10_ROUND(x) ((SMUQ10_TO_UINT(x)) + ((SMUQ10_FRAC(x)) >= 0x200))
> -#define GET_METRIC_FIELD(field, flag) ((flag) ?\
> - (metrics_v1->field) : (metrics_v0->field))
> +#define GET_GPU_METRIC_FIELD(field, version) ((version == METRICS_VERSION_V0) ?\
> + (metrics_v0->field) : (metrics_v2->field))
> +#define GET_METRIC_FIELD(field, version) ((version == METRICS_VERSION_V1) ?\
> + (metrics_v1->field) : GET_GPU_METRIC_FIELD(field, version))
> +#define METRICS_TABLE_SIZE (max3(sizeof(MetricsTableV0_t),\
> + sizeof(MetricsTableV1_t),\
> + sizeof(MetricsTableV2_t)))
>
> struct smu_v13_0_6_dpm_map {
> enum smu_clk_type clk_type;
> @@ -282,6 +286,18 @@ struct smu_v13_0_6_dpm_map {
> uint32_t *freq_table;
> };
>
> +static inline int smu_v13_0_6_get_metrics_version(struct smu_context *smu)
> +{
> + if ((smu->adev->flags & AMD_IS_APU) &&
> + smu->smc_fw_version <= 0x4556900)
> + return METRICS_VERSION_V1;
> + else if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) ==
> + IP_VERSION(13, 0, 12))
> + return METRICS_VERSION_V2;
> +
> + return METRICS_VERSION_V0;
> +}
> +
> static inline void smu_v13_0_6_cap_set(struct smu_context *smu,
> enum smu_v13_0_6_caps cap)
> {
> @@ -309,7 +325,6 @@ static inline bool smu_v13_0_6_cap_supported(struct smu_context *smu,
> static void smu_v13_0_14_init_caps(struct smu_context *smu)
> {
> enum smu_v13_0_6_caps default_cap_list[] = { SMU_CAP(DPM),
> - SMU_CAP(UNI_METRICS),
> SMU_CAP(SET_UCLK_MAX),
> SMU_CAP(DPM_POLICY),
> SMU_CAP(PCIE_METRICS),
> @@ -335,12 +350,14 @@ static void smu_v13_0_14_init_caps(struct smu_context *smu)
> static void smu_v13_0_12_init_caps(struct smu_context *smu)
> {
> enum smu_v13_0_6_caps default_cap_list[] = { SMU_CAP(DPM),
> - SMU_CAP(UNI_METRICS),
> SMU_CAP(PCIE_METRICS),
> SMU_CAP(CTF_LIMIT),
> SMU_CAP(MCA_DEBUG_MODE),
> SMU_CAP(RMA_MSG),
> - SMU_CAP(ACA_SYND) };
> + SMU_CAP(ACA_SYND),
> + SMU_CAP(OTHER_END_METRICS),
> + SMU_CAP(HST_LIMIT_METRICS),
> + SMU_CAP(PER_INST_METRICS) };
> uint32_t fw_ver = smu->smc_fw_version;
>
> for (int i = 0; i < ARRAY_SIZE(default_cap_list); i++)
> @@ -356,7 +373,6 @@ static void smu_v13_0_12_init_caps(struct smu_context *smu)
> static void smu_v13_0_6_init_caps(struct smu_context *smu)
> {
> enum smu_v13_0_6_caps default_cap_list[] = { SMU_CAP(DPM),
> - SMU_CAP(UNI_METRICS),
> SMU_CAP(SET_UCLK_MAX),
> SMU_CAP(DPM_POLICY),
> SMU_CAP(PCIE_METRICS),
> @@ -382,8 +398,6 @@ static void smu_v13_0_6_init_caps(struct smu_context *smu)
> smu_v13_0_6_cap_clear(smu, SMU_CAP(RMA_MSG));
> smu_v13_0_6_cap_clear(smu, SMU_CAP(ACA_SYND));
>
> - if (fw_ver <= 0x4556900)
> - smu_v13_0_6_cap_clear(smu, SMU_CAP(UNI_METRICS));
> if (fw_ver >= 0x04556F00)
> smu_v13_0_6_cap_set(smu, SMU_CAP(HST_LIMIT_METRICS));
> if (fw_ver >= 0x04556A00)
> @@ -514,7 +528,7 @@ static int smu_v13_0_6_tables_init(struct smu_context *smu)
> PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
>
> SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS,
> - max(sizeof(MetricsTableV0_t), sizeof(MetricsTableV1_t)),
> + METRICS_TABLE_SIZE,
> PAGE_SIZE,
> AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT);
>
> @@ -522,8 +536,7 @@ static int smu_v13_0_6_tables_init(struct smu_context *smu)
> PAGE_SIZE,
> AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT);
>
> - smu_table->metrics_table = kzalloc(max(sizeof(MetricsTableV0_t),
> - sizeof(MetricsTableV1_t)), GFP_KERNEL);
> + smu_table->metrics_table = kzalloc(METRICS_TABLE_SIZE, GFP_KERNEL);
> if (!smu_table->metrics_table)
> return -ENOMEM;
> smu_table->metrics_time = 0;
> @@ -755,9 +768,10 @@ static int smu_v13_0_6_setup_driver_pptable(struct smu_context *smu)
> struct smu_table_context *smu_table = &smu->smu_table;
> MetricsTableV0_t *metrics_v0 = (MetricsTableV0_t *)smu_table->metrics_table;
> MetricsTableV1_t *metrics_v1 = (MetricsTableV1_t *)smu_table->metrics_table;
> + MetricsTableV2_t *metrics_v2 = (MetricsTableV2_t *)smu_table->metrics_table;
> struct PPTable_t *pptable =
> (struct PPTable_t *)smu_table->driver_pptable;
> - bool flag = !smu_v13_0_6_cap_supported(smu, SMU_CAP(UNI_METRICS));
> + int version = smu_v13_0_6_get_metrics_version(smu);
> int ret, i, retry = 100;
> uint32_t table_version;
>
> @@ -769,7 +783,7 @@ static int smu_v13_0_6_setup_driver_pptable(struct smu_context *smu)
> return ret;
>
> /* Ensure that metrics have been updated */
> - if (GET_METRIC_FIELD(AccumulationCounter, flag))
> + if (GET_METRIC_FIELD(AccumulationCounter, version))
> break;
>
> usleep_range(1000, 1100);
> @@ -786,29 +800,30 @@ static int smu_v13_0_6_setup_driver_pptable(struct smu_context *smu)
> table_version;
>
> pptable->MaxSocketPowerLimit =
> - SMUQ10_ROUND(GET_METRIC_FIELD(MaxSocketPowerLimit, flag));
> + SMUQ10_ROUND(GET_METRIC_FIELD(MaxSocketPowerLimit, version));
> pptable->MaxGfxclkFrequency =
> - SMUQ10_ROUND(GET_METRIC_FIELD(MaxGfxclkFrequency, flag));
> + SMUQ10_ROUND(GET_METRIC_FIELD(MaxGfxclkFrequency, version));
> pptable->MinGfxclkFrequency =
> - SMUQ10_ROUND(GET_METRIC_FIELD(MinGfxclkFrequency, flag));
> + SMUQ10_ROUND(GET_METRIC_FIELD(MinGfxclkFrequency, version));
>
> for (i = 0; i < 4; ++i) {
> pptable->FclkFrequencyTable[i] =
> - SMUQ10_ROUND(GET_METRIC_FIELD(FclkFrequencyTable, flag)[i]);
> + SMUQ10_ROUND(GET_METRIC_FIELD(FclkFrequencyTable, version)[i]);
> pptable->UclkFrequencyTable[i] =
> - SMUQ10_ROUND(GET_METRIC_FIELD(UclkFrequencyTable, flag)[i]);
> + SMUQ10_ROUND(GET_METRIC_FIELD(UclkFrequencyTable, version)[i]);
> pptable->SocclkFrequencyTable[i] = SMUQ10_ROUND(
> - GET_METRIC_FIELD(SocclkFrequencyTable, flag)[i]);
> + GET_METRIC_FIELD(SocclkFrequencyTable, version)[i]);
> pptable->VclkFrequencyTable[i] =
> - SMUQ10_ROUND(GET_METRIC_FIELD(VclkFrequencyTable, flag)[i]);
> + SMUQ10_ROUND(GET_METRIC_FIELD(VclkFrequencyTable, version)[i]);
> pptable->DclkFrequencyTable[i] =
> - SMUQ10_ROUND(GET_METRIC_FIELD(DclkFrequencyTable, flag)[i]);
> + SMUQ10_ROUND(GET_METRIC_FIELD(DclkFrequencyTable, version)[i]);
> pptable->LclkFrequencyTable[i] =
> - SMUQ10_ROUND(GET_METRIC_FIELD(LclkFrequencyTable, flag)[i]);
> + SMUQ10_ROUND(GET_METRIC_FIELD(LclkFrequencyTable, version)[i]);
> }
>
> /* use AID0 serial number by default */
> - pptable->PublicSerialNumber_AID = GET_METRIC_FIELD(PublicSerialNumber_AID, flag)[0];
> + pptable->PublicSerialNumber_AID =
> + GET_METRIC_FIELD(PublicSerialNumber_AID, version)[0];
>
> pptable->Init = true;
> }
> @@ -1130,7 +1145,8 @@ static int smu_v13_0_6_get_smu_metrics_data(struct smu_context *smu,
> struct smu_table_context *smu_table = &smu->smu_table;
> MetricsTableV0_t *metrics_v0 = (MetricsTableV0_t *)smu_table->metrics_table;
> MetricsTableV1_t *metrics_v1 = (MetricsTableV1_t *)smu_table->metrics_table;
> - bool flag = !smu_v13_0_6_cap_supported(smu, SMU_CAP(UNI_METRICS));
> + MetricsTableV2_t *metrics_v2 = (MetricsTableV2_t *)smu_table->metrics_table;
> + int version = smu_v13_0_6_get_metrics_version(smu);
> struct amdgpu_device *adev = smu->adev;
> int ret = 0;
> int xcc_id;
> @@ -1145,50 +1161,50 @@ static int smu_v13_0_6_get_smu_metrics_data(struct smu_context *smu,
> case METRICS_AVERAGE_GFXCLK:
> if (smu_v13_0_6_cap_supported(smu, SMU_CAP(DPM))) {
> xcc_id = GET_INST(GC, 0);
> - *value = SMUQ10_ROUND(GET_METRIC_FIELD(GfxclkFrequency, flag)[xcc_id]);
> + *value = SMUQ10_ROUND(GET_METRIC_FIELD(GfxclkFrequency, version)[xcc_id]);
> } else {
> *value = 0;
> }
> break;
> case METRICS_CURR_SOCCLK:
> case METRICS_AVERAGE_SOCCLK:
> - *value = SMUQ10_ROUND(GET_METRIC_FIELD(SocclkFrequency, flag)[0]);
> + *value = SMUQ10_ROUND(GET_METRIC_FIELD(SocclkFrequency, version)[0]);
> break;
> case METRICS_CURR_UCLK:
> case METRICS_AVERAGE_UCLK:
> - *value = SMUQ10_ROUND(GET_METRIC_FIELD(UclkFrequency, flag));
> + *value = SMUQ10_ROUND(GET_METRIC_FIELD(UclkFrequency, version));
> break;
> case METRICS_CURR_VCLK:
> - *value = SMUQ10_ROUND(GET_METRIC_FIELD(VclkFrequency, flag)[0]);
> + *value = SMUQ10_ROUND(GET_METRIC_FIELD(VclkFrequency, version)[0]);
> break;
> case METRICS_CURR_DCLK:
> - *value = SMUQ10_ROUND(GET_METRIC_FIELD(DclkFrequency, flag)[0]);
> + *value = SMUQ10_ROUND(GET_METRIC_FIELD(DclkFrequency, version)[0]);
> break;
> case METRICS_CURR_FCLK:
> - *value = SMUQ10_ROUND(GET_METRIC_FIELD(FclkFrequency, flag));
> + *value = SMUQ10_ROUND(GET_METRIC_FIELD(FclkFrequency, version));
> break;
> case METRICS_AVERAGE_GFXACTIVITY:
> - *value = SMUQ10_ROUND(GET_METRIC_FIELD(SocketGfxBusy, flag));
> + *value = SMUQ10_ROUND(GET_METRIC_FIELD(SocketGfxBusy, version));
> break;
> case METRICS_AVERAGE_MEMACTIVITY:
> - *value = SMUQ10_ROUND(GET_METRIC_FIELD(DramBandwidthUtilization, flag));
> + *value = SMUQ10_ROUND(GET_METRIC_FIELD(DramBandwidthUtilization, version));
> break;
> case METRICS_CURR_SOCKETPOWER:
> - *value = SMUQ10_ROUND(GET_METRIC_FIELD(SocketPower, flag)) << 8;
> + *value = SMUQ10_ROUND(GET_METRIC_FIELD(SocketPower, version)) << 8;
> break;
> case METRICS_TEMPERATURE_HOTSPOT:
> - *value = SMUQ10_ROUND(GET_METRIC_FIELD(MaxSocketTemperature, flag)) *
> + *value = SMUQ10_ROUND(GET_METRIC_FIELD(MaxSocketTemperature, version)) *
> SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
> break;
> case METRICS_TEMPERATURE_MEM:
> - *value = SMUQ10_ROUND(GET_METRIC_FIELD(MaxHbmTemperature, flag)) *
> + *value = SMUQ10_ROUND(GET_METRIC_FIELD(MaxHbmTemperature, version)) *
> SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
> break;
> /* This is the max of all VRs and not just SOC VR.
> * No need to define another data type for the same.
> */
> case METRICS_TEMPERATURE_VRSOC:
> - *value = SMUQ10_ROUND(GET_METRIC_FIELD(MaxVrTemperature, flag)) *
> + *value = SMUQ10_ROUND(GET_METRIC_FIELD(MaxVrTemperature, version)) *
> SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
> break;
> default:
> @@ -2479,17 +2495,18 @@ static ssize_t smu_v13_0_6_get_gpu_metrics(struct smu_context *smu, void **table
> struct smu_table_context *smu_table = &smu->smu_table;
> struct gpu_metrics_v1_7 *gpu_metrics =
> (struct gpu_metrics_v1_7 *)smu_table->gpu_metrics_table;
> - bool flag = !smu_v13_0_6_cap_supported(smu, SMU_CAP(UNI_METRICS));
> + int version = smu_v13_0_6_get_metrics_version(smu);
> int ret = 0, xcc_id, inst, i, j, k, idx;
> struct amdgpu_device *adev = smu->adev;
> MetricsTableV0_t *metrics_v0;
> MetricsTableV1_t *metrics_v1;
> + MetricsTableV2_t *metrics_v2;
> struct amdgpu_xcp *xcp;
> u16 link_width_level;
> u32 inst_mask;
> bool per_inst;
>
> - metrics_v0 = kzalloc(max(sizeof(MetricsTableV0_t), sizeof(MetricsTableV1_t)), GFP_KERNEL);
> + metrics_v0 = kzalloc(METRICS_TABLE_SIZE, GFP_KERNEL);
> ret = smu_v13_0_6_get_metrics_table(smu, metrics_v0, true);
> if (ret) {
> kfree(metrics_v0);
> @@ -2497,64 +2514,69 @@ static ssize_t smu_v13_0_6_get_gpu_metrics(struct smu_context *smu, void **table
> }
>
> metrics_v1 = (MetricsTableV1_t *)metrics_v0;
> + metrics_v2 = (MetricsTableV2_t *)metrics_v0;
>
> smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 7);
>
> gpu_metrics->temperature_hotspot =
> - SMUQ10_ROUND(GET_METRIC_FIELD(MaxSocketTemperature, flag));
> + SMUQ10_ROUND(GET_METRIC_FIELD(MaxSocketTemperature, version));
> /* Individual HBM stack temperature is not reported */
> gpu_metrics->temperature_mem =
> - SMUQ10_ROUND(GET_METRIC_FIELD(MaxHbmTemperature, flag));
> + SMUQ10_ROUND(GET_METRIC_FIELD(MaxHbmTemperature, version));
> /* Reports max temperature of all voltage rails */
> gpu_metrics->temperature_vrsoc =
> - SMUQ10_ROUND(GET_METRIC_FIELD(MaxVrTemperature, flag));
> + SMUQ10_ROUND(GET_METRIC_FIELD(MaxVrTemperature, version));
>
> gpu_metrics->average_gfx_activity =
> - SMUQ10_ROUND(GET_METRIC_FIELD(SocketGfxBusy, flag));
> + SMUQ10_ROUND(GET_METRIC_FIELD(SocketGfxBusy, version));
> gpu_metrics->average_umc_activity =
> - SMUQ10_ROUND(GET_METRIC_FIELD(DramBandwidthUtilization, flag));
> + SMUQ10_ROUND(GET_METRIC_FIELD(DramBandwidthUtilization, version));
>
> gpu_metrics->mem_max_bandwidth =
> - SMUQ10_ROUND(GET_METRIC_FIELD(MaxDramBandwidth, flag));
> + SMUQ10_ROUND(GET_METRIC_FIELD(MaxDramBandwidth, version));
>
> gpu_metrics->curr_socket_power =
> - SMUQ10_ROUND(GET_METRIC_FIELD(SocketPower, flag));
> + SMUQ10_ROUND(GET_METRIC_FIELD(SocketPower, version));
> /* Energy counter reported in 15.259uJ (2^-16) units */
> - gpu_metrics->energy_accumulator = GET_METRIC_FIELD(SocketEnergyAcc, flag);
> + gpu_metrics->energy_accumulator = GET_METRIC_FIELD(SocketEnergyAcc, version);
>
> for (i = 0; i < MAX_GFX_CLKS; i++) {
> xcc_id = GET_INST(GC, i);
> if (xcc_id >= 0)
> gpu_metrics->current_gfxclk[i] =
> - SMUQ10_ROUND(GET_METRIC_FIELD(GfxclkFrequency, flag)[xcc_id]);
> + SMUQ10_ROUND(GET_METRIC_FIELD(GfxclkFrequency, version)[xcc_id]);
>
> if (i < MAX_CLKS) {
> gpu_metrics->current_socclk[i] =
> - SMUQ10_ROUND(GET_METRIC_FIELD(SocclkFrequency, flag)[i]);
> + SMUQ10_ROUND(GET_METRIC_FIELD(SocclkFrequency, version)[i]);
> inst = GET_INST(VCN, i);
> if (inst >= 0) {
> gpu_metrics->current_vclk0[i] =
> - SMUQ10_ROUND(GET_METRIC_FIELD(VclkFrequency, flag)[inst]);
> + SMUQ10_ROUND(GET_METRIC_FIELD(VclkFrequency,
> + version)[inst]);
> gpu_metrics->current_dclk0[i] =
> - SMUQ10_ROUND(GET_METRIC_FIELD(DclkFrequency, flag)[inst]);
> + SMUQ10_ROUND(GET_METRIC_FIELD(DclkFrequency,
> + version)[inst]);
> }
> }
> }
>
> - gpu_metrics->current_uclk = SMUQ10_ROUND(GET_METRIC_FIELD(UclkFrequency, flag));
> + gpu_metrics->current_uclk = SMUQ10_ROUND(GET_METRIC_FIELD(UclkFrequency, version));
>
> /* Total accumulated cycle counter */
> - gpu_metrics->accumulation_counter = GET_METRIC_FIELD(AccumulationCounter, flag);
> + gpu_metrics->accumulation_counter = GET_METRIC_FIELD(AccumulationCounter, version);
>
> /* Accumulated throttler residencies */
> - gpu_metrics->prochot_residency_acc = GET_METRIC_FIELD(ProchotResidencyAcc, flag);
> - gpu_metrics->ppt_residency_acc = GET_METRIC_FIELD(PptResidencyAcc, flag);
> - gpu_metrics->socket_thm_residency_acc = GET_METRIC_FIELD(SocketThmResidencyAcc, flag);
> - gpu_metrics->vr_thm_residency_acc = GET_METRIC_FIELD(VrThmResidencyAcc, flag);
> - gpu_metrics->hbm_thm_residency_acc = GET_METRIC_FIELD(HbmThmResidencyAcc, flag);
> + gpu_metrics->prochot_residency_acc = GET_METRIC_FIELD(ProchotResidencyAcc, version);
> + gpu_metrics->ppt_residency_acc = GET_METRIC_FIELD(PptResidencyAcc, version);
> + gpu_metrics->socket_thm_residency_acc = GET_METRIC_FIELD(SocketThmResidencyAcc, version);
> + gpu_metrics->vr_thm_residency_acc = GET_METRIC_FIELD(VrThmResidencyAcc, version);
> + gpu_metrics->hbm_thm_residency_acc =
> + GET_METRIC_FIELD(HbmThmResidencyAcc, version);
>
> /* Clock Lock Status. Each bit corresponds to each GFXCLK instance */
> - gpu_metrics->gfxclk_lock_status = GET_METRIC_FIELD(GfxLockXCDMak, flag) >> GET_INST(GC, 0);
> + gpu_metrics->gfxclk_lock_status = GET_METRIC_FIELD(GfxLockXCDMak,
> + version) >> GET_INST(GC, 0);
>
> if (!(adev->flags & AMD_IS_APU)) {
> /*Check smu version, PCIE link speed and width will be reported from pmfw metric
> @@ -2562,9 +2584,9 @@ static ssize_t smu_v13_0_6_get_gpu_metrics(struct smu_context *smu, void **table
> * for pf from registers
> */
> if (smu_v13_0_6_cap_supported(smu, SMU_CAP(PCIE_METRICS))) {
> - gpu_metrics->pcie_link_width = metrics_v0->PCIeLinkWidth;
> + gpu_metrics->pcie_link_width = GET_GPU_METRIC_FIELD(PCIeLinkWidth, version);
> gpu_metrics->pcie_link_speed =
> - pcie_gen_to_speed(metrics_v0->PCIeLinkSpeed);
> + pcie_gen_to_speed(GET_GPU_METRIC_FIELD(PCIeLinkSpeed, version));
> } else if (!amdgpu_sriov_vf(adev)) {
> link_width_level = smu_v13_0_6_get_current_pcie_link_width_level(smu);
> if (link_width_level > MAX_LINK_WIDTH)
> @@ -2577,37 +2599,37 @@ static ssize_t smu_v13_0_6_get_gpu_metrics(struct smu_context *smu, void **table
> }
>
> gpu_metrics->pcie_bandwidth_acc =
> - SMUQ10_ROUND(metrics_v0->PcieBandwidthAcc[0]);
> + SMUQ10_ROUND(GET_GPU_METRIC_FIELD(PcieBandwidthAcc, version)[0]);
> gpu_metrics->pcie_bandwidth_inst =
> - SMUQ10_ROUND(metrics_v0->PcieBandwidth[0]);
> + SMUQ10_ROUND(GET_GPU_METRIC_FIELD(PcieBandwidth, version)[0]);
> gpu_metrics->pcie_l0_to_recov_count_acc =
> - metrics_v0->PCIeL0ToRecoveryCountAcc;
> + GET_GPU_METRIC_FIELD(PCIeL0ToRecoveryCountAcc, version);
> gpu_metrics->pcie_replay_count_acc =
> - metrics_v0->PCIenReplayAAcc;
> + GET_GPU_METRIC_FIELD(PCIenReplayAAcc, version);
> gpu_metrics->pcie_replay_rover_count_acc =
> - metrics_v0->PCIenReplayARolloverCountAcc;
> + GET_GPU_METRIC_FIELD(PCIenReplayARolloverCountAcc, version);
> gpu_metrics->pcie_nak_sent_count_acc =
> - metrics_v0->PCIeNAKSentCountAcc;
> + GET_GPU_METRIC_FIELD(PCIeNAKSentCountAcc, version);
> gpu_metrics->pcie_nak_rcvd_count_acc =
> - metrics_v0->PCIeNAKReceivedCountAcc;
> + GET_GPU_METRIC_FIELD(PCIeNAKReceivedCountAcc, version);
> if (smu_v13_0_6_cap_supported(smu, SMU_CAP(OTHER_END_METRICS)))
> gpu_metrics->pcie_lc_perf_other_end_recovery =
> - metrics_v0->PCIeOtherEndRecoveryAcc;
> + GET_GPU_METRIC_FIELD(PCIeOtherEndRecoveryAcc, version);
>
> }
>
> gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
>
> gpu_metrics->gfx_activity_acc =
> - SMUQ10_ROUND(GET_METRIC_FIELD(SocketGfxBusyAcc, flag));
> + SMUQ10_ROUND(GET_METRIC_FIELD(SocketGfxBusyAcc, version));
> gpu_metrics->mem_activity_acc =
> - SMUQ10_ROUND(GET_METRIC_FIELD(DramBandwidthUtilizationAcc, flag));
> + SMUQ10_ROUND(GET_METRIC_FIELD(DramBandwidthUtilizationAcc, version));
>
> for (i = 0; i < NUM_XGMI_LINKS; i++) {
> gpu_metrics->xgmi_read_data_acc[i] =
> - SMUQ10_ROUND(GET_METRIC_FIELD(XgmiReadDataSizeAcc, flag)[i]);
> + SMUQ10_ROUND(GET_METRIC_FIELD(XgmiReadDataSizeAcc, version)[i]);
> gpu_metrics->xgmi_write_data_acc[i] =
> - SMUQ10_ROUND(GET_METRIC_FIELD(XgmiWriteDataSizeAcc, flag)[i]);
> + SMUQ10_ROUND(GET_METRIC_FIELD(XgmiWriteDataSizeAcc, version)[i]);
> ret = amdgpu_get_xgmi_link_status(adev, i);
> if (ret >= 0)
> gpu_metrics->xgmi_link_status[i] = ret;
> @@ -2627,11 +2649,11 @@ static ssize_t smu_v13_0_6_get_gpu_metrics(struct smu_context *smu, void **table
> for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) {
> gpu_metrics->xcp_stats[i].jpeg_busy
> [(idx * adev->jpeg.num_jpeg_rings) + j] =
> - SMUQ10_ROUND(GET_METRIC_FIELD(JpegBusy, flag)
> + SMUQ10_ROUND(GET_METRIC_FIELD(JpegBusy, version)
> [(inst * adev->jpeg.num_jpeg_rings) + j]);
> }
> gpu_metrics->xcp_stats[i].vcn_busy[idx] =
> - SMUQ10_ROUND(GET_METRIC_FIELD(VcnBusy, flag)[inst]);
> + SMUQ10_ROUND(GET_METRIC_FIELD(VcnBusy, version)[inst]);
> idx++;
>
> }
> @@ -2642,24 +2664,26 @@ static ssize_t smu_v13_0_6_get_gpu_metrics(struct smu_context *smu, void **table
> for_each_inst(k, inst_mask) {
> inst = GET_INST(GC, k);
> gpu_metrics->xcp_stats[i].gfx_busy_inst[idx] =
> - SMUQ10_ROUND(metrics_v0->GfxBusy[inst]);
> + SMUQ10_ROUND(GET_GPU_METRIC_FIELD(GfxBusy, version)[inst]);
> gpu_metrics->xcp_stats[i].gfx_busy_acc[idx] =
> - SMUQ10_ROUND(metrics_v0->GfxBusyAcc[inst]);
> + SMUQ10_ROUND(GET_GPU_METRIC_FIELD(GfxBusyAcc,
> + version)[inst]);
>
> if (smu_v13_0_6_cap_supported(
> smu, SMU_CAP(HST_LIMIT_METRICS)))
> gpu_metrics->xcp_stats[i].gfx_below_host_limit_acc[idx] =
> - SMUQ10_ROUND(metrics_v0->GfxclkBelowHostLimitAcc
> + SMUQ10_ROUND(GET_GPU_METRIC_FIELD
> + (GfxclkBelowHostLimitAcc, version)
> [inst]);
> idx++;
> }
> }
> }
>
> - gpu_metrics->xgmi_link_width = SMUQ10_ROUND(GET_METRIC_FIELD(XgmiWidth, flag));
> - gpu_metrics->xgmi_link_speed = SMUQ10_ROUND(GET_METRIC_FIELD(XgmiBitrate, flag));
> + gpu_metrics->xgmi_link_width = SMUQ10_ROUND(GET_METRIC_FIELD(XgmiWidth, version));
> + gpu_metrics->xgmi_link_speed = SMUQ10_ROUND(GET_METRIC_FIELD(XgmiBitrate, version));
>
> - gpu_metrics->firmware_timestamp = GET_METRIC_FIELD(Timestamp, flag);
> + gpu_metrics->firmware_timestamp = GET_METRIC_FIELD(Timestamp, version);
>
> *table = (void *)gpu_metrics;
> kfree(metrics_v0);
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.h b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.h
> index f0fa42a645c0..717fe669882e 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.h
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.h
> @@ -27,6 +27,14 @@
> #define SMU_13_0_6_UMD_PSTATE_SOCCLK_LEVEL 0x4
> #define SMU_13_0_6_UMD_PSTATE_MCLK_LEVEL 0x2
>
> +typedef enum {
> +/*0*/ METRICS_VERSION_V0 = 0,
> +/*1*/ METRICS_VERSION_V1 = 1,
> +/*2*/ METRICS_VERSION_V2 = 2,
> +
> +/*3*/ NUM_METRICS = 3
> +} METRICS_LIST_e;
> +
> extern void smu_v13_0_6_set_ppt_funcs(struct smu_context *smu);
>
> #endif
^ permalink raw reply [flat|nested] 8+ messages in thread
* RE: [PATCH v2 6/6] drm/amd/pm: Update pm attr for gc_9_5_0
2025-01-22 9:55 ` [PATCH v2 6/6] drm/amd/pm: Update pm attr for gc_9_5_0 Asad Kamal
@ 2025-01-24 6:39 ` Zhang, Hawking
0 siblings, 0 replies; 8+ messages in thread
From: Zhang, Hawking @ 2025-01-24 6:39 UTC (permalink / raw)
To: Kamal, Asad, amd-gfx@lists.freedesktop.org, Lazar, Lijo
Cc: Ma, Le, Zhang, Morris, Deucher, Alexander
[AMD Official Use Only - AMD Internal Distribution Only]
Series is
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Regards,
Hawking
-----Original Message-----
From: Kamal, Asad <Asad.Kamal@amd.com>
Sent: Wednesday, January 22, 2025 17:56
To: amd-gfx@lists.freedesktop.org; Lazar, Lijo <Lijo.Lazar@amd.com>
Cc: Ma, Le <Le.Ma@amd.com>; Zhang, Hawking <Hawking.Zhang@amd.com>; Zhang, Morris <Shiwu.Zhang@amd.com>; Kamal, Asad <Asad.Kamal@amd.com>; Deucher, Alexander <Alexander.Deucher@amd.com>
Subject: [PATCH v2 6/6] drm/amd/pm: Update pm attr for gc_9_5_0
Update power management & clk attributes for gc_v_9_5_0
Signed-off-by: Asad Kamal <asad.kamal@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
---
drivers/gpu/drm/amd/pm/amdgpu_pm.c | 27 ++++++++++++++++++---------
1 file changed, 18 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
index e8ae7681bf0a..0aca0803514e 100644
--- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
@@ -2006,9 +2006,10 @@ static int pp_od_clk_voltage_attr_update(struct amdgpu_device *adev, struct amdg
return 0;
}
- /* Enable pp_od_clk_voltage node for gc 9.4.3 SRIOV/BM support */
+ /* Enable pp_od_clk_voltage node for gc 9.4.3, 9.4.4, 9.5.0 SRIOV/BM
+support */
if (gc_ver == IP_VERSION(9, 4, 3) ||
- gc_ver == IP_VERSION(9, 4, 4)) {
+ gc_ver == IP_VERSION(9, 4, 4) ||
+ gc_ver == IP_VERSION(9, 5, 0)) {
if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev))
*states = ATTR_STATE_UNSUPPORTED;
return 0;
@@ -2087,7 +2088,8 @@ static int pp_dpm_clk_default_attr_update(struct amdgpu_device *adev, struct amd
gc_ver == IP_VERSION(11, 0, 2) ||
gc_ver == IP_VERSION(11, 0, 3) ||
gc_ver == IP_VERSION(9, 4, 3) ||
- gc_ver == IP_VERSION(9, 4, 4)))
+ gc_ver == IP_VERSION(9, 4, 4) ||
+ gc_ver == IP_VERSION(9, 5, 0)))
*states = ATTR_STATE_UNSUPPORTED;
} else if (DEVICE_ATTR_IS(pp_dpm_vclk1)) {
if (!((gc_ver == IP_VERSION(10, 3, 1) || @@ -2109,7 +2111,8 @@ static int pp_dpm_clk_default_attr_update(struct amdgpu_device *adev, struct amd
gc_ver == IP_VERSION(11, 0, 2) ||
gc_ver == IP_VERSION(11, 0, 3) ||
gc_ver == IP_VERSION(9, 4, 3) ||
- gc_ver == IP_VERSION(9, 4, 4)))
+ gc_ver == IP_VERSION(9, 4, 4) ||
+ gc_ver == IP_VERSION(9, 5, 0)))
*states = ATTR_STATE_UNSUPPORTED;
} else if (DEVICE_ATTR_IS(pp_dpm_dclk1)) {
if (!((gc_ver == IP_VERSION(10, 3, 1) || @@ -2120,7 +2123,8 @@ static int pp_dpm_clk_default_attr_update(struct amdgpu_device *adev, struct amd
} else if (DEVICE_ATTR_IS(pp_dpm_pcie)) {
if (gc_ver == IP_VERSION(9, 4, 2) ||
gc_ver == IP_VERSION(9, 4, 3) ||
- gc_ver == IP_VERSION(9, 4, 4))
+ gc_ver == IP_VERSION(9, 4, 4) ||
+ gc_ver == IP_VERSION(9, 5, 0))
*states = ATTR_STATE_UNSUPPORTED;
}
@@ -2416,6 +2420,7 @@ static int default_attr_update(struct amdgpu_device *adev, struct amdgpu_device_
case IP_VERSION(9, 4, 2):
case IP_VERSION(9, 4, 3):
case IP_VERSION(9, 4, 4):
+ case IP_VERSION(9, 5, 0):
case IP_VERSION(10, 3, 0):
case IP_VERSION(11, 0, 0):
case IP_VERSION(11, 0, 1):
@@ -3530,7 +3535,8 @@ static umode_t hwmon_attributes_visible(struct kobject *kobj,
/* Skip crit temp on APU */
if ((((adev->flags & AMD_IS_APU) && (adev->family >= AMDGPU_FAMILY_CZ)) ||
- (gc_ver == IP_VERSION(9, 4, 3) || gc_ver == IP_VERSION(9, 4, 4))) &&
+ (gc_ver == IP_VERSION(9, 4, 3) || gc_ver == IP_VERSION(9, 4, 4) ||
+ gc_ver == IP_VERSION(9, 5, 0))) &&
(attr == &sensor_dev_attr_temp1_crit.dev_attr.attr ||
attr == &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr))
return 0;
@@ -3605,7 +3611,8 @@ static umode_t hwmon_attributes_visible(struct kobject *kobj,
if ((adev->family == AMDGPU_FAMILY_SI || /* not implemented yet */
adev->family == AMDGPU_FAMILY_KV || /* not implemented yet */
(gc_ver == IP_VERSION(9, 4, 3) ||
- gc_ver == IP_VERSION(9, 4, 4))) &&
+ gc_ver == IP_VERSION(9, 4, 4) ||
+ gc_ver == IP_VERSION(9, 5, 0))) &&
(attr == &sensor_dev_attr_in0_input.dev_attr.attr ||
attr == &sensor_dev_attr_in0_label.dev_attr.attr))
return 0;
@@ -3613,7 +3620,8 @@ static umode_t hwmon_attributes_visible(struct kobject *kobj,
/* only APUs other than gc 9,4,3 have vddnb */
if ((!(adev->flags & AMD_IS_APU) ||
(gc_ver == IP_VERSION(9, 4, 3) ||
- gc_ver == IP_VERSION(9, 4, 4))) &&
+ gc_ver == IP_VERSION(9, 4, 4) ||
+ gc_ver == IP_VERSION(9, 5, 0))) &&
(attr == &sensor_dev_attr_in1_input.dev_attr.attr ||
attr == &sensor_dev_attr_in1_label.dev_attr.attr))
return 0;
@@ -3636,7 +3644,8 @@ static umode_t hwmon_attributes_visible(struct kobject *kobj,
/* hotspot temperature for gc 9,4,3*/
if (gc_ver == IP_VERSION(9, 4, 3) ||
- gc_ver == IP_VERSION(9, 4, 4)) {
+ gc_ver == IP_VERSION(9, 4, 4) ||
+ gc_ver == IP_VERSION(9, 5, 0)) {
if (attr == &sensor_dev_attr_temp1_input.dev_attr.attr ||
attr == &sensor_dev_attr_temp1_emergency.dev_attr.attr ||
attr == &sensor_dev_attr_temp1_label.dev_attr.attr)
--
2.46.0
^ permalink raw reply related [flat|nested] 8+ messages in thread
end of thread, other threads:[~2025-01-24 6:39 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2025-01-22 9:55 [PATCH v2 1/6] drm/amd/pm: Update metrics tbl struct for smu_v_13.0.6 Asad Kamal
2025-01-22 9:55 ` [PATCH v2 2/6] drm/amd/pm: Add metrics table header for smu_v13_0_12 Asad Kamal
2025-01-22 9:55 ` [PATCH v2 3/6] drm/amd/pm: Add SMUv13.0.12 PPT interface Asad Kamal
2025-01-22 9:55 ` [PATCH v2 4/6] drm/amd/pm: Add metrics support for smuv13.0.12 Asad Kamal
2025-01-22 11:23 ` Lazar, Lijo
2025-01-22 9:55 ` [PATCH v2 5/6] drm/amd/pm: Skip showing MCLK_OD level Asad Kamal
2025-01-22 9:55 ` [PATCH v2 6/6] drm/amd/pm: Update pm attr for gc_9_5_0 Asad Kamal
2025-01-24 6:39 ` Zhang, Hawking
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