[PATCH v2] drm/amdgpu: Use correct address to setup gart page table for vram access

[PATCH v2] drm/amdgpu: Use correct address to setup gart page table for vram access

[Xiaogang.Chen]

From: Xiaogang Chen <xiaogang.chen@amd.com>

Fixes: 68a5940841684 ("drm/amdgpu/gart: Add helper to bind VRAM pages (v2)")

Use dst input parameter to setup gart page table entries instead of using fixed
location.

Signed-off-by: Xiaogang Chen <xiaogang.chen@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c
index 16c3b78e50cb..ec911dce345f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c
@@ -375,7 +375,7 @@ void amdgpu_gart_map(struct amdgpu_device *adev, uint64_t offset,
  * @start_page: first page to map in the GART aperture
  * @num_pages: number of pages to be mapped
  * @flags: page table entry flags
- * @dst: CPU address of the GART table
+ * @dst: valid CPU address of GART table, cannot be null
  *
  * Binds a BO that is allocated in VRAM to the GART page table
  * (all ASICs).
@@ -396,7 +396,7 @@ void amdgpu_gart_map_vram_range(struct amdgpu_device *adev, uint64_t pa,
 		return;
 
 	for (i = 0; i < num_pages; ++i) {
-		amdgpu_gmc_set_pte_pde(adev, adev->gart.ptr,
+		amdgpu_gmc_set_pte_pde(adev, dst,
 			start_page + i, pa + AMDGPU_GPU_PAGE_SIZE * i, flags);
 	}
 
-- 
2.34.1

Re: [PATCH v2] drm/amdgpu: Use correct address to setup gart page table for vram access

[Alex Deucher]

On Thu, Jan 8, 2026 at 11:08 AM Xiaogang.Chen <xiaogang.chen@amd.com> wrote:
>
> From: Xiaogang Chen <xiaogang.chen@amd.com>
>
> Fixes: 68a5940841684 ("drm/amdgpu/gart: Add helper to bind VRAM pages (v2)")
>
> Use dst input parameter to setup gart page table entries instead of using fixed
> location.
>
> Signed-off-by: Xiaogang Chen <xiaogang.chen@amd.com>

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c
> index 16c3b78e50cb..ec911dce345f 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c
> @@ -375,7 +375,7 @@ void amdgpu_gart_map(struct amdgpu_device *adev, uint64_t offset,
>   * @start_page: first page to map in the GART aperture
>   * @num_pages: number of pages to be mapped
>   * @flags: page table entry flags
> - * @dst: CPU address of the GART table
> + * @dst: valid CPU address of GART table, cannot be null
>   *
>   * Binds a BO that is allocated in VRAM to the GART page table
>   * (all ASICs).
> @@ -396,7 +396,7 @@ void amdgpu_gart_map_vram_range(struct amdgpu_device *adev, uint64_t pa,
>                 return;
>
>         for (i = 0; i < num_pages; ++i) {
> -               amdgpu_gmc_set_pte_pde(adev, adev->gart.ptr,
> +               amdgpu_gmc_set_pte_pde(adev, dst,
>                         start_page + i, pa + AMDGPU_GPU_PAGE_SIZE * i, flags);
>         }
>
> --
> 2.34.1
>

Re: [PATCH v2] drm/amdgpu: Use correct address to setup gart page table for vram access

[Christian König]

On 1/8/26 17:00, Xiaogang.Chen wrote:
> From: Xiaogang Chen <xiaogang.chen@amd.com>
> 
> Fixes: 68a5940841684 ("drm/amdgpu/gart: Add helper to bind VRAM pages (v2)")
> 
> Use dst input parameter to setup gart page table entries instead of using fixed
> location.
> 
> Signed-off-by: Xiaogang Chen <xiaogang.chen@amd.com>

Reviewed-by: Christian König <christian.koenig@amd.com>

> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c
> index 16c3b78e50cb..ec911dce345f 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c
> @@ -375,7 +375,7 @@ void amdgpu_gart_map(struct amdgpu_device *adev, uint64_t offset,
>   * @start_page: first page to map in the GART aperture
>   * @num_pages: number of pages to be mapped
>   * @flags: page table entry flags
> - * @dst: CPU address of the GART table
> + * @dst: valid CPU address of GART table, cannot be null
>   *
>   * Binds a BO that is allocated in VRAM to the GART page table
>   * (all ASICs).
> @@ -396,7 +396,7 @@ void amdgpu_gart_map_vram_range(struct amdgpu_device *adev, uint64_t pa,
>  		return;
>  
>  	for (i = 0; i < num_pages; ++i) {
> -		amdgpu_gmc_set_pte_pde(adev, adev->gart.ptr,
> +		amdgpu_gmc_set_pte_pde(adev, dst,
>  			start_page + i, pa + AMDGPU_GPU_PAGE_SIZE * i, flags);
>  	}
>