Re: [PATCH] drm/amdgpu: skip the VMID 0 flush for VRAM clear-on-release

["Timur Kristóf" <timur.kristof@gmail.com>]

On 2026. augusztus 28., péntek 6:47:34 közép-európai nyári idő Arunpravin 
Paneer Selvam wrote:
> Clear-on-release only runs on VRAM, which amdgpu_ttm_map_buffer() reaches
> via its direct MC address without programming a GART window, yet the wipe
> still forces a VMID 0 flush.

Makes sense.
We don't need the VM flush when we are not changing the page tables.

I agree with the patch, just would like to ask a few questions to better 
understand the underlying problem:

> On GFX11 (e.g. Navi33) that spurious SDMA
> flush can wedge the engine

What is happening when the SDMA engine is wedged? Can it be recovered by an 
SDMA queue reset? Is it just a hang, or can it cause other issues such as page 
faults?

> only flush when a GART window is actually used.

Does that mean that there is still a risk of the wedge when the GART windows 
are used? Can you remind me when/why we need the GART windows exactly?

> Fixes: a68c7eaa7a8f ("drm/amdgpu: Enable clear page functionality")
> Cc: stable@vger.kernel.org
> Cc: Christian König <christian.koenig@amd.com>
> Signed-off-by: Arunpravin Paneer Selvam <Arunpravin.PaneerSelvam@amd.com>

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>

Thanks and best regards,
Timur

> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 5 ++++-
>  1 file changed, 4 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index
> 6c07cee8e8777..2e6c98c2f1efa 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> @@ -2578,6 +2578,7 @@ int amdgpu_ttm_clear_buffer(struct
> amdgpu_ttm_buffer_entity *entity, struct amdgpu_device *adev =
> amdgpu_ttm_adev(bo->tbo.bdev);
>  	struct dma_fence *fence = NULL;
>  	struct amdgpu_res_cursor dst;
> +	bool vm_needs_flush;
>  	int r;
> 
>  	if (!entity)
> @@ -2585,6 +2586,8 @@ int amdgpu_ttm_clear_buffer(struct
> amdgpu_ttm_buffer_entity *entity,
> 
>  	amdgpu_res_first(bo->tbo.resource, 0, amdgpu_bo_size(bo), &dst);
> 
> +	vm_needs_flush = bo->tbo.resource->start == 
AMDGPU_BO_INVALID_OFFSET;
> +
>  	mutex_lock(&entity->lock);
>  	while (dst.remaining) {
>  		struct dma_fence *next;
> @@ -2605,7 +2608,7 @@ int amdgpu_ttm_clear_buffer(struct
> amdgpu_ttm_buffer_entity *entity,
> 
>  		r = amdgpu_ttm_fill_mem(adev, entity,
>  					0, to, cur_size, resv,
> -					&next, true, 
k_job_id);
> +					&next, vm_needs_flush, 
k_job_id);
>  		if (r)
>  			goto error;