* [ath9k-devel] [PATCH 3/3] ath10k: replace TARGET_READ/WRITE macros with inline funcitons
2013-04-23 9:56 [ath9k-devel] [PATCH 0/3] ath10k: PCI cleanups Bartosz Markowski
2013-04-23 9:56 ` [ath9k-devel] [PATCH 1/3] ath10k: update FIXME comments Bartosz Markowski
2013-04-23 9:56 ` [ath9k-devel] [PATCH 2/3] ath10k: rename WAR_CE_SRC_RING_WRITE_IDX_SET Bartosz Markowski
@ 2013-04-23 9:56 ` Bartosz Markowski
2013-04-24 10:47 ` [ath9k-devel] [PATCH 0/3] ath10k: PCI cleanups Kalle Valo
3 siblings, 0 replies; 5+ messages in thread
From: Bartosz Markowski @ 2013-04-23 9:56 UTC (permalink / raw)
To: ath9k-devel
Rename and change into inline functions:
* ath10k_pci_read2
* ath10k_pci_write32
Simplify the argument lists. We store the iomem address in
ath_pci structure. So simply pass to new read/write32 functions
pointer to ath10k struct and allow them to dereference the address.
Those, get rid of targid (intermediate) variables.
Signed-off-by: Bartosz Markowski <bartosz.markowski@tieto.com>
---
drivers/net/wireless/ath/ath10k/ce.c | 80 ++++++++-------------
drivers/net/wireless/ath/ath10k/ce.h | 124 ++++++++++++++++-----------------
drivers/net/wireless/ath/ath10k/pci.c | 24 ++-----
drivers/net/wireless/ath/ath10k/pci.h | 31 +++++----
4 files changed, 111 insertions(+), 148 deletions(-)
diff --git a/drivers/net/wireless/ath/ath10k/ce.c b/drivers/net/wireless/ath/ath10k/ce.c
index a72ed67..8073fc5 100644
--- a/drivers/net/wireless/ath/ath10k/ce.c
+++ b/drivers/net/wireless/ath/ath10k/ce.c
@@ -214,7 +214,6 @@ int ath10k_ce_recv_buf_enqueue(struct ce_state *ce_state,
u32 ctrl_addr = ce_state->ctrl_addr;
struct ath10k *ar = ce_state->ar;
struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
- void __iomem *targid = ar_pci->mem;
unsigned int nentries_mask = dest_ring->nentries_mask;
unsigned int write_index;
unsigned int sw_index;
@@ -239,7 +238,7 @@ int ath10k_ce_recv_buf_enqueue(struct ce_state *ce_state,
/* Update Destination Ring Write Index */
write_index = CE_RING_IDX_INCR(nentries_mask, write_index);
- CE_DEST_RING_WRITE_IDX_SET(ar, targid, ctrl_addr, write_index);
+ CE_DEST_RING_WRITE_IDX_SET(ar, ctrl_addr, write_index);
dest_ring->write_index = write_index;
ret = 0;
} else {
@@ -397,8 +396,6 @@ static int ath10k_ce_completed_send_next_nolock(struct ce_state *ce_state,
struct ce_ring_state *src_ring = ce_state->src_ring;
u32 ctrl_addr = ce_state->ctrl_addr;
struct ath10k *ar = ce_state->ar;
- struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
- void __iomem *targid = ar_pci->mem;
unsigned int nentries_mask = src_ring->nentries_mask;
unsigned int sw_index = src_ring->sw_index;
unsigned int read_index;
@@ -413,8 +410,7 @@ static int ath10k_ce_completed_send_next_nolock(struct ce_state *ce_state,
* value of the HW index has become stale.
*/
ath10k_pci_wake(ar);
- src_ring->hw_index =
- CE_SRC_RING_READ_IDX_GET(targid, ctrl_addr);
+ src_ring->hw_index = CE_SRC_RING_READ_IDX_GET(ar, ctrl_addr);
ath10k_pci_sleep(ar);
}
read_index = src_ring->hw_index;
@@ -534,7 +530,6 @@ void ath10k_ce_per_engine_service(struct ath10k *ar, unsigned int ce_id)
struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
struct ce_state *ce_state = ar_pci->ce_id_to_state[ce_id];
u32 ctrl_addr = ce_state->ctrl_addr;
- void __iomem *targid = ar_pci->mem;
void *transfer_context;
u32 buf;
unsigned int nbytes;
@@ -545,8 +540,7 @@ void ath10k_ce_per_engine_service(struct ath10k *ar, unsigned int ce_id)
spin_lock_bh(&ar_pci->ce_lock);
/* Clear the copy-complete interrupts that will be handled here. */
- CE_ENGINE_INT_STATUS_CLEAR(ar, targid, ctrl_addr,
- HOST_IS_COPY_COMPLETE_MASK);
+ CE_ENGINE_INT_STATUS_CLEAR(ar, ctrl_addr, HOST_IS_COPY_COMPLETE_MASK);
if (ce_state->recv_cb) {
/*
@@ -558,8 +552,7 @@ void ath10k_ce_per_engine_service(struct ath10k *ar, unsigned int ce_id)
&buf, &nbytes,
&id, &flags) == 0) {
spin_unlock_bh(&ar_pci->ce_lock);
- ce_state->recv_cb(ce_state, transfer_context, buf,
- nbytes, id, flags);
+ ce_state->recv_cb(ce_state, transfer_context, buf, nbytes, id, flags);
spin_lock_bh(&ar_pci->ce_lock);
}
}
@@ -575,8 +568,7 @@ void ath10k_ce_per_engine_service(struct ath10k *ar, unsigned int ce_id)
&nbytes,
&id) == 0) {
spin_unlock_bh(&ar_pci->ce_lock);
- ce_state->send_cb(ce_state, transfer_context, buf,
- nbytes, id);
+ ce_state->send_cb(ce_state, transfer_context, buf, nbytes, id);
spin_lock_bh(&ar_pci->ce_lock);
}
}
@@ -585,8 +577,7 @@ void ath10k_ce_per_engine_service(struct ath10k *ar, unsigned int ce_id)
* Misc CE interrupts are not being handled, but still need
* to be cleared.
*/
- CE_ENGINE_INT_STATUS_CLEAR(ar, targid, ctrl_addr,
- CE_WATERMARK_MASK);
+ CE_ENGINE_INT_STATUS_CLEAR(ar, ctrl_addr, CE_WATERMARK_MASK);
spin_unlock_bh(&ar_pci->ce_lock);
ath10k_pci_sleep(ar);
@@ -601,12 +592,11 @@ void ath10k_ce_per_engine_service(struct ath10k *ar, unsigned int ce_id)
void ath10k_ce_per_engine_service_any(struct ath10k *ar)
{
struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
- void __iomem *targid = ar_pci->mem;
int ce_id;
u32 intr_summary;
ath10k_pci_wake(ar);
- intr_summary = CE_INTERRUPT_SUMMARY(ar, targid);
+ intr_summary = CE_INTERRUPT_SUMMARY(ar);
for (ce_id = 0; intr_summary && (ce_id < ar_pci->ce_count); ce_id++) {
if (intr_summary & (1 << ce_id))
@@ -633,19 +623,15 @@ static void ath10k_ce_per_engine_handler_adjust(struct ce_state *ce_state,
{
u32 ctrl_addr = ce_state->ctrl_addr;
struct ath10k *ar = ce_state->ar;
- struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
- void __iomem *targid = ar_pci->mem;
ath10k_pci_wake(ar);
- if ((!disable_copy_compl_intr) &&
- (ce_state->send_cb || ce_state->recv_cb)) {
- CE_COPY_COMPLETE_INTR_ENABLE(ar, targid, ctrl_addr);
- } else {
- CE_COPY_COMPLETE_INTR_DISABLE(ar, targid, ctrl_addr);
- }
+ if ((!disable_copy_compl_intr) && (ce_state->send_cb || ce_state->recv_cb))
+ CE_COPY_COMPLETE_INTR_ENABLE(ar, ctrl_addr);
+ else
+ CE_COPY_COMPLETE_INTR_DISABLE(ar, ctrl_addr);
- CE_WATERMARK_INTR_DISABLE(ar, targid, ctrl_addr);
+ CE_WATERMARK_INTR_DISABLE(ar, ctrl_addr);
ath10k_pci_sleep(ar);
}
@@ -653,7 +639,6 @@ static void ath10k_ce_per_engine_handler_adjust(struct ce_state *ce_state,
void ath10k_ce_disable_interrupts(struct ath10k *ar)
{
struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
- void __iomem *targid = ar_pci->mem;
int ce_id;
ath10k_pci_wake(ar);
@@ -661,7 +646,7 @@ void ath10k_ce_disable_interrupts(struct ath10k *ar)
struct ce_state *ce_state = ar_pci->ce_id_to_state[ce_id];
u32 ctrl_addr = ce_state->ctrl_addr;
- CE_COPY_COMPLETE_INTR_DISABLE(ar, targid, ctrl_addr);
+ CE_COPY_COMPLETE_INTR_DISABLE(ar, ctrl_addr);
}
ath10k_pci_sleep(ar);
}
@@ -710,7 +695,6 @@ static int ath10k_ce_init_src_ring(struct ath10k *ar,
unsigned int nentries = attr->src_nentries;
unsigned int ce_nbytes;
u32 ctrl_addr = CE_BASE_ADDRESS(ar, ce_id);
- void __iomem *targid = ar_pci->mem;
dma_addr_t base_addr;
char *ptr;
@@ -733,9 +717,9 @@ static int ath10k_ce_init_src_ring(struct ath10k *ar,
ath10k_pci_wake(ar);
src_ring->hw_index = src_ring->sw_index =
- CE_SRC_RING_READ_IDX_GET(targid, ctrl_addr);
+ CE_SRC_RING_READ_IDX_GET(ar, ctrl_addr);
src_ring->write_index =
- CE_SRC_RING_WRITE_IDX_GET(targid, ctrl_addr);
+ CE_SRC_RING_WRITE_IDX_GET(ar, ctrl_addr);
ath10k_pci_sleep(ar);
src_ring->per_transfer_context = (void **)ptr;
@@ -779,14 +763,12 @@ static int ath10k_ce_init_src_ring(struct ath10k *ar,
CE_DESC_RING_ALIGN - 1) & ~(CE_DESC_RING_ALIGN - 1));
ath10k_pci_wake(ar);
- CE_SRC_RING_BASE_ADDR_SET(ar, targid, ctrl_addr,
- src_ring->base_addr_ce_space);
- CE_SRC_RING_SZ_SET(ar, targid, ctrl_addr, nentries);
- CE_SRC_RING_DMAX_SET(ar, targid, ctrl_addr,
- attr->src_sz_max);
- CE_SRC_RING_BYTE_SWAP_SET(ar, targid, ctrl_addr, 0);
- CE_SRC_RING_LOWMARK_SET(ar, targid, ctrl_addr, 0);
- CE_SRC_RING_HIGHMARK_SET(ar, targid, ctrl_addr, nentries);
+ CE_SRC_RING_BASE_ADDR_SET(ar, ctrl_addr, src_ring->base_addr_ce_space);
+ CE_SRC_RING_SZ_SET(ar, ctrl_addr, nentries);
+ CE_SRC_RING_DMAX_SET(ar, ctrl_addr, attr->src_sz_max);
+ CE_SRC_RING_BYTE_SWAP_SET(ar, ctrl_addr, 0);
+ CE_SRC_RING_LOWMARK_SET(ar, ctrl_addr, 0);
+ CE_SRC_RING_HIGHMARK_SET(ar, ctrl_addr, nentries);
ath10k_pci_sleep(ar);
return 0;
@@ -802,7 +784,6 @@ static int ath10k_ce_init_dest_ring(struct ath10k *ar,
unsigned int nentries = attr->dest_nentries;
unsigned int ce_nbytes;
u32 ctrl_addr = CE_BASE_ADDRESS(ar, ce_id);
- void __iomem *targid = ar_pci->mem;
dma_addr_t base_addr;
char *ptr;
@@ -824,8 +805,8 @@ static int ath10k_ce_init_dest_ring(struct ath10k *ar,
dest_ring->nentries_mask = nentries - 1;
ath10k_pci_wake(ar);
- dest_ring->sw_index = CE_DEST_RING_READ_IDX_GET(targid, ctrl_addr);
- dest_ring->write_index = CE_DEST_RING_WRITE_IDX_GET(targid, ctrl_addr);
+ dest_ring->sw_index = CE_DEST_RING_READ_IDX_GET(ar, ctrl_addr);
+ dest_ring->write_index = CE_DEST_RING_WRITE_IDX_GET(ar, ctrl_addr);
ath10k_pci_sleep(ar);
dest_ring->per_transfer_context = (void **)ptr;
@@ -864,12 +845,11 @@ static int ath10k_ce_init_dest_ring(struct ath10k *ar,
}
ath10k_pci_wake(ar);
- CE_DEST_RING_BASE_ADDR_SET(ar, targid, ctrl_addr,
- dest_ring->base_addr_ce_space);
- CE_DEST_RING_SZ_SET(ar, targid, ctrl_addr, nentries);
- CE_DEST_RING_BYTE_SWAP_SET(ar, targid, ctrl_addr, 0);
- CE_DEST_RING_LOWMARK_SET(ar, targid, ctrl_addr, 0);
- CE_DEST_RING_HIGHMARK_SET(ar, targid, ctrl_addr, nentries);
+ CE_DEST_RING_BASE_ADDR_SET(ar, ctrl_addr, dest_ring->base_addr_ce_space);
+ CE_DEST_RING_SZ_SET(ar, ctrl_addr, nentries);
+ CE_DEST_RING_BYTE_SWAP_SET(ar, ctrl_addr, 0);
+ CE_DEST_RING_LOWMARK_SET(ar, ctrl_addr, 0);
+ CE_DEST_RING_HIGHMARK_SET(ar, ctrl_addr, nentries);
ath10k_pci_sleep(ar);
return 0;
@@ -918,10 +898,8 @@ struct ce_state *ath10k_ce_init(struct ath10k *ar,
unsigned int ce_id,
struct ce_attr *attr)
{
- struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
struct ce_state *ce_state;
u32 ctrl_addr = CE_BASE_ADDRESS(ar, ce_id);
- void __iomem *targid = ar_pci->mem;
ce_state = ath10k_ce_init_state(ar, ce_id, attr);
if (!ce_state) {
@@ -947,7 +925,7 @@ struct ce_state *ath10k_ce_init(struct ath10k *ar,
/* Enable CE error interrupts */
ath10k_pci_wake(ar);
- CE_ERROR_INTR_ENABLE(ar, targid, ctrl_addr);
+ CE_ERROR_INTR_ENABLE(ar, ctrl_addr);
ath10k_pci_sleep(ar);
return ce_state;
diff --git a/drivers/net/wireless/ath/ath10k/ce.h b/drivers/net/wireless/ath/ath10k/ce.h
index 084b997..bd7188d 100644
--- a/drivers/net/wireless/ath/ath10k/ce.h
+++ b/drivers/net/wireless/ath/ath10k/ce.h
@@ -477,104 +477,104 @@ struct ce_attr {
(CE0_BASE_ADDRESS + \
(CE1_BASE_ADDRESS - CE0_BASE_ADDRESS)*(ce_id))
-#define CE_SRC_RING_WRITE_IDX_SET(ar, targid, ce_ctrl_addr, n) \
- TARGET_WRITE((ar), (targid), (ce_ctrl_addr) + SR_WR_INDEX_ADDRESS, (n))
+#define CE_SRC_RING_WRITE_IDX_SET(ar, ce_ctrl_addr, n) \
+ ath10k_pci_write32((ar), (ce_ctrl_addr) + SR_WR_INDEX_ADDRESS, (n))
-#define CE_SRC_RING_WRITE_IDX_GET(targid, ce_ctrl_addr) \
- TARGET_READ((targid), (ce_ctrl_addr) + SR_WR_INDEX_ADDRESS)
+#define CE_SRC_RING_WRITE_IDX_GET(ar, ce_ctrl_addr) \
+ ath10k_pci_read32((ar), (ce_ctrl_addr) + SR_WR_INDEX_ADDRESS)
-#define CE_SRC_RING_READ_IDX_GET(targid, ce_ctrl_addr) \
- TARGET_READ((targid), (ce_ctrl_addr) + CURRENT_SRRI_ADDRESS)
+#define CE_SRC_RING_READ_IDX_GET(ar, ce_ctrl_addr) \
+ ath10k_pci_read32((ar), (ce_ctrl_addr) + CURRENT_SRRI_ADDRESS)
-#define CE_SRC_RING_BASE_ADDR_SET(ar, targid, ce_ctrl_addr, addr) \
- TARGET_WRITE((ar), (targid), (ce_ctrl_addr) + SR_BA_ADDRESS, (addr))
+#define CE_SRC_RING_BASE_ADDR_SET(ar, ce_ctrl_addr, addr) \
+ ath10k_pci_write32((ar), (ce_ctrl_addr) + SR_BA_ADDRESS, (addr))
-#define CE_SRC_RING_SZ_SET(ar, targid, ce_ctrl_addr, n) \
- TARGET_WRITE((ar), (targid), (ce_ctrl_addr) + SR_SIZE_ADDRESS, (n))
+#define CE_SRC_RING_SZ_SET(ar, ce_ctrl_addr, n) \
+ ath10k_pci_write32((ar), (ce_ctrl_addr) + SR_SIZE_ADDRESS, (n))
-#define CE_SRC_RING_DMAX_SET(ar, targid, ce_ctrl_addr, n) \
- TARGET_WRITE((ar), (targid), (ce_ctrl_addr) + CE_CTRL1_ADDRESS, \
- (TARGET_READ((targid), (ce_ctrl_addr) + CE_CTRL1_ADDRESS) & \
+#define CE_SRC_RING_DMAX_SET(ar, ce_ctrl_addr, n) \
+ ath10k_pci_write32((ar), (ce_ctrl_addr) + CE_CTRL1_ADDRESS, \
+ (ath10k_pci_read32((ar), (ce_ctrl_addr) + CE_CTRL1_ADDRESS) & \
~CE_CTRL1_DMAX_LENGTH_MASK) | \
CE_CTRL1_DMAX_LENGTH_SET(n))
-#define CE_SRC_RING_BYTE_SWAP_SET(ar, targid, ce_ctrl_addr, n) \
- TARGET_WRITE((ar), (targid), (ce_ctrl_addr) + CE_CTRL1_ADDRESS, \
- (TARGET_READ((targid), (ce_ctrl_addr) + CE_CTRL1_ADDRESS) & \
+#define CE_SRC_RING_BYTE_SWAP_SET(ar, ce_ctrl_addr, n) \
+ ath10k_pci_write32((ar), (ce_ctrl_addr) + CE_CTRL1_ADDRESS, \
+ (ath10k_pci_read32((ar), (ce_ctrl_addr) + CE_CTRL1_ADDRESS) & \
~CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK) | \
CE_CTRL1_SRC_RING_BYTE_SWAP_EN_SET(n))
-#define CE_DEST_RING_BYTE_SWAP_SET(ar, targid, ce_ctrl_addr, n) \
- TARGET_WRITE((ar), (targid), (ce_ctrl_addr) + CE_CTRL1_ADDRESS, \
- (TARGET_READ((targid), (ce_ctrl_addr) + CE_CTRL1_ADDRESS) & \
+#define CE_DEST_RING_BYTE_SWAP_SET(ar, ce_ctrl_addr, n) \
+ ath10k_pci_write32((ar), (ce_ctrl_addr) + CE_CTRL1_ADDRESS, \
+ (ath10k_pci_read32((ar), (ce_ctrl_addr) + CE_CTRL1_ADDRESS) & \
~CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK) | \
CE_CTRL1_DST_RING_BYTE_SWAP_EN_SET(n))
-#define CE_DEST_RING_WRITE_IDX_SET(ar, targid, ce_ctrl_addr, n) \
- TARGET_WRITE((ar), (targid), (ce_ctrl_addr) + DST_WR_INDEX_ADDRESS, (n))
+#define CE_DEST_RING_WRITE_IDX_SET(ar, ce_ctrl_addr, n) \
+ ath10k_pci_write32((ar), (ce_ctrl_addr) + DST_WR_INDEX_ADDRESS, (n))
-#define CE_DEST_RING_WRITE_IDX_GET(targid, ce_ctrl_addr) \
- TARGET_READ((targid), (ce_ctrl_addr) + DST_WR_INDEX_ADDRESS)
+#define CE_DEST_RING_WRITE_IDX_GET(ar, ce_ctrl_addr) \
+ ath10k_pci_read32((ar), (ce_ctrl_addr) + DST_WR_INDEX_ADDRESS)
-#define CE_DEST_RING_READ_IDX_GET(targid, ce_ctrl_addr) \
- TARGET_READ((targid), (ce_ctrl_addr) + CURRENT_DRRI_ADDRESS)
+#define CE_DEST_RING_READ_IDX_GET(ar, ce_ctrl_addr) \
+ ath10k_pci_read32((ar), (ce_ctrl_addr) + CURRENT_DRRI_ADDRESS)
-#define CE_DEST_RING_BASE_ADDR_SET(ar, targid, ce_ctrl_addr, addr) \
- TARGET_WRITE((ar), (targid), (ce_ctrl_addr) + DR_BA_ADDRESS, (addr))
+#define CE_DEST_RING_BASE_ADDR_SET(ar, ce_ctrl_addr, addr) \
+ ath10k_pci_write32((ar), (ce_ctrl_addr) + DR_BA_ADDRESS, (addr))
-#define CE_DEST_RING_SZ_SET(ar, targid, ce_ctrl_addr, n) \
- TARGET_WRITE((ar), (targid), (ce_ctrl_addr) + DR_SIZE_ADDRESS, (n))
+#define CE_DEST_RING_SZ_SET(ar, ce_ctrl_addr, n) \
+ ath10k_pci_write32((ar), (ce_ctrl_addr) + DR_SIZE_ADDRESS, (n))
-#define CE_SRC_RING_HIGHMARK_SET(ar, targid, ce_ctrl_addr, n) \
- TARGET_WRITE((ar), (targid), (ce_ctrl_addr) + SRC_WATERMARK_ADDRESS, \
- (TARGET_READ((targid), (ce_ctrl_addr) + SRC_WATERMARK_ADDRESS) & \
+#define CE_SRC_RING_HIGHMARK_SET(ar, ce_ctrl_addr, n) \
+ ath10k_pci_write32((ar), (ce_ctrl_addr) + SRC_WATERMARK_ADDRESS, \
+ (ath10k_pci_read32((ar), (ce_ctrl_addr) + SRC_WATERMARK_ADDRESS) & \
~SRC_WATERMARK_HIGH_MASK) | SRC_WATERMARK_HIGH_SET(n))
-#define CE_SRC_RING_LOWMARK_SET(ar, targid, ce_ctrl_addr, n) \
- TARGET_WRITE((ar), (targid), (ce_ctrl_addr) + SRC_WATERMARK_ADDRESS, \
- (TARGET_READ((targid), (ce_ctrl_addr) + SRC_WATERMARK_ADDRESS) & \
+#define CE_SRC_RING_LOWMARK_SET(ar, ce_ctrl_addr, n) \
+ ath10k_pci_write32((ar), (ce_ctrl_addr) + SRC_WATERMARK_ADDRESS, \
+ (ath10k_pci_read32((ar), (ce_ctrl_addr) + SRC_WATERMARK_ADDRESS) & \
~SRC_WATERMARK_LOW_MASK) | SRC_WATERMARK_LOW_SET(n))
-#define CE_DEST_RING_HIGHMARK_SET(ar, targid, ce_ctrl_addr, n) \
- TARGET_WRITE((ar), (targid), (ce_ctrl_addr) + DST_WATERMARK_ADDRESS, \
- (TARGET_READ((targid), (ce_ctrl_addr) + DST_WATERMARK_ADDRESS) & \
+#define CE_DEST_RING_HIGHMARK_SET(ar, ce_ctrl_addr, n) \
+ ath10k_pci_write32((ar), (ce_ctrl_addr) + DST_WATERMARK_ADDRESS, \
+ (ath10k_pci_read32((ar), (ce_ctrl_addr) + DST_WATERMARK_ADDRESS) & \
~DST_WATERMARK_HIGH_MASK) | DST_WATERMARK_HIGH_SET(n))
-#define CE_DEST_RING_LOWMARK_SET(ar, targid, ce_ctrl_addr, n) \
- TARGET_WRITE((ar), (targid), (ce_ctrl_addr) + DST_WATERMARK_ADDRESS, \
- (TARGET_READ((targid), (ce_ctrl_addr) + DST_WATERMARK_ADDRESS) & \
+#define CE_DEST_RING_LOWMARK_SET(ar, ce_ctrl_addr, n) \
+ ath10k_pci_write32((ar), (ce_ctrl_addr) + DST_WATERMARK_ADDRESS, \
+ (ath10k_pci_read32((ar), (ce_ctrl_addr) + DST_WATERMARK_ADDRESS) & \
~DST_WATERMARK_LOW_MASK) | DST_WATERMARK_LOW_SET(n))
-#define CE_COPY_COMPLETE_INTR_ENABLE(ar, targid, ce_ctrl_addr) \
- TARGET_WRITE((ar), (targid), (ce_ctrl_addr) + HOST_IE_ADDRESS, \
- TARGET_READ((targid), (ce_ctrl_addr) + HOST_IE_ADDRESS) | \
+#define CE_COPY_COMPLETE_INTR_ENABLE(ar, ce_ctrl_addr) \
+ ath10k_pci_write32((ar), (ce_ctrl_addr) + HOST_IE_ADDRESS, \
+ ath10k_pci_read32((ar), (ce_ctrl_addr) + HOST_IE_ADDRESS) | \
HOST_IE_COPY_COMPLETE_MASK)
-#define CE_COPY_COMPLETE_INTR_DISABLE(ar, targid, ce_ctrl_addr) \
- TARGET_WRITE((ar), (targid), (ce_ctrl_addr) + HOST_IE_ADDRESS, \
- TARGET_READ((targid), (ce_ctrl_addr) + HOST_IE_ADDRESS) & \
+#define CE_COPY_COMPLETE_INTR_DISABLE(ar, ce_ctrl_addr) \
+ ath10k_pci_write32((ar), (ce_ctrl_addr) + HOST_IE_ADDRESS, \
+ ath10k_pci_read32((ar), (ce_ctrl_addr) + HOST_IE_ADDRESS) & \
~HOST_IE_COPY_COMPLETE_MASK)
-#define CE_WATERMARK_INTR_ENABLE(ar, targid, ce_ctrl_addr) \
- TARGET_WRITE((ar), (targid), (ce_ctrl_addr) + HOST_IE_ADDRESS, \
- TARGET_READ((targid), (ce_ctrl_addr) + HOST_IE_ADDRESS) | \
+#define CE_WATERMARK_INTR_ENABLE(ar, ce_ctrl_addr) \
+ ath10k_pci_write32((ar), (ce_ctrl_addr) + HOST_IE_ADDRESS, \
+ ath10k_pci_read32((ar), (ce_ctrl_addr) + HOST_IE_ADDRESS) | \
CE_WATERMARK_MASK)
-#define CE_WATERMARK_INTR_DISABLE(ar, targid, ce_ctrl_addr) \
- TARGET_WRITE((ar), (targid), (ce_ctrl_addr) + HOST_IE_ADDRESS, \
- TARGET_READ((targid), (ce_ctrl_addr) + HOST_IE_ADDRESS) & \
+#define CE_WATERMARK_INTR_DISABLE(ar, ce_ctrl_addr) \
+ ath10k_pci_write32((ar), (ce_ctrl_addr) + HOST_IE_ADDRESS, \
+ ath10k_pci_read32((ar), (ce_ctrl_addr) + HOST_IE_ADDRESS) & \
~CE_WATERMARK_MASK)
-#define CE_ERROR_INTR_ENABLE(ar, targid, ce_ctrl_addr) \
- TARGET_WRITE((ar), (targid), (ce_ctrl_addr) + MISC_IE_ADDRESS, \
- TARGET_READ((targid), (ce_ctrl_addr) + MISC_IE_ADDRESS) | \
+#define CE_ERROR_INTR_ENABLE(ar, ce_ctrl_addr) \
+ ath10k_pci_write32((ar), (ce_ctrl_addr) + MISC_IE_ADDRESS, \
+ ath10k_pci_read32((ar), (ce_ctrl_addr) + MISC_IE_ADDRESS) | \
CE_ERROR_MASK)
-#define CE_ENGINE_INT_STATUS_GET(targid, ce_ctrl_addr) \
- TARGET_READ((targid), (ce_ctrl_addr)+HOST_IS_ADDRESS)
+#define CE_ENGINE_INT_STATUS_GET(ar, ce_ctrl_addr) \
+ ath10k_pci_read32((ar), (ce_ctrl_addr)+HOST_IS_ADDRESS)
-#define CE_ENGINE_INT_STATUS_CLEAR(ar, targid, ce_ctrl_addr, mask) \
- TARGET_WRITE((ar), (targid), (ce_ctrl_addr)+HOST_IS_ADDRESS, (mask))
+#define CE_ENGINE_INT_STATUS_CLEAR(ar, ce_ctrl_addr, mask) \
+ ath10k_pci_write32((ar), (ce_ctrl_addr)+HOST_IS_ADDRESS, (mask))
#define CE_WATERMARK_MASK (HOST_IS_SRC_RING_LOW_WATERMARK_MASK | \
HOST_IS_SRC_RING_HIGH_WATERMARK_MASK | \
@@ -607,9 +607,9 @@ struct ce_attr {
CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB)
#define CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS 0x0000
-#define CE_INTERRUPT_SUMMARY(ar, targid) \
+#define CE_INTERRUPT_SUMMARY(ar) \
CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_GET( \
- TARGET_READ((targid), CE_WRAPPER_BASE_ADDRESS + \
+ ath10k_pci_read32((ar), CE_WRAPPER_BASE_ADDRESS + \
CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS))
#endif /* _CE_H_ */
diff --git a/drivers/net/wireless/ath/ath10k/pci.c b/drivers/net/wireless/ath/ath10k/pci.c
index b35b7a0..b0110e5 100644
--- a/drivers/net/wireless/ath/ath10k/pci.c
+++ b/drivers/net/wireless/ath/ath10k/pci.c
@@ -102,7 +102,6 @@ static int ath10k_pci_diag_read_mem(struct ath10k *ar, u32 address, u8 *data,
int nbytes)
{
struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
- void __iomem *targid;
int ret = 0;
u32 buf;
unsigned int completed_nbytes, orig_nbytes, remaining_bytes;
@@ -133,7 +132,6 @@ static int ath10k_pci_diag_read_mem(struct ath10k *ar, u32 address, u8 *data,
return ret;
}
- targid = ar_pci->mem;
ce_diag = ar_pci->ce_diag;
/*
@@ -253,13 +251,8 @@ static int ath10k_pci_diag_read_access(struct ath10k *ar, u32 address, u32 *data
return ath10k_pci_diag_read_mem(ar, address, (u8 *)data,
sizeof(u32));
else {
- struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
- void __iomem *targid;
-
- targid = ar_pci->mem;
-
ath10k_pci_wake(ar);
- *data = TARGET_READ(targid, address);
+ *data = ath10k_pci_read32(ar, address);
ath10k_pci_sleep(ar);
return 0;
}
@@ -269,7 +262,6 @@ static int ath10k_pci_diag_write_mem(struct ath10k *ar, u32 address, u8 *data,
int nbytes)
{
struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
- void __iomem *targid;
int ret = 0;
u32 buf;
unsigned int completed_nbytes, orig_nbytes, remaining_bytes;
@@ -281,7 +273,6 @@ static int ath10k_pci_diag_write_mem(struct ath10k *ar, u32 address, u8 *data,
dma_addr_t ce_data_base = 0;
int i;
- targid = ar_pci->mem;
ce_diag = ar_pci->ce_diag;
/*
@@ -408,13 +399,8 @@ static int ath10k_pci_diag_write_access(struct ath10k *ar, u32 address,
return ath10k_pci_diag_write_mem(ar, address, (u8 *) &data_buf,
sizeof(u32));
} else {
- struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
- void __iomem *targid;
-
- targid = ar_pci->mem;
-
ath10k_pci_wake(ar);
- TARGET_WRITE(ar, targid, address, data);
+ ath10k_pci_write32(ar, address, data);
ath10k_pci_sleep(ar);
return 0;
@@ -1708,18 +1694,16 @@ ce_deinit:
static void ath10k_pci_fw_interrupt_handler(struct ath10k *ar)
{
struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
- void __iomem *targid = ar_pci->mem;
u32 fw_indicator_address, fw_indicator;
ath10k_pci_wake(ar);
fw_indicator_address = ar_pci->fw_indicator_address;
- fw_indicator = TARGET_READ(targid, fw_indicator_address);
+ fw_indicator = ath10k_pci_read32(ar, fw_indicator_address);
if (fw_indicator & FW_IND_EVENT_PENDING) {
/* ACK: clear Target-side pending event */
- TARGET_WRITE(ar, targid, fw_indicator_address,
- fw_indicator & ~FW_IND_EVENT_PENDING);
+ ath10k_pci_write32(ar, fw_indicator_address, fw_indicator & ~FW_IND_EVENT_PENDING);
ath10k_pci_sleep(ar);
if (ar_pci->started)
diff --git a/drivers/net/wireless/ath/ath10k/pci.h b/drivers/net/wireless/ath/ath10k/pci.h
index 7270e72..5396150 100644
--- a/drivers/net/wireless/ath/ath10k/pci.h
+++ b/drivers/net/wireless/ath/ath10k/pci.h
@@ -259,11 +259,10 @@ static inline struct ath10k_pci *ath10k_pci_priv(struct ath10k *ar)
/* Wait up to this many Ms for a Diagnostic Access CE operation to complete */
#define DIAG_ACCESS_CE_TIMEOUT_MS 10
-static inline void pci_write32_v1_workaround(struct ath10k *ar,
- void __iomem *addr,
- u32 offset, u32 value)
+static inline void pci_write32_v1_workaround(struct ath10k *ar, u32 offset, u32 value)
{
struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
+ void __iomem *addr = ar_pci->mem;
if (ar_pci->hw_v1_workaround) {
unsigned long irq_flags;
@@ -281,8 +280,8 @@ static inline void pci_write32_v1_workaround(struct ath10k *ar,
}
/*
- * This API allows the Host to access Target registers of a given
- * A_target_id_t directly and relatively efficiently over PCIe.
+ * This API allows the Host to access Target registers directly
+ * and relatively efficiently over PCIe.
* This allows the Host to avoid extra overhead associated with
* sending a message to firmware and waiting for a response message
* from firmware, as is done on other interconnects.
@@ -293,10 +292,8 @@ static inline void pci_write32_v1_workaround(struct ath10k *ar,
* and to verify that it is awake and will remain awake.
*
* Usage:
- * During initialization, use TARGET_ID to obtain an 'target ID'
- * for use with these interfaces.
*
- * Use TARGET_READ and TARGET_WRITE to access Target space.
+ * Use ath10k_pci_read32 and ath10k_pci_write32 to access Target space.
* These calls must be bracketed by ath10k_pci_wake and
* ath10k_pci_sleep. A single BEGIN/END pair is adequate for
* multiple READ/WRITE operations.
@@ -311,10 +308,15 @@ static inline void pci_write32_v1_workaround(struct ath10k *ar,
* directly accessible. BEGIN/END is under a reference counter;
* multiple code paths may issue BEGIN/END on a single targid.
*/
-#define TARGET_WRITE(ar, targid, offset, value) \
- pci_write32_v1_workaround(ar, targid , (offset), (value))
+static inline void ath10k_pci_write32(struct ath10k *ar, u32 offset, u32 value) {
+ pci_write32_v1_workaround(ar, offset, value);
+}
+
+static inline u32 ath10k_pci_read32(struct ath10k *ar, u32 offset) {
+ struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
-#define TARGET_READ(targid, offset) ioread32(targid + (offset))
+ return ioread32(ar_pci->mem + offset);
+}
/*
* FIXME: This function is a wrapper to workaround QCA988x_1.0 HW CE problem.
@@ -327,16 +329,15 @@ static inline void ath10k_set_source_ring_write_index(struct ath10k *ar,
{
struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
void __iomem *indicator_addr;
- void __iomem *targid = ar_pci->mem;
if (!ar_pci->hw_v1_workaround) {
- CE_SRC_RING_WRITE_IDX_SET(ar, targid, ctrl_addr, write_index);
+ CE_SRC_RING_WRITE_IDX_SET(ar, ctrl_addr, write_index);
return;
}
/* workaround path starts from here */
- indicator_addr = targid + ctrl_addr + DST_WATERMARK_ADDRESS;
+ indicator_addr = ar_pci->mem + ctrl_addr + DST_WATERMARK_ADDRESS;
if (ctrl_addr == CE_BASE_ADDRESS(ar, CDC_WAR_DATA_CE)) {
iowrite32((CDC_WAR_MAGIC_STR | write_index), indicator_addr);
@@ -352,7 +353,7 @@ static inline void ath10k_set_source_ring_write_index(struct ath10k *ar,
(void)ioread32(indicator_addr);
(void)ioread32(indicator_addr); /* conservative */
- CE_SRC_RING_WRITE_IDX_SET(ar, targid, ctrl_addr, write_index);
+ CE_SRC_RING_WRITE_IDX_SET(ar, ctrl_addr, write_index);
iowrite32(0, indicator_addr);
local_irq_restore(irq_flags);
--
1.7.10
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