* [PATCH 10/11] ARM: SoCFPGA: Add EBV SoCrates board support
From: Sascha Hauer @ 2013-09-16 8:48 UTC (permalink / raw)
To: barebox
In-Reply-To: <1379321300-8085-1-git-send-email-s.hauer@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/boards/Makefile | 1 +
arch/arm/boards/ebv-socrates/Makefile | 2 +
arch/arm/boards/ebv-socrates/board.c | 37 ++++
arch/arm/boards/ebv-socrates/config.h | 1 +
arch/arm/boards/ebv-socrates/lowlevel.c | 99 ++++++++++
arch/arm/boards/ebv-socrates/pinmux_config.c | 210 +++++++++++++++++++++
arch/arm/boards/ebv-socrates/pll_config.h | 97 ++++++++++
arch/arm/boards/ebv-socrates/sdram_config.h | 73 +++++++
arch/arm/boards/ebv-socrates/sequencer_auto.h | 174 +++++++++++++++++
.../boards/ebv-socrates/sequencer_auto_ac_init.c | 40 ++++
.../boards/ebv-socrates/sequencer_auto_inst_init.c | 132 +++++++++++++
arch/arm/boards/ebv-socrates/sequencer_defines.h | 118 ++++++++++++
arch/arm/dts/Makefile | 4 +-
arch/arm/dts/socfpga_cyclone5_socrates.dts | 64 +++++++
arch/arm/mach-socfpga/Kconfig | 4 +
images/Makefile.socfpga | 8 +
16 files changed, 1063 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/boards/ebv-socrates/Makefile
create mode 100644 arch/arm/boards/ebv-socrates/board.c
create mode 100644 arch/arm/boards/ebv-socrates/config.h
create mode 100644 arch/arm/boards/ebv-socrates/lowlevel.c
create mode 100644 arch/arm/boards/ebv-socrates/pinmux_config.c
create mode 100644 arch/arm/boards/ebv-socrates/pll_config.h
create mode 100644 arch/arm/boards/ebv-socrates/sdram_config.h
create mode 100644 arch/arm/boards/ebv-socrates/sequencer_auto.h
create mode 100644 arch/arm/boards/ebv-socrates/sequencer_auto_ac_init.c
create mode 100644 arch/arm/boards/ebv-socrates/sequencer_auto_inst_init.c
create mode 100644 arch/arm/boards/ebv-socrates/sequencer_defines.h
create mode 100644 arch/arm/dts/socfpga_cyclone5_socrates.dts
diff --git a/arch/arm/boards/Makefile b/arch/arm/boards/Makefile
index a9bc15f..2210fd4 100644
--- a/arch/arm/boards/Makefile
+++ b/arch/arm/boards/Makefile
@@ -75,6 +75,7 @@ obj-$(CONFIG_MACH_SABRELITE) += freescale-mx6-sabrelite/
obj-$(CONFIG_MACH_SABRESD) += freescale-mx6-sabresd/
obj-$(CONFIG_MACH_SAMA5D3XEK) += sama5d3xek/
obj-$(CONFIG_MACH_SCB9328) += scb9328/
+obj-$(CONFIG_MACH_SOCFPGA_EBV_SOCRATES) += ebv-socrates/
obj-$(CONFIG_MACH_SOCFPGA_TERASIC_SOCKIT) += terasic-sockit/
obj-$(CONFIG_MACH_TNY_A9260) += tny-a926x/
obj-$(CONFIG_MACH_TNY_A9263) += tny-a926x/
diff --git a/arch/arm/boards/ebv-socrates/Makefile b/arch/arm/boards/ebv-socrates/Makefile
new file mode 100644
index 0000000..8c927fe
--- /dev/null
+++ b/arch/arm/boards/ebv-socrates/Makefile
@@ -0,0 +1,2 @@
+obj-y += lowlevel.o board.o
+pbl-y += lowlevel.o
diff --git a/arch/arm/boards/ebv-socrates/board.c b/arch/arm/boards/ebv-socrates/board.c
new file mode 100644
index 0000000..b2f62dc
--- /dev/null
+++ b/arch/arm/boards/ebv-socrates/board.c
@@ -0,0 +1,37 @@
+#include <common.h>
+#include <types.h>
+#include <driver.h>
+#include <init.h>
+#include <asm/armlinux.h>
+#include <linux/micrel_phy.h>
+#include <linux/phy.h>
+#include <sizes.h>
+#include <fcntl.h>
+#include <fs.h>
+#include <mach/socfpga-regs.h>
+
+static int phy_fixup(struct phy_device *dev)
+{
+ /* min rx data delay */
+ phy_write(dev, 0x0b, 0x8105);
+ phy_write(dev, 0x0c, 0x0000);
+
+ /* max rx/tx clock delay, min rx/tx control delay */
+ phy_write(dev, 0x0b, 0x8104);
+ phy_write(dev, 0x0c, 0xa0d0);
+ phy_write(dev, 0x0b, 0x104);
+
+ return 0;
+}
+
+static int socrates_init(void)
+{
+ if (!of_machine_is_compatible("ebv,socrates"))
+ return 0;
+
+ if (IS_ENABLED(CONFIG_PHYLIB))
+ phy_register_fixup_for_uid(PHY_ID_KSZ9021, MICREL_PHY_ID_MASK, phy_fixup);
+
+ return 0;
+}
+postcore_initcall(socrates_init);
diff --git a/arch/arm/boards/ebv-socrates/config.h b/arch/arm/boards/ebv-socrates/config.h
new file mode 100644
index 0000000..da84fa5
--- /dev/null
+++ b/arch/arm/boards/ebv-socrates/config.h
@@ -0,0 +1 @@
+/* nothing */
diff --git a/arch/arm/boards/ebv-socrates/lowlevel.c b/arch/arm/boards/ebv-socrates/lowlevel.c
new file mode 100644
index 0000000..d2f02e0
--- /dev/null
+++ b/arch/arm/boards/ebv-socrates/lowlevel.c
@@ -0,0 +1,99 @@
+#include <common.h>
+#include <sizes.h>
+#include <io.h>
+#include <asm/barebox-arm-head.h>
+#include <asm/barebox-arm.h>
+#include <asm/cache.h>
+#include <mach/generic.h>
+#include <debug_ll.h>
+#include "sdram_config.h"
+#include <mach/sdram_config.h>
+#include "pinmux_config.c"
+#include "pll_config.h"
+#include <mach/pll_config.h>
+#include "sequencer_defines.h"
+#include "sequencer_auto.h"
+#include <mach/sequencer.c>
+#include "sequencer_auto_inst_init.c"
+#include "sequencer_auto_ac_init.c"
+
+static inline void ledon(void)
+{
+ u32 val;
+
+ val = readl(0xFF708000);
+ val &= ~(1 << 28);
+ writel(val, 0xFF708000);
+
+ val = readl(0xFF708004);
+ val |= 1 << 28;
+ writel(val, 0xFF708004);
+}
+
+static inline void ledoff(void)
+{
+ u32 val;
+
+ val = readl(0xFF708000);
+ val |= 1 << 28;
+ writel(val, 0xFF708000);
+
+ val = readl(0xFF708004);
+ val |= 1 << 28;
+ writel(val, 0xFF708004);
+}
+
+extern char __dtb_socfpga_cyclone5_socrates_start[];
+
+ENTRY_FUNCTION(start_socfpga_socrates)(void)
+{
+ uint32_t fdt;
+
+ __barebox_arm_head();
+
+ arm_cpu_lowlevel_init();
+
+ fdt = (uint32_t)__dtb_socfpga_cyclone5_socrates_start - get_runtime_offset();
+
+ barebox_arm_entry(0x0, SZ_1G, fdt);
+}
+
+static noinline void socrates_entry(void)
+{
+ int ret;
+
+ arm_early_mmu_cache_invalidate();
+
+ relocate_to_current_adr();
+ setup_c();
+
+ socfpga_lowlevel_init(&cm_default_cfg,
+ sys_mgr_init_table, ARRAY_SIZE(sys_mgr_init_table));
+
+ puts_ll("lowlevel init done\n");
+ puts_ll("SDRAM setup...\n");
+
+ socfpga_sdram_mmr_init();
+
+ puts_ll("SDRAM calibration...\n");
+
+ ret = socfpga_sdram_calibration(inst_rom_init, inst_rom_init_size,
+ ac_rom_init, ac_rom_init_size);
+ if (ret)
+ hang();
+
+ puts_ll("done\n");
+
+ barebox_arm_entry(0x0, SZ_1G, 0);
+}
+
+ENTRY_FUNCTION(start_socfpga_socrates_xload)(void)
+{
+ __barebox_arm_head();
+
+ arm_cpu_lowlevel_init();
+
+ arm_setup_stack(0xffff0000 + SZ_64K - SZ_4K - 16);
+
+ socrates_entry();
+}
diff --git a/arch/arm/boards/ebv-socrates/pinmux_config.c b/arch/arm/boards/ebv-socrates/pinmux_config.c
new file mode 100644
index 0000000..e259078
--- /dev/null
+++ b/arch/arm/boards/ebv-socrates/pinmux_config.c
@@ -0,0 +1,210 @@
+/* pin MUX configuration data */
+static unsigned long sys_mgr_init_table[] = {
+ 0, /* EMACIO0 */
+ 2, /* EMACIO1 */
+ 2, /* EMACIO2 */
+ 2, /* EMACIO3 */
+ 2, /* EMACIO4 */
+ 2, /* EMACIO5 */
+ 2, /* EMACIO6 */
+ 2, /* EMACIO7 */
+ 2, /* EMACIO8 */
+ 0, /* EMACIO9 */
+ 2, /* EMACIO10 */
+ 2, /* EMACIO11 */
+ 2, /* EMACIO12 */
+ 2, /* EMACIO13 */
+ 0, /* EMACIO14 */
+ 0, /* EMACIO15 */
+ 0, /* EMACIO16 */
+ 0, /* EMACIO17 */
+ 0, /* EMACIO18 */
+ 0, /* EMACIO19 */
+ 3, /* FLASHIO0 */
+ 0, /* FLASHIO1 */
+ 3, /* FLASHIO2 */
+ 3, /* FLASHIO3 */
+ 0, /* FLASHIO4 */
+ 0, /* FLASHIO5 */
+ 0, /* FLASHIO6 */
+ 0, /* FLASHIO7 */
+ 0, /* FLASHIO8 */
+ 3, /* FLASHIO9 */
+ 3, /* FLASHIO10 */
+ 3, /* FLASHIO11 */
+ 0, /* GENERALIO0 */
+ 1, /* GENERALIO1 */
+ 1, /* GENERALIO2 */
+ 1, /* GENERALIO3 */
+ 1, /* GENERALIO4 */
+ 0, /* GENERALIO5 */
+ 0, /* GENERALIO6 */
+ 1, /* GENERALIO7 */
+ 1, /* GENERALIO8 */
+ 3, /* GENERALIO9 */
+ 3, /* GENERALIO10 */
+ 3, /* GENERALIO11 */
+ 3, /* GENERALIO12 */
+ 2, /* GENERALIO13 */
+ 2, /* GENERALIO14 */
+ 1, /* GENERALIO15 */
+ 1, /* GENERALIO16 */
+ 1, /* GENERALIO17 */
+ 1, /* GENERALIO18 */
+ 0, /* GENERALIO19 */
+ 0, /* GENERALIO20 */
+ 0, /* GENERALIO21 */
+ 0, /* GENERALIO22 */
+ 0, /* GENERALIO23 */
+ 0, /* GENERALIO24 */
+ 0, /* GENERALIO25 */
+ 0, /* GENERALIO26 */
+ 0, /* GENERALIO27 */
+ 0, /* GENERALIO28 */
+ 0, /* GENERALIO29 */
+ 0, /* GENERALIO30 */
+ 0, /* GENERALIO31 */
+ 2, /* MIXED1IO0 */
+ 2, /* MIXED1IO1 */
+ 2, /* MIXED1IO2 */
+ 2, /* MIXED1IO3 */
+ 2, /* MIXED1IO4 */
+ 2, /* MIXED1IO5 */
+ 2, /* MIXED1IO6 */
+ 2, /* MIXED1IO7 */
+ 2, /* MIXED1IO8 */
+ 2, /* MIXED1IO9 */
+ 2, /* MIXED1IO10 */
+ 2, /* MIXED1IO11 */
+ 2, /* MIXED1IO12 */
+ 2, /* MIXED1IO13 */
+ 0, /* MIXED1IO14 */
+ 3, /* MIXED1IO15 */
+ 3, /* MIXED1IO16 */
+ 3, /* MIXED1IO17 */
+ 3, /* MIXED1IO18 */
+ 3, /* MIXED1IO19 */
+ 3, /* MIXED1IO20 */
+ 0, /* MIXED1IO21 */
+ 0, /* MIXED2IO0 */
+ 0, /* MIXED2IO1 */
+ 0, /* MIXED2IO2 */
+ 0, /* MIXED2IO3 */
+ 0, /* MIXED2IO4 */
+ 0, /* MIXED2IO5 */
+ 0, /* MIXED2IO6 */
+ 0, /* MIXED2IO7 */
+ 0, /* GPLINMUX48 */
+ 0, /* GPLINMUX49 */
+ 0, /* GPLINMUX50 */
+ 0, /* GPLINMUX51 */
+ 0, /* GPLINMUX52 */
+ 0, /* GPLINMUX53 */
+ 0, /* GPLINMUX54 */
+ 0, /* GPLINMUX55 */
+ 0, /* GPLINMUX56 */
+ 0, /* GPLINMUX57 */
+ 0, /* GPLINMUX58 */
+ 0, /* GPLINMUX59 */
+ 0, /* GPLINMUX60 */
+ 0, /* GPLINMUX61 */
+ 0, /* GPLINMUX62 */
+ 0, /* GPLINMUX63 */
+ 0, /* GPLINMUX64 */
+ 0, /* GPLINMUX65 */
+ 0, /* GPLINMUX66 */
+ 0, /* GPLINMUX67 */
+ 0, /* GPLINMUX68 */
+ 0, /* GPLINMUX69 */
+ 0, /* GPLINMUX70 */
+ 1, /* GPLMUX0 */
+ 1, /* GPLMUX1 */
+ 1, /* GPLMUX2 */
+ 1, /* GPLMUX3 */
+ 1, /* GPLMUX4 */
+ 1, /* GPLMUX5 */
+ 1, /* GPLMUX6 */
+ 1, /* GPLMUX7 */
+ 1, /* GPLMUX8 */
+ 1, /* GPLMUX9 */
+ 1, /* GPLMUX10 */
+ 1, /* GPLMUX11 */
+ 1, /* GPLMUX12 */
+ 1, /* GPLMUX13 */
+ 1, /* GPLMUX14 */
+ 1, /* GPLMUX15 */
+ 1, /* GPLMUX16 */
+ 1, /* GPLMUX17 */
+ 1, /* GPLMUX18 */
+ 1, /* GPLMUX19 */
+ 1, /* GPLMUX20 */
+ 1, /* GPLMUX21 */
+ 1, /* GPLMUX22 */
+ 1, /* GPLMUX23 */
+ 1, /* GPLMUX24 */
+ 1, /* GPLMUX25 */
+ 1, /* GPLMUX26 */
+ 1, /* GPLMUX27 */
+ 1, /* GPLMUX28 */
+ 1, /* GPLMUX29 */
+ 1, /* GPLMUX30 */
+ 1, /* GPLMUX31 */
+ 1, /* GPLMUX32 */
+ 1, /* GPLMUX33 */
+ 1, /* GPLMUX34 */
+ 1, /* GPLMUX35 */
+ 1, /* GPLMUX36 */
+ 1, /* GPLMUX37 */
+ 1, /* GPLMUX38 */
+ 1, /* GPLMUX39 */
+ 1, /* GPLMUX40 */
+ 1, /* GPLMUX41 */
+ 1, /* GPLMUX42 */
+ 1, /* GPLMUX43 */
+ 1, /* GPLMUX44 */
+ 1, /* GPLMUX45 */
+ 1, /* GPLMUX46 */
+ 1, /* GPLMUX47 */
+ 1, /* GPLMUX48 */
+ 1, /* GPLMUX49 */
+ 1, /* GPLMUX50 */
+ 1, /* GPLMUX51 */
+ 1, /* GPLMUX52 */
+ 1, /* GPLMUX53 */
+ 1, /* GPLMUX54 */
+ 1, /* GPLMUX55 */
+ 1, /* GPLMUX56 */
+ 1, /* GPLMUX57 */
+ 1, /* GPLMUX58 */
+ 1, /* GPLMUX59 */
+ 1, /* GPLMUX60 */
+ 1, /* GPLMUX61 */
+ 1, /* GPLMUX62 */
+ 1, /* GPLMUX63 */
+ 1, /* GPLMUX64 */
+ 1, /* GPLMUX65 */
+ 1, /* GPLMUX66 */
+ 1, /* GPLMUX67 */
+ 1, /* GPLMUX68 */
+ 1, /* GPLMUX69 */
+ 1, /* GPLMUX70 */
+ 0, /* NANDUSEFPGA */
+ 0, /* UART0USEFPGA */
+ 0, /* RGMII1USEFPGA */
+ 0, /* SPIS0USEFPGA */
+ 0, /* CAN0USEFPGA */
+ 0, /* I2C0USEFPGA */
+ 0, /* SDMMCUSEFPGA */
+ 0, /* QSPIUSEFPGA */
+ 0, /* SPIS1USEFPGA */
+ 0, /* RGMII0USEFPGA */
+ 0, /* UART1USEFPGA */
+ 0, /* CAN1USEFPGA */
+ 0, /* USB1USEFPGA */
+ 0, /* I2C3USEFPGA */
+ 0, /* I2C2USEFPGA */
+ 0, /* I2C1USEFPGA */
+ 0, /* SPIM1USEFPGA */
+ 0, /* USB0USEFPGA */
+ 0 /* SPIM0USEFPGA */
+};
diff --git a/arch/arm/boards/ebv-socrates/pll_config.h b/arch/arm/boards/ebv-socrates/pll_config.h
new file mode 100644
index 0000000..7682f63
--- /dev/null
+++ b/arch/arm/boards/ebv-socrates/pll_config.h
@@ -0,0 +1,97 @@
+#ifndef _PRELOADER_PLL_CONFIG_H_
+#define _PRELOADER_PLL_CONFIG_H_
+
+/* PLL configuration data */
+/* Main PLL */
+#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM (0)
+#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER (63)
+#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT (0)
+#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT (0)
+#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT (0)
+#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT (3)
+#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT (3)
+#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT (15)
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK (1)
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK (1)
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK (1)
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK (1)
+#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK (0)
+#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK (1)
+#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK (0)
+/*
+ * To tell where is the clock source:
+ * 0 = MAINPLL
+ * 1 = PERIPHPLL
+ */
+#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP (1)
+#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP (1)
+
+/* Peripheral PLL */
+#define CONFIG_HPS_PERPLLGRP_VCO_DENOM (1)
+#define CONFIG_HPS_PERPLLGRP_VCO_NUMER (79)
+/*
+ * To tell where is the VCOs source:
+ * 0 = EOSC1
+ * 1 = EOSC2
+ * 2 = F2S
+ */
+#define CONFIG_HPS_PERPLLGRP_VCO_PSRC (0)
+#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT (3)
+#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT (3)
+#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT (1)
+#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT (19)
+#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT (4)
+#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT (9)
+#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK (0)
+#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK (0)
+#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK (1)
+#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK (1)
+#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK (6249)
+/*
+ * To tell where is the clock source:
+ * 0 = F2S_PERIPH_REF_CLK
+ * 1 = MAIN_CLK
+ * 2 = PERIPH_CLK
+ */
+#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC (1)
+#define CONFIG_HPS_PERPLLGRP_SRC_NAND (2)
+#define CONFIG_HPS_PERPLLGRP_SRC_QSPI (1)
+
+/* SDRAM PLL */
+#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM (2)
+#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER (79)
+/*
+ * To tell where is the VCOs source:
+ * 0 = EOSC1
+ * 1 = EOSC2
+ * 2 = F2S
+ */
+#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC (0)
+#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT (1)
+#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE (0)
+#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT (0)
+#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE (0)
+#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT (1)
+#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE (4)
+#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT (5)
+#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE (0)
+
+/* Info for driver */
+#define CONFIG_HPS_CLK_OSC1_HZ (25000000)
+#define CONFIG_HPS_CLK_MAINVCO_HZ (1600000000)
+#define CONFIG_HPS_CLK_PERVCO_HZ (1000000000)
+#define CONFIG_HPS_CLK_SDRVCO_HZ (600000000)
+#define CONFIG_HPS_CLK_EMAC0_HZ (50000000)
+#define CONFIG_HPS_CLK_EMAC1_HZ (50000000)
+#define CONFIG_HPS_CLK_USBCLK_HZ (200000000)
+#define CONFIG_HPS_CLK_NAND_HZ (100000000)
+#define CONFIG_HPS_CLK_SDMMC_HZ (50000000)
+#define CONFIG_HPS_CLK_QSPI_HZ (400000000)
+#define CONFIG_HPS_CLK_SPIM_HZ (200000000)
+#define CONFIG_HPS_CLK_CAN0_HZ (100000000)
+#define CONFIG_HPS_CLK_CAN1_HZ (100000000)
+#define CONFIG_HPS_CLK_GPIODB_HZ (32000)
+#define CONFIG_HPS_CLK_L4_MP_HZ (100000000)
+#define CONFIG_HPS_CLK_L4_SP_HZ (100000000)
+
+#endif /* _PRELOADER_PLL_CONFIG_H_ */
diff --git a/arch/arm/boards/ebv-socrates/sdram_config.h b/arch/arm/boards/ebv-socrates/sdram_config.h
new file mode 100644
index 0000000..94d1cbe
--- /dev/null
+++ b/arch/arm/boards/ebv-socrates/sdram_config.h
@@ -0,0 +1,73 @@
+#ifndef __SDRAM_CONFIG_H
+#define __SDRAM_CONFIG_H
+
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE (2)
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL (8)
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER (0)
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN (0)
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN (0)
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN (1)
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT (10)
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN (0)
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS (0)
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL (6)
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL (0)
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL (6)
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD (4)
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW (14)
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC (117)
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI (1300)
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD (5)
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP (5)
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR (5)
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR (4)
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP (4)
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS (12)
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC (17)
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD (4)
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD (4)
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT (200)
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT (3)
+#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES (0)
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS (10)
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS (15)
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS (3)
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS (1)
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH (32)
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH (8)
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN (0)
+#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL (2)
+#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA (0)
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH (2)
+#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN (0)
+#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE (0)
+#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC (0)
+#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY (0x3FFD1088)
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 (0x21084210)
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 (0x1EF84)
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 (0x2020)
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 (0x0)
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 (0xF800)
+#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 (0x200)
+
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH (0x44555)
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP (0x2C011000)
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP (0xB00088)
+#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP (0x760210)
+#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP (0x980543)
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR (0x5A56A)
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 (0x20820820)
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 (0x8208208)
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 (0)
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 (0x41041041)
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 (0x410410)
+#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 (0x80808080)
+#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 (0x80808080)
+#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 (0x8080)
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ (0)
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE (1)
+#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST_READ_PORT_USED (0)
+#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST_WRITE_PORT_USED (0)
+#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST_COMMAND_PORT_USED (0)
+
+#endif /*#ifndef__SDRAM_CONFIG_H*/
diff --git a/arch/arm/boards/ebv-socrates/sequencer_auto.h b/arch/arm/boards/ebv-socrates/sequencer_auto.h
new file mode 100644
index 0000000..59aa9cf
--- /dev/null
+++ b/arch/arm/boards/ebv-socrates/sequencer_auto.h
@@ -0,0 +1,174 @@
+#define __RW_MGR_ac_mrs1 0x04
+#define __RW_MGR_ac_mrs3 0x06
+#define __RW_MGR_ac_write_bank_0_col_0_nodata_wl_1 0x1C
+#define __RW_MGR_ac_act_1 0x11
+#define __RW_MGR_ac_write_postdata 0x1A
+#define __RW_MGR_ac_act_0 0x10
+#define __RW_MGR_ac_des 0x0D
+#define __RW_MGR_ac_init_reset_1_cke_0 0x01
+#define __RW_MGR_ac_write_data 0x19
+#define __RW_MGR_ac_init_reset_0_cke_0 0x00
+#define __RW_MGR_ac_read_bank_0_1_norden 0x22
+#define __RW_MGR_ac_pre_all 0x12
+#define __RW_MGR_ac_mrs0_user 0x02
+#define __RW_MGR_ac_mrs0_dll_reset 0x03
+#define __RW_MGR_ac_read_bank_0_0 0x1D
+#define __RW_MGR_ac_write_bank_0_col_1 0x16
+#define __RW_MGR_ac_read_bank_0_1 0x1F
+#define __RW_MGR_ac_write_bank_1_col_0 0x15
+#define __RW_MGR_ac_write_bank_1_col_1 0x17
+#define __RW_MGR_ac_write_bank_0_col_0 0x14
+#define __RW_MGR_ac_read_bank_1_0 0x1E
+#define __RW_MGR_ac_mrs1_mirr 0x0A
+#define __RW_MGR_ac_read_bank_1_1 0x20
+#define __RW_MGR_ac_des_odt_1 0x0E
+#define __RW_MGR_ac_mrs0_dll_reset_mirr 0x09
+#define __RW_MGR_ac_zqcl 0x07
+#define __RW_MGR_ac_write_predata 0x18
+#define __RW_MGR_ac_mrs0_user_mirr 0x08
+#define __RW_MGR_ac_ref 0x13
+#define __RW_MGR_ac_nop 0x0F
+#define __RW_MGR_ac_rdimm 0x23
+#define __RW_MGR_ac_mrs2_mirr 0x0B
+#define __RW_MGR_ac_write_bank_0_col_0_nodata 0x1B
+#define __RW_MGR_ac_read_en 0x21
+#define __RW_MGR_ac_mrs3_mirr 0x0C
+#define __RW_MGR_ac_mrs2 0x05
+#define __RW_MGR_CONTENT_ac_mrs1 0x10090044
+#define __RW_MGR_CONTENT_ac_mrs3 0x100B0000
+#define __RW_MGR_CONTENT_ac_write_bank_0_col_0_nodata_wl_1 0x18980000
+#define __RW_MGR_CONTENT_ac_act_1 0x106B0000
+#define __RW_MGR_CONTENT_ac_write_postdata 0x38780000
+#define __RW_MGR_CONTENT_ac_act_0 0x10680000
+#define __RW_MGR_CONTENT_ac_des 0x30780000
+#define __RW_MGR_CONTENT_ac_init_reset_1_cke_0 0x20780000
+#define __RW_MGR_CONTENT_ac_write_data 0x3CF80000
+#define __RW_MGR_CONTENT_ac_init_reset_0_cke_0 0x20700000
+#define __RW_MGR_CONTENT_ac_read_bank_0_1_norden 0x10580008
+#define __RW_MGR_CONTENT_ac_pre_all 0x10280400
+#define __RW_MGR_CONTENT_ac_mrs0_user 0x10080221
+#define __RW_MGR_CONTENT_ac_mrs0_dll_reset 0x10080320
+#define __RW_MGR_CONTENT_ac_read_bank_0_0 0x13580000
+#define __RW_MGR_CONTENT_ac_write_bank_0_col_1 0x1C980008
+#define __RW_MGR_CONTENT_ac_read_bank_0_1 0x13580008
+#define __RW_MGR_CONTENT_ac_write_bank_1_col_0 0x1C9B0000
+#define __RW_MGR_CONTENT_ac_write_bank_1_col_1 0x1C9B0008
+#define __RW_MGR_CONTENT_ac_write_bank_0_col_0 0x1C980000
+#define __RW_MGR_CONTENT_ac_read_bank_1_0 0x135B0000
+#define __RW_MGR_CONTENT_ac_mrs1_mirr 0x100A0024
+#define __RW_MGR_CONTENT_ac_read_bank_1_1 0x135B0008
+#define __RW_MGR_CONTENT_ac_des_odt_1 0x38780000
+#define __RW_MGR_CONTENT_ac_mrs0_dll_reset_mirr 0x100802C0
+#define __RW_MGR_CONTENT_ac_zqcl 0x10380400
+#define __RW_MGR_CONTENT_ac_write_predata 0x38F80000
+#define __RW_MGR_CONTENT_ac_mrs0_user_mirr 0x10080241
+#define __RW_MGR_CONTENT_ac_ref 0x10480000
+#define __RW_MGR_CONTENT_ac_nop 0x30780000
+#define __RW_MGR_CONTENT_ac_rdimm 0x10780000
+#define __RW_MGR_CONTENT_ac_mrs2_mirr 0x10090010
+#define __RW_MGR_CONTENT_ac_write_bank_0_col_0_nodata 0x18180000
+#define __RW_MGR_CONTENT_ac_read_en 0x33780000
+#define __RW_MGR_CONTENT_ac_mrs3_mirr 0x100B0000
+#define __RW_MGR_CONTENT_ac_mrs2 0x100A0008
+
+#define __RW_MGR_READ_B2B_WAIT2 0x6A
+#define __RW_MGR_LFSR_WR_RD_BANK_0_WAIT 0x31
+#define __RW_MGR_REFRESH_ALL 0x14
+#define __RW_MGR_ZQCL 0x06
+#define __RW_MGR_LFSR_WR_RD_BANK_0_NOP 0x22
+#define __RW_MGR_LFSR_WR_RD_BANK_0_DQS 0x23
+#define __RW_MGR_ACTIVATE_0_AND_1 0x0D
+#define __RW_MGR_MRS2_MIRR 0x0A
+#define __RW_MGR_INIT_RESET_0_CKE_0 0x6E
+#define __RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT 0x45
+#define __RW_MGR_ACTIVATE_1 0x0F
+#define __RW_MGR_MRS2 0x04
+#define __RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1 0x34
+#define __RW_MGR_MRS1 0x03
+#define __RW_MGR_IDLE_LOOP1 0x7C
+#define __RW_MGR_GUARANTEED_WRITE_WAIT2 0x18
+#define __RW_MGR_MRS3 0x05
+#define __RW_MGR_IDLE_LOOP2 0x7B
+#define __RW_MGR_GUARANTEED_WRITE_WAIT1 0x1E
+#define __RW_MGR_LFSR_WR_RD_BANK_0_DATA 0x24
+#define __RW_MGR_GUARANTEED_WRITE_WAIT3 0x1C
+#define __RW_MGR_RDIMM_CMD 0x7A
+#define __RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP 0x36
+#define __RW_MGR_GUARANTEED_WRITE_WAIT0 0x1A
+#define __RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA 0x38
+#define __RW_MGR_GUARANTEED_READ_CONT 0x53
+#define __RW_MGR_MRS3_MIRR 0x0B
+#define __RW_MGR_IDLE 0x00
+#define __RW_MGR_READ_B2B 0x58
+#define __RW_MGR_INIT_RESET_0_CKE_0_inloop 0x6F
+#define __RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS 0x37
+#define __RW_MGR_GUARANTEED_WRITE 0x17
+#define __RW_MGR_PRECHARGE_ALL 0x12
+#define __RW_MGR_INIT_RESET_1_CKE_0_inloop_1 0x74
+#define __RW_MGR_SGLE_READ 0x7E
+#define __RW_MGR_MRS0_USER_MIRR 0x0C
+#define __RW_MGR_RETURN 0x01
+#define __RW_MGR_LFSR_WR_RD_DM_BANK_0 0x35
+#define __RW_MGR_MRS0_USER 0x07
+#define __RW_MGR_GUARANTEED_READ 0x4B
+#define __RW_MGR_MRS0_DLL_RESET_MIRR 0x08
+#define __RW_MGR_INIT_RESET_1_CKE_0 0x73
+#define __RW_MGR_ACTIVATE_0_AND_1_WAIT2 0x10
+#define __RW_MGR_LFSR_WR_RD_BANK_0_WL_1 0x20
+#define __RW_MGR_MRS0_DLL_RESET 0x02
+#define __RW_MGR_ACTIVATE_0_AND_1_WAIT1 0x0E
+#define __RW_MGR_LFSR_WR_RD_BANK_0 0x21
+#define __RW_MGR_CLEAR_DQS_ENABLE 0x48
+#define __RW_MGR_MRS1_MIRR 0x09
+#define __RW_MGR_READ_B2B_WAIT1 0x60
+#define __RW_MGR_CONTENT_READ_B2B_WAIT2 0x00C680
+#define __RW_MGR_CONTENT_LFSR_WR_RD_BANK_0_WAIT 0x00A680
+#define __RW_MGR_CONTENT_REFRESH_ALL 0x000980
+#define __RW_MGR_CONTENT_ZQCL 0x008380
+#define __RW_MGR_CONTENT_LFSR_WR_RD_BANK_0_NOP 0x00E700
+#define __RW_MGR_CONTENT_LFSR_WR_RD_BANK_0_DQS 0x000C00
+#define __RW_MGR_CONTENT_ACTIVATE_0_AND_1 0x000800
+#define __RW_MGR_CONTENT_MRS2_MIRR 0x008580
+#define __RW_MGR_CONTENT_INIT_RESET_0_CKE_0 0x000000
+#define __RW_MGR_CONTENT_LFSR_WR_RD_DM_BANK_0_WAIT 0x00A680
+#define __RW_MGR_CONTENT_ACTIVATE_1 0x000880
+#define __RW_MGR_CONTENT_MRS2 0x008280
+#define __RW_MGR_CONTENT_LFSR_WR_RD_DM_BANK_0_WL_1 0x00CE00
+#define __RW_MGR_CONTENT_MRS1 0x008200
+#define __RW_MGR_CONTENT_IDLE_LOOP1 0x00A680
+#define __RW_MGR_CONTENT_GUARANTEED_WRITE_WAIT2 0x00CCE8
+#define __RW_MGR_CONTENT_MRS3 0x008300
+#define __RW_MGR_CONTENT_IDLE_LOOP2 0x008680
+#define __RW_MGR_CONTENT_GUARANTEED_WRITE_WAIT1 0x00AC88
+#define __RW_MGR_CONTENT_LFSR_WR_RD_BANK_0_DATA 0x020CE0
+#define __RW_MGR_CONTENT_GUARANTEED_WRITE_WAIT3 0x00EC88
+#define __RW_MGR_CONTENT_RDIMM_CMD 0x009180
+#define __RW_MGR_CONTENT_LFSR_WR_RD_DM_BANK_0_NOP 0x00E700
+#define __RW_MGR_CONTENT_GUARANTEED_WRITE_WAIT0 0x008CE8
+#define __RW_MGR_CONTENT_LFSR_WR_RD_DM_BANK_0_DATA 0x030CE0
+#define __RW_MGR_CONTENT_GUARANTEED_READ_CONT 0x001168
+#define __RW_MGR_CONTENT_MRS3_MIRR 0x008600
+#define __RW_MGR_CONTENT_IDLE 0x080000
+#define __RW_MGR_CONTENT_READ_B2B 0x040E88
+#define __RW_MGR_CONTENT_INIT_RESET_0_CKE_0_inloop 0x000000
+#define __RW_MGR_CONTENT_LFSR_WR_RD_DM_BANK_0_DQS 0x000C00
+#define __RW_MGR_CONTENT_GUARANTEED_WRITE 0x000B68
+#define __RW_MGR_CONTENT_PRECHARGE_ALL 0x000900
+#define __RW_MGR_CONTENT_INIT_RESET_1_CKE_0_inloop_1 0x000080
+#define __RW_MGR_CONTENT_SGLE_READ 0x040F08
+#define __RW_MGR_CONTENT_MRS0_USER_MIRR 0x008400
+#define __RW_MGR_CONTENT_RETURN 0x080680
+#define __RW_MGR_CONTENT_LFSR_WR_RD_DM_BANK_0 0x00CD80
+#define __RW_MGR_CONTENT_MRS0_USER 0x008100
+#define __RW_MGR_CONTENT_GUARANTEED_READ 0x001168
+#define __RW_MGR_CONTENT_MRS0_DLL_RESET_MIRR 0x008480
+#define __RW_MGR_CONTENT_INIT_RESET_1_CKE_0 0x000080
+#define __RW_MGR_CONTENT_ACTIVATE_0_AND_1_WAIT2 0x00A680
+#define __RW_MGR_CONTENT_LFSR_WR_RD_BANK_0_WL_1 0x00CE00
+#define __RW_MGR_CONTENT_MRS0_DLL_RESET 0x008180
+#define __RW_MGR_CONTENT_ACTIVATE_0_AND_1_WAIT1 0x008680
+#define __RW_MGR_CONTENT_LFSR_WR_RD_BANK_0 0x00CD80
+#define __RW_MGR_CONTENT_CLEAR_DQS_ENABLE 0x001158
+#define __RW_MGR_CONTENT_MRS1_MIRR 0x008500
+#define __RW_MGR_CONTENT_READ_B2B_WAIT1 0x00A680
+
diff --git a/arch/arm/boards/ebv-socrates/sequencer_auto_ac_init.c b/arch/arm/boards/ebv-socrates/sequencer_auto_ac_init.c
new file mode 100644
index 0000000..5b5196a
--- /dev/null
+++ b/arch/arm/boards/ebv-socrates/sequencer_auto_ac_init.c
@@ -0,0 +1,40 @@
+static const uint32_t ac_rom_init_size = 36;
+static const uint32_t ac_rom_init[36] =
+{
+ 0x20700000,
+ 0x20780000,
+ 0x10080221,
+ 0x10080320,
+ 0x10090044,
+ 0x100a0008,
+ 0x100b0000,
+ 0x10380400,
+ 0x10080241,
+ 0x100802c0,
+ 0x100a0024,
+ 0x10090010,
+ 0x100b0000,
+ 0x30780000,
+ 0x38780000,
+ 0x30780000,
+ 0x10680000,
+ 0x106b0000,
+ 0x10280400,
+ 0x10480000,
+ 0x1c980000,
+ 0x1c9b0000,
+ 0x1c980008,
+ 0x1c9b0008,
+ 0x38f80000,
+ 0x3cf80000,
+ 0x38780000,
+ 0x18180000,
+ 0x18980000,
+ 0x13580000,
+ 0x135b0000,
+ 0x13580008,
+ 0x135b0008,
+ 0x33780000,
+ 0x10580008,
+ 0x10780000
+};
diff --git a/arch/arm/boards/ebv-socrates/sequencer_auto_inst_init.c b/arch/arm/boards/ebv-socrates/sequencer_auto_inst_init.c
new file mode 100644
index 0000000..e261ecb
--- /dev/null
+++ b/arch/arm/boards/ebv-socrates/sequencer_auto_inst_init.c
@@ -0,0 +1,132 @@
+static const uint32_t inst_rom_init_size = 128;
+static const uint32_t inst_rom_init[128] =
+{
+ 0x80000,
+ 0x80680,
+ 0x8180,
+ 0x8200,
+ 0x8280,
+ 0x8300,
+ 0x8380,
+ 0x8100,
+ 0x8480,
+ 0x8500,
+ 0x8580,
+ 0x8600,
+ 0x8400,
+ 0x800,
+ 0x8680,
+ 0x880,
+ 0xa680,
+ 0x80680,
+ 0x900,
+ 0x80680,
+ 0x980,
+ 0x8680,
+ 0x80680,
+ 0xb68,
+ 0xcce8,
+ 0xae8,
+ 0x8ce8,
+ 0xb88,
+ 0xec88,
+ 0xa08,
+ 0xac88,
+ 0x80680,
+ 0xce00,
+ 0xcd80,
+ 0xe700,
+ 0xc00,
+ 0x20ce0,
+ 0x20ce0,
+ 0x20ce0,
+ 0x20ce0,
+ 0xd00,
+ 0x680,
+ 0x680,
+ 0x680,
+ 0x680,
+ 0x60e80,
+ 0x61080,
+ 0x61080,
+ 0x61080,
+ 0xa680,
+ 0x8680,
+ 0x80680,
+ 0xce00,
+ 0xcd80,
+ 0xe700,
+ 0xc00,
+ 0x30ce0,
+ 0x30ce0,
+ 0x30ce0,
+ 0x30ce0,
+ 0xd00,
+ 0x680,
+ 0x680,
+ 0x680,
+ 0x680,
+ 0x70e80,
+ 0x71080,
+ 0x71080,
+ 0x71080,
+ 0xa680,
+ 0x8680,
+ 0x80680,
+ 0x1158,
+ 0x6d8,
+ 0x80680,
+ 0x1168,
+ 0x7e8,
+ 0x7e8,
+ 0x87e8,
+ 0x40fe8,
+ 0x410e8,
+ 0x410e8,
+ 0x410e8,
+ 0x1168,
+ 0x7e8,
+ 0x7e8,
+ 0xa7e8,
+ 0x80680,
+ 0x40e88,
+ 0x41088,
+ 0x41088,
+ 0x41088,
+ 0x40f68,
+ 0x410e8,
+ 0x410e8,
+ 0x410e8,
+ 0xa680,
+ 0x40fe8,
+ 0x410e8,
+ 0x410e8,
+ 0x410e8,
+ 0x41008,
+ 0x41088,
+ 0x41088,
+ 0x41088,
+ 0x1100,
+ 0xc680,
+ 0x8680,
+ 0xe680,
+ 0x80680,
+ 0x0,
+ 0x0,
+ 0xa000,
+ 0x8000,
+ 0x80000,
+ 0x80,
+ 0x80,
+ 0x80,
+ 0x80,
+ 0xa080,
+ 0x8080,
+ 0x80080,
+ 0x9180,
+ 0x8680,
+ 0xa680,
+ 0x80680,
+ 0x40f08,
+ 0x80680
+};
diff --git a/arch/arm/boards/ebv-socrates/sequencer_defines.h b/arch/arm/boards/ebv-socrates/sequencer_defines.h
new file mode 100644
index 0000000..1ebbc48
--- /dev/null
+++ b/arch/arm/boards/ebv-socrates/sequencer_defines.h
@@ -0,0 +1,118 @@
+#ifndef _SEQUENCER_DEFINES_H_
+#define _SEQUENCER_DEFINES_H_
+
+#define AC_ROM_MR1_MIRR 0000000100100
+#define AC_ROM_MR1_OCD_ENABLE
+#define AC_ROM_MR2_MIRR 0000000010000
+#define AC_ROM_MR3_MIRR 0000000000000
+#define AC_ROM_MR0_CALIB
+#define AC_ROM_MR0_DLL_RESET_MIRR 0001011000000
+#define AC_ROM_MR0_DLL_RESET 0001100100000
+#define AC_ROM_MR0_MIRR 0001001000001
+#define AC_ROM_MR0 0001000100001
+#define AC_ROM_MR1 0000001000100
+#define AC_ROM_MR2 0000000001000
+#define AC_ROM_MR3 0000000000000
+#define AFI_CLK_FREQ 334
+#define AFI_RATE_RATIO 1
+#define ARRIAVGZ 0
+#define ARRIAV 0
+#define AVL_CLK_FREQ 67
+#define BFM_MODE 0
+#define BURST2 0
+#define CALIBRATE_BIT_SLIPS 0
+#define CALIB_LFIFO_OFFSET 6
+#define CALIB_VFIFO_OFFSET 4
+#define CYCLONEV 1
+#define DDR2 0
+#define DDR3 1
+#define DDRX 1
+#define DM_PINS_ENABLED 1
+#define ENABLE_ASSERT 0
+#define ENABLE_BRINGUP_DEBUGGING 0
+#define ENABLE_DQS_IN_CENTERING 1
+#define ENABLE_DQS_OUT_CENTERING 0
+#define ENABLE_EXPORT_SEQ_DEBUG_BRIDGE 0
+#define ENABLE_INST_ROM_WRITE 1
+#define ENABLE_MARGIN_REPORT_GEN 0
+#define ENABLE_NON_DESTRUCTIVE_CALIB 0
+#define ENABLE_SUPER_QUICK_CALIBRATION 0
+#define ENABLE_TCL_DEBUG 0
+#define FULL_RATE 1
+#define GUARANTEED_READ_BRINGUP_TEST 0
+#define HALF_RATE 0
+#define HARD_PHY 1
+#define HARD_VFIFO 1
+#define HCX_COMPAT_MODE 0
+#define HHP_HPS_SIMULATION 0
+#define HHP_HPS_VERIFICATION 0
+#define HHP_HPS 1
+#define HPS_HW 1
+#define HR_DDIO_OUT_HAS_THREE_REGS 0
+#define IO_DELAY_PER_DCHAIN_TAP 25
+#define IO_DELAY_PER_DQS_EN_DCHAIN_TAP 25
+#define IO_DELAY_PER_OPA_TAP 375
+#define IO_DLL_CHAIN_LENGTH 8
+#define IO_DM_OUT_RESERVE 0
+#define IO_DQDQS_OUT_PHASE_MAX 0
+#define IO_DQS_EN_DELAY_MAX 31
+#define IO_DQS_EN_DELAY_OFFSET 0
+#define IO_DQS_EN_PHASE_MAX 7
+#define IO_DQS_IN_DELAY_MAX 31
+#define IO_DQS_IN_RESERVE 4
+#define IO_DQS_OUT_RESERVE 4
+#define IO_DQ_OUT_RESERVE 0
+#define IO_IO_IN_DELAY_MAX 31
+#define IO_IO_OUT1_DELAY_MAX 31
+#define IO_IO_OUT2_DELAY_MAX 0
+#define IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS 0
+#define LPDDR1 0
+#define LPDDR2 0
+#define LRDIMM 0
+#define MARGIN_VARIATION_TEST 0
+#define MAX_LATENCY_COUNT_WIDTH 5
+#define MEM_ADDR_WIDTH 13
+#define MULTIPLE_AFI_WLAT 0
+#define NUM_SHADOW_REGS 1
+#define QDRII 0
+#define QUARTER_RATE 0
+#define RDIMM 0
+#define READ_AFTER_WRITE_CALIBRATION 1
+#define READ_VALID_FIFO_SIZE 16
+#define REG_FILE_INIT_SEQ_SIGNATURE 0x55550482
+#define RLDRAM3 0
+#define RLDRAMII 0
+#define RLDRAMX 0
+#define RUNTIME_CAL_REPORT 0
+#define RW_MGR_MEM_ADDRESS_MIRRORING 0
+#define RW_MGR_MEM_ADDRESS_WIDTH 15
+#define RW_MGR_MEM_BANK_WIDTH 3
+#define RW_MGR_MEM_CHIP_SELECT_WIDTH 1
+#define RW_MGR_MEM_CLK_EN_WIDTH 1
+#define RW_MGR_MEM_CONTROL_WIDTH 1
+#define RW_MGR_MEM_DATA_MASK_WIDTH 4
+#define RW_MGR_MEM_DATA_WIDTH 32
+#define RW_MGR_MEM_DQ_PER_READ_DQS 8
+#define RW_MGR_MEM_DQ_PER_WRITE_DQS 8
+#define RW_MGR_MEM_IF_READ_DQS_WIDTH 4
+#define RW_MGR_MEM_IF_WRITE_DQS_WIDTH 4
+#define RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM 1
+#define RW_MGR_MEM_NUMBER_OF_RANKS 1
+#define RW_MGR_MEM_ODT_WIDTH 1
+#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS 1
+#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS 1
+#define RW_MGR_MR0_BL 1
+#define RW_MGR_MR0_CAS_LATENCY 2
+#define RW_MGR_TRUE_MEM_DATA_MASK_WIDTH 4
+#define RW_MGR_WRITE_TO_DEBUG_READ 1.0
+#define SKEW_CALIBRATION 0
+#define STATIC_FULL_CALIBRATION 1
+#define STATIC_SIM_FILESET 0
+#define STATIC_SKIP_MEM_INIT 0
+#define STRATIXV 0
+#define TRACKING_ERROR_TEST 0
+#define TRACKING_WATCH_TEST 0
+#define USE_DQS_TRACKING 1
+#define USE_SHADOW_REGS 0
+
+#endif /* _SEQUENCER_DEFINES_H_ */
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 7aaf61d..7782874 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -11,7 +11,8 @@ dtb-$(CONFIG_ARCH_IMX6) += imx6q-gk802.dtb \
imx6q-mba6x.dtb \
imx6q-phytec-pbab01.dtb
dtb-$(CONFIG_ARCH_MVEBU) += dove-cubox.dtb
-dtb-$(CONFIG_ARCH_SOCFPGA) += socfpga_cyclone5_sockit.dtb
+dtb-$(CONFIG_ARCH_SOCFPGA) += socfpga_cyclone5_sockit.dtb \
+ socfpga_cyclone5_socrates.dtb
BUILTIN_DTB := $(patsubst "%",%,$(CONFIG_BUILTIN_DTB_NAME))
obj-$(CONFIG_BUILTIN_DTB) += $(BUILTIN_DTB).dtb.o
@@ -25,6 +26,7 @@ pbl-$(CONFIG_MACH_REALQ7) += imx6q-dmo-realq7.dtb.o
pbl-$(CONFIG_MACH_SOLIDRUN_CUBOX) += dove-cubox.dtb.o
pbl-$(CONFIG_MACH_GK802) += imx6q-gk802.dtb.o
pbl-$(CONFIG_MACH_TQMA6X) += imx6dl-mba6x.dtb.o imx6q-mba6x.dtb.o
+pbl-$(CONFIG_MACH_SOCFPGA_EBV_SOCRATES) += socfpga_cyclone5_socrates.dtb.o
pbl-$(CONFIG_MACH_SOCFPGA_TERASIC_SOCKIT) += socfpga_cyclone5_sockit.dtb.o
.SECONDARY: $(obj)/$(BUILTIN_DTB).dtb.S
diff --git a/arch/arm/dts/socfpga_cyclone5_socrates.dts b/arch/arm/dts/socfpga_cyclone5_socrates.dts
new file mode 100644
index 0000000..7fa5e63
--- /dev/null
+++ b/arch/arm/dts/socfpga_cyclone5_socrates.dts
@@ -0,0 +1,64 @@
+/*
+ * Copyright (C) 2013 Steffen Trumtrar <s.trumtrar@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/include/ "socfpga_cyclone5.dtsi"
+
+/ {
+ model = "EBV SoCrates";
+ compatible = "ebv,socrates", "altr,socfpga";
+
+ chosen {
+ };
+
+ memory {
+ name = "memory";
+ device_type = "memory";
+ reg = <0x0 0x0>;
+ };
+
+ leds: gpio-leds {
+ };
+};
+
+&leds {
+ compatible = "gpio-leds";
+
+ led@0 {
+ label = "0";
+ gpios = <&gpio0 28 1>;
+ linux,default-trigger = "heartbeat";
+ };
+
+ led@1 {
+ label = "1";
+ gpios = <&gpio1 19 1>;
+ };
+
+ led@2 {
+ label = "2";
+ gpios = <&gpio1 25 1>;
+ };
+};
+
+&gmac1 {
+ phy-mode = "rgmii";
+ status = "okay";
+};
+
+&mmc {
+ status = "okay";
+};
diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index 70d0a4d..18f434c 100644
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -13,6 +13,10 @@ config ARCH_TEXT_BASE
hex
default 0x00100000 if MACH_SOCFPGA_CYCLONE5
+config MACH_SOCFPGA_EBV_SOCRATES
+ select HAVE_DEFAULT_ENVIRONMENT_NEW
+ bool "EBV Socrates"
+
config MACH_SOCFPGA_TERASIC_SOCKIT
select HAVE_DEFAULT_ENVIRONMENT_NEW
bool "Terasic SoCKit"
diff --git a/images/Makefile.socfpga b/images/Makefile.socfpga
index 66aec9d..5eed83c 100644
--- a/images/Makefile.socfpga
+++ b/images/Makefile.socfpga
@@ -19,6 +19,14 @@ pblx-$(CONFIG_MACH_SOCFPGA_TERASIC_SOCKIT) += start_socfpga_sockit
FILE_barebox-socfpga-sockit.img = start_socfpga_sockit.pblx
barebox-$(CONFIG_MACH_SOCFPGA_TERASIC_SOCKIT) += barebox-socfpga-sockit.img
+pblx-$(CONFIG_MACH_SOCFPGA_EBV_SOCRATES) += start_socfpga_socrates_xload
+FILE_barebox-socfpga-socrates-xload.img = start_socfpga_socrates_xload.pblx.socfpgaimg
+xload-$(CONFIG_MACH_SOCFPGA_EBV_SOCRATES) += barebox-socfpga-socrates-xload.img
+
+pblx-$(CONFIG_MACH_SOCFPGA_EBV_SOCRATES) += start_socfpga_socrates
+FILE_barebox-socfpga-socrates.img = start_socfpga_socrates.pblx
+barebox-$(CONFIG_MACH_SOCFPGA_EBV_SOCRATES) += barebox-socfpga-socrates.img
+
ifdef CONFIG_ARCH_SOCFPGA_XLOAD
image-y += $(xload-y)
else
--
1.8.4.rc3
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply related
* [PATCH 09/11] ARM: SoCFPGA: Add Terasic SoCkit board support
From: Sascha Hauer @ 2013-09-16 8:48 UTC (permalink / raw)
To: barebox
In-Reply-To: <1379321300-8085-1-git-send-email-s.hauer@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/boards/Makefile | 1 +
arch/arm/boards/terasic-sockit/Makefile | 2 +
arch/arm/boards/terasic-sockit/board.c | 37 ++++
arch/arm/boards/terasic-sockit/config.h | 1 +
arch/arm/boards/terasic-sockit/lowlevel.c | 99 ++++++++++
arch/arm/boards/terasic-sockit/pinmux_config.c | 211 +++++++++++++++++++++
arch/arm/boards/terasic-sockit/pll_config.h | 98 ++++++++++
arch/arm/boards/terasic-sockit/sdram_config.h | 69 +++++++
arch/arm/boards/terasic-sockit/sequencer_auto.h | 173 +++++++++++++++++
.../boards/terasic-sockit/sequencer_auto_ac_init.c | 40 ++++
.../terasic-sockit/sequencer_auto_inst_init.c | 134 +++++++++++++
arch/arm/boards/terasic-sockit/sequencer_defines.h | 118 ++++++++++++
arch/arm/dts/Makefile | 2 +
arch/arm/dts/socfpga_cyclone5_sockit.dts | 121 ++++++++++++
arch/arm/mach-socfpga/Kconfig | 4 +
images/Makefile.socfpga | 7 +
16 files changed, 1117 insertions(+)
create mode 100644 arch/arm/boards/terasic-sockit/Makefile
create mode 100644 arch/arm/boards/terasic-sockit/board.c
create mode 100644 arch/arm/boards/terasic-sockit/config.h
create mode 100644 arch/arm/boards/terasic-sockit/lowlevel.c
create mode 100644 arch/arm/boards/terasic-sockit/pinmux_config.c
create mode 100644 arch/arm/boards/terasic-sockit/pll_config.h
create mode 100644 arch/arm/boards/terasic-sockit/sdram_config.h
create mode 100644 arch/arm/boards/terasic-sockit/sequencer_auto.h
create mode 100644 arch/arm/boards/terasic-sockit/sequencer_auto_ac_init.c
create mode 100644 arch/arm/boards/terasic-sockit/sequencer_auto_inst_init.c
create mode 100644 arch/arm/boards/terasic-sockit/sequencer_defines.h
create mode 100644 arch/arm/dts/socfpga_cyclone5_sockit.dts
diff --git a/arch/arm/boards/Makefile b/arch/arm/boards/Makefile
index 38ef512..a9bc15f 100644
--- a/arch/arm/boards/Makefile
+++ b/arch/arm/boards/Makefile
@@ -75,6 +75,7 @@ obj-$(CONFIG_MACH_SABRELITE) += freescale-mx6-sabrelite/
obj-$(CONFIG_MACH_SABRESD) += freescale-mx6-sabresd/
obj-$(CONFIG_MACH_SAMA5D3XEK) += sama5d3xek/
obj-$(CONFIG_MACH_SCB9328) += scb9328/
+obj-$(CONFIG_MACH_SOCFPGA_TERASIC_SOCKIT) += terasic-sockit/
obj-$(CONFIG_MACH_TNY_A9260) += tny-a926x/
obj-$(CONFIG_MACH_TNY_A9263) += tny-a926x/
obj-$(CONFIG_MACH_TNY_A9G20) += tny-a926x/
diff --git a/arch/arm/boards/terasic-sockit/Makefile b/arch/arm/boards/terasic-sockit/Makefile
new file mode 100644
index 0000000..8c927fe
--- /dev/null
+++ b/arch/arm/boards/terasic-sockit/Makefile
@@ -0,0 +1,2 @@
+obj-y += lowlevel.o board.o
+pbl-y += lowlevel.o
diff --git a/arch/arm/boards/terasic-sockit/board.c b/arch/arm/boards/terasic-sockit/board.c
new file mode 100644
index 0000000..fdff76f
--- /dev/null
+++ b/arch/arm/boards/terasic-sockit/board.c
@@ -0,0 +1,37 @@
+#include <common.h>
+#include <types.h>
+#include <driver.h>
+#include <init.h>
+#include <asm/armlinux.h>
+#include <linux/micrel_phy.h>
+#include <linux/phy.h>
+#include <sizes.h>
+#include <fcntl.h>
+#include <fs.h>
+#include <mach/socfpga-regs.h>
+
+static int phy_fixup(struct phy_device *dev)
+{
+ /* min rx data delay */
+ phy_write(dev, 0x0b, 0x8105);
+ phy_write(dev, 0x0c, 0x0000);
+
+ /* max rx/tx clock delay, min rx/tx control delay */
+ phy_write(dev, 0x0b, 0x8104);
+ phy_write(dev, 0x0c, 0xa0d0);
+ phy_write(dev, 0x0b, 0x104);
+
+ return 0;
+}
+
+static int socfpga_console_init(void)
+{
+ if (!of_machine_is_compatible("terasic,sockit"))
+ return 0;
+
+ if (IS_ENABLED(CONFIG_PHYLIB))
+ phy_register_fixup_for_uid(PHY_ID_KSZ9021, MICREL_PHY_ID_MASK, phy_fixup);
+
+ return 0;
+}
+console_initcall(socfpga_console_init);
diff --git a/arch/arm/boards/terasic-sockit/config.h b/arch/arm/boards/terasic-sockit/config.h
new file mode 100644
index 0000000..da84fa5
--- /dev/null
+++ b/arch/arm/boards/terasic-sockit/config.h
@@ -0,0 +1 @@
+/* nothing */
diff --git a/arch/arm/boards/terasic-sockit/lowlevel.c b/arch/arm/boards/terasic-sockit/lowlevel.c
new file mode 100644
index 0000000..8a1e0ce
--- /dev/null
+++ b/arch/arm/boards/terasic-sockit/lowlevel.c
@@ -0,0 +1,99 @@
+#include <common.h>
+#include <sizes.h>
+#include <io.h>
+#include <asm/barebox-arm-head.h>
+#include <asm/barebox-arm.h>
+#include <mach/generic.h>
+#include <debug_ll.h>
+#include <asm/cache.h>
+#include "sdram_config.h"
+#include <mach/sdram_config.h>
+#include "pinmux_config.c"
+#include "pll_config.h"
+#include <mach/pll_config.h>
+#include "sequencer_defines.h"
+#include "sequencer_auto.h"
+#include <mach/sequencer.c>
+#include "sequencer_auto_inst_init.c"
+#include "sequencer_auto_ac_init.c"
+
+static inline void ledon(int led)
+{
+ u32 val;
+
+ val = readl(0xFF709000);
+ val |= 1 << (led + 24);
+ writel(val, 0xFF709000);
+
+ val = readl(0xFF709004);
+ val |= 1 << (led + 24);
+ writel(val, 0xFF709004);
+}
+
+static inline void ledoff(int led)
+{
+ u32 val;
+
+ val = readl(0xFF709000);
+ val &= ~(1 << (led + 24));
+ writel(val, 0xFF709000);
+
+ val = readl(0xFF709004);
+ val &= ~(1 << (led + 24));
+ writel(val, 0xFF709004);
+}
+
+extern char __dtb_socfpga_cyclone5_sockit_start[];
+
+ENTRY_FUNCTION(start_socfpga_sockit)(void)
+{
+ uint32_t fdt;
+
+ __barebox_arm_head();
+
+ arm_cpu_lowlevel_init();
+
+ fdt = (uint32_t)__dtb_socfpga_cyclone5_sockit_start - get_runtime_offset();
+
+ barebox_arm_entry(0x0, SZ_1G, fdt);
+}
+
+static noinline void sockit_entry(void)
+{
+ int ret;
+
+ arm_early_mmu_cache_invalidate();
+
+ relocate_to_current_adr();
+ setup_c();
+
+ socfpga_lowlevel_init(&cm_default_cfg,
+ sys_mgr_init_table, ARRAY_SIZE(sys_mgr_init_table));
+
+ puts_ll("lowlevel init done\n");
+ puts_ll("SDRAM setup...\n");
+
+ socfpga_sdram_mmr_init();
+
+ puts_ll("SDRAM calibration...\n");
+
+ ret = socfpga_sdram_calibration(inst_rom_init, inst_rom_init_size,
+ ac_rom_init, ac_rom_init_size);
+ if (ret)
+ hang();
+
+ puts_ll("done\n");
+
+ barebox_arm_entry(0x0, SZ_1G, 0);
+}
+
+ENTRY_FUNCTION(start_socfpga_sockit_xload)(void)
+{
+ __barebox_arm_head();
+
+ arm_cpu_lowlevel_init();
+
+ arm_setup_stack(0xffff0000 + SZ_64K - SZ_4K - 16);
+
+ sockit_entry();
+}
diff --git a/arch/arm/boards/terasic-sockit/pinmux_config.c b/arch/arm/boards/terasic-sockit/pinmux_config.c
new file mode 100644
index 0000000..554fbd8
--- /dev/null
+++ b/arch/arm/boards/terasic-sockit/pinmux_config.c
@@ -0,0 +1,211 @@
+#include <common.h>
+
+unsigned long sys_mgr_init_table[] = {
+ 0, /* EMACIO0 */
+ 2, /* EMACIO1 */
+ 2, /* EMACIO2 */
+ 2, /* EMACIO3 */
+ 2, /* EMACIO4 */
+ 2, /* EMACIO5 */
+ 2, /* EMACIO6 */
+ 2, /* EMACIO7 */
+ 2, /* EMACIO8 */
+ 0, /* EMACIO9 */
+ 2, /* EMACIO10 */
+ 2, /* EMACIO11 */
+ 2, /* EMACIO12 */
+ 2, /* EMACIO13 */
+ 0, /* EMACIO14 */
+ 0, /* EMACIO15 */
+ 0, /* EMACIO16 */
+ 0, /* EMACIO17 */
+ 0, /* EMACIO18 */
+ 0, /* EMACIO19 */
+ 3, /* FLASHIO0 */
+ 0, /* FLASHIO1 */
+ 3, /* FLASHIO2 */
+ 3, /* FLASHIO3 */
+ 0, /* FLASHIO4 */
+ 0, /* FLASHIO5 */
+ 0, /* FLASHIO6 */
+ 0, /* FLASHIO7 */
+ 0, /* FLASHIO8 */
+ 3, /* FLASHIO9 */
+ 3, /* FLASHIO10 */
+ 3, /* FLASHIO11 */
+ 0, /* GENERALIO0 */
+ 1, /* GENERALIO1 */
+ 1, /* GENERALIO2 */
+ 1, /* GENERALIO3 */
+ 1, /* GENERALIO4 */
+ 0, /* GENERALIO5 */
+ 0, /* GENERALIO6 */
+ 0, /* GENERALIO7 */
+ 0, /* GENERALIO8 */
+ 3, /* GENERALIO9 */
+ 3, /* GENERALIO10 */
+ 3, /* GENERALIO11 */
+ 3, /* GENERALIO12 */
+ 0, /* GENERALIO13 */
+ 0, /* GENERALIO14 */
+ 1, /* GENERALIO15 */
+ 1, /* GENERALIO16 */
+ 1, /* GENERALIO17 */
+ 1, /* GENERALIO18 */
+ 0, /* GENERALIO19 */
+ 0, /* GENERALIO20 */
+ 0, /* GENERALIO21 */
+ 0, /* GENERALIO22 */
+ 0, /* GENERALIO23 */
+ 0, /* GENERALIO24 */
+ 0, /* GENERALIO25 */
+ 0, /* GENERALIO26 */
+ 0, /* GENERALIO27 */
+ 0, /* GENERALIO28 */
+ 0, /* GENERALIO29 */
+ 0, /* GENERALIO30 */
+ 0, /* GENERALIO31 */
+ 2, /* MIXED1IO0 */
+ 2, /* MIXED1IO1 */
+ 2, /* MIXED1IO2 */
+ 2, /* MIXED1IO3 */
+ 2, /* MIXED1IO4 */
+ 2, /* MIXED1IO5 */
+ 2, /* MIXED1IO6 */
+ 2, /* MIXED1IO7 */
+ 2, /* MIXED1IO8 */
+ 2, /* MIXED1IO9 */
+ 2, /* MIXED1IO10 */
+ 2, /* MIXED1IO11 */
+ 2, /* MIXED1IO12 */
+ 2, /* MIXED1IO13 */
+ 0, /* MIXED1IO14 */
+ 3, /* MIXED1IO15 */
+ 3, /* MIXED1IO16 */
+ 3, /* MIXED1IO17 */
+ 3, /* MIXED1IO18 */
+ 3, /* MIXED1IO19 */
+ 3, /* MIXED1IO20 */
+ 0, /* MIXED1IO21 */
+ 0, /* MIXED2IO0 */
+ 0, /* MIXED2IO1 */
+ 0, /* MIXED2IO2 */
+ 0, /* MIXED2IO3 */
+ 0, /* MIXED2IO4 */
+ 0, /* MIXED2IO5 */
+ 0, /* MIXED2IO6 */
+ 0, /* MIXED2IO7 */
+ 0, /* GPLINMUX48 */
+ 0, /* GPLINMUX49 */
+ 0, /* GPLINMUX50 */
+ 0, /* GPLINMUX51 */
+ 0, /* GPLINMUX52 */
+ 0, /* GPLINMUX53 */
+ 0, /* GPLINMUX54 */
+ 0, /* GPLINMUX55 */
+ 0, /* GPLINMUX56 */
+ 0, /* GPLINMUX57 */
+ 0, /* GPLINMUX58 */
+ 0, /* GPLINMUX59 */
+ 0, /* GPLINMUX60 */
+ 0, /* GPLINMUX61 */
+ 0, /* GPLINMUX62 */
+ 0, /* GPLINMUX63 */
+ 0, /* GPLINMUX64 */
+ 0, /* GPLINMUX65 */
+ 0, /* GPLINMUX66 */
+ 0, /* GPLINMUX67 */
+ 0, /* GPLINMUX68 */
+ 0, /* GPLINMUX69 */
+ 0, /* GPLINMUX70 */
+ 1, /* GPLMUX0 */
+ 1, /* GPLMUX1 */
+ 1, /* GPLMUX2 */
+ 1, /* GPLMUX3 */
+ 1, /* GPLMUX4 */
+ 1, /* GPLMUX5 */
+ 1, /* GPLMUX6 */
+ 1, /* GPLMUX7 */
+ 1, /* GPLMUX8 */
+ 1, /* GPLMUX9 */
+ 1, /* GPLMUX10 */
+ 1, /* GPLMUX11 */
+ 1, /* GPLMUX12 */
+ 1, /* GPLMUX13 */
+ 1, /* GPLMUX14 */
+ 1, /* GPLMUX15 */
+ 1, /* GPLMUX16 */
+ 1, /* GPLMUX17 */
+ 1, /* GPLMUX18 */
+ 1, /* GPLMUX19 */
+ 1, /* GPLMUX20 */
+ 1, /* GPLMUX21 */
+ 1, /* GPLMUX22 */
+ 1, /* GPLMUX23 */
+ 1, /* GPLMUX24 */
+ 1, /* GPLMUX25 */
+ 1, /* GPLMUX26 */
+ 1, /* GPLMUX27 */
+ 1, /* GPLMUX28 */
+ 1, /* GPLMUX29 */
+ 1, /* GPLMUX30 */
+ 1, /* GPLMUX31 */
+ 1, /* GPLMUX32 */
+ 1, /* GPLMUX33 */
+ 1, /* GPLMUX34 */
+ 1, /* GPLMUX35 */
+ 1, /* GPLMUX36 */
+ 1, /* GPLMUX37 */
+ 1, /* GPLMUX38 */
+ 1, /* GPLMUX39 */
+ 1, /* GPLMUX40 */
+ 1, /* GPLMUX41 */
+ 1, /* GPLMUX42 */
+ 1, /* GPLMUX43 */
+ 1, /* GPLMUX44 */
+ 1, /* GPLMUX45 */
+ 1, /* GPLMUX46 */
+ 1, /* GPLMUX47 */
+ 1, /* GPLMUX48 */
+ 1, /* GPLMUX49 */
+ 1, /* GPLMUX50 */
+ 1, /* GPLMUX51 */
+ 1, /* GPLMUX52 */
+ 1, /* GPLMUX53 */
+ 1, /* GPLMUX54 */
+ 1, /* GPLMUX55 */
+ 1, /* GPLMUX56 */
+ 1, /* GPLMUX57 */
+ 1, /* GPLMUX58 */
+ 1, /* GPLMUX59 */
+ 1, /* GPLMUX60 */
+ 1, /* GPLMUX61 */
+ 1, /* GPLMUX62 */
+ 1, /* GPLMUX63 */
+ 1, /* GPLMUX64 */
+ 1, /* GPLMUX65 */
+ 1, /* GPLMUX66 */
+ 1, /* GPLMUX67 */
+ 1, /* GPLMUX68 */
+ 1, /* GPLMUX69 */
+ 1, /* GPLMUX70 */
+ 0, /* NANDUSEFPGA */
+ 0, /* UART0USEFPGA */
+ 0, /* RGMII1USEFPGA */
+ 0, /* SPIS0USEFPGA */
+ 0, /* CAN0USEFPGA */
+ 0, /* I2C0USEFPGA */
+ 0, /* SDMMCUSEFPGA */
+ 0, /* QSPIUSEFPGA */
+ 0, /* SPIS1USEFPGA */
+ 0, /* RGMII0USEFPGA */
+ 0, /* UART1USEFPGA */
+ 0, /* CAN1USEFPGA */
+ 0, /* USB1USEFPGA */
+ 0, /* I2C3USEFPGA */
+ 0, /* I2C2USEFPGA */
+ 0, /* I2C1USEFPGA */
+ 0, /* SPIM1USEFPGA */
+ 0, /* USB0USEFPGA */
+ 0 /* SPIM0USEFPGA */
+};
diff --git a/arch/arm/boards/terasic-sockit/pll_config.h b/arch/arm/boards/terasic-sockit/pll_config.h
new file mode 100644
index 0000000..732f241
--- /dev/null
+++ b/arch/arm/boards/terasic-sockit/pll_config.h
@@ -0,0 +1,98 @@
+
+#ifndef _PRELOADER_PLL_CONFIG_H_
+#define _PRELOADER_PLL_CONFIG_H_
+
+/* PLL configuration data */
+/* Main PLL */
+#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM (0)
+#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER (63)
+#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT (0)
+#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT (0)
+#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT (0)
+#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT (3)
+#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT (3)
+#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT (15)
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK (1)
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK (1)
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK (1)
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK (1)
+#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK (0)
+#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK (1)
+#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK (0)
+/*
+ * To tell where is the clock source:
+ * 0 = MAINPLL
+ * 1 = PERIPHPLL
+ */
+#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP (1)
+#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP (1)
+
+/* Peripheral PLL */
+#define CONFIG_HPS_PERPLLGRP_VCO_DENOM (1)
+#define CONFIG_HPS_PERPLLGRP_VCO_NUMER (79)
+/*
+ * To tell where is the VCOs source:
+ * 0 = EOSC1
+ * 1 = EOSC2
+ * 2 = F2S
+ */
+#define CONFIG_HPS_PERPLLGRP_VCO_PSRC (0)
+#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT (3)
+#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT (3)
+#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT (1)
+#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT (19)
+#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT (4)
+#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT (9)
+#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK (0)
+#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK (0)
+#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK (1)
+#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK (1)
+#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK (6249)
+/*
+ * To tell where is the clock source:
+ * 0 = F2S_PERIPH_REF_CLK
+ * 1 = MAIN_CLK
+ * 2 = PERIPH_CLK
+ */
+#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC (1)
+#define CONFIG_HPS_PERPLLGRP_SRC_NAND (2)
+#define CONFIG_HPS_PERPLLGRP_SRC_QSPI (1)
+
+/* SDRAM PLL */
+#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM (0)
+#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER (31)
+/*
+ * To tell where is the VCOs source:
+ * 0 = EOSC1
+ * 1 = EOSC2
+ * 2 = F2S
+ */
+#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC (0)
+#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT (1)
+#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE (0)
+#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT (0)
+#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE (0)
+#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT (1)
+#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE (4)
+#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT (5)
+#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE (0)
+
+/* Info for driver */
+#define CONFIG_HPS_CLK_OSC1_HZ (25000000)
+#define CONFIG_HPS_CLK_MAINVCO_HZ (1600000000)
+#define CONFIG_HPS_CLK_PERVCO_HZ (1000000000)
+#define CONFIG_HPS_CLK_SDRVCO_HZ (600000000)
+#define CONFIG_HPS_CLK_EMAC0_HZ (50000000)
+#define CONFIG_HPS_CLK_EMAC1_HZ (50000000)
+#define CONFIG_HPS_CLK_USBCLK_HZ (200000000)
+#define CONFIG_HPS_CLK_NAND_HZ (100000000)
+#define CONFIG_HPS_CLK_SDMMC_HZ (50000000)
+#define CONFIG_HPS_CLK_QSPI_HZ (400000000)
+#define CONFIG_HPS_CLK_SPIM_HZ (200000000)
+#define CONFIG_HPS_CLK_CAN0_HZ (100000000)
+#define CONFIG_HPS_CLK_CAN1_HZ (100000000)
+#define CONFIG_HPS_CLK_GPIODB_HZ (32000)
+#define CONFIG_HPS_CLK_L4_MP_HZ (100000000)
+#define CONFIG_HPS_CLK_L4_SP_HZ (100000000)
+
+#endif /* _PRELOADER_PLL_CONFIG_H_ */
diff --git a/arch/arm/boards/terasic-sockit/sdram_config.h b/arch/arm/boards/terasic-sockit/sdram_config.h
new file mode 100644
index 0000000..3d6f938
--- /dev/null
+++ b/arch/arm/boards/terasic-sockit/sdram_config.h
@@ -0,0 +1,69 @@
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE (2)
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL (8)
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER (0)
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN (0)
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN (0)
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN (1)
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT (10)
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN (0)
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS (0)
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL (8)
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL (0)
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL (11)
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD (3)
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW (12)
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC (104)
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI (3120)
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD (6)
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP (6)
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR (6)
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR (4)
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP (3)
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS (14)
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC (20)
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD (4)
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD (4)
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT (200)
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT (3)
+#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES (0)
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS (10)
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS (15)
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS (3)
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS (1)
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH (32)
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH (8)
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN (0)
+#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL (2)
+#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA (0)
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH (2)
+#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN (0)
+#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE (0)
+#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC (0)
+#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY (0x3FFD1088)
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 (0x21084210)
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 (0x1EF84)
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 (0x2020)
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 (0x0)
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 (0xF800)
+#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 (0x200)
+
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH (0x44555)
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP (0x2C011000)
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP (0xB00088)
+#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP (0x760210)
+#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP (0x980543)
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR (0x5A56A)
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 (0x20820820)
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 (0x8208208)
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 (0)
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 (0x41041041)
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 (0x410410)
+#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 (0x80808080)
+#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 (0x80808080)
+#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 (0x8080)
+
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ (0)
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE (1)
+#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST_READ_PORT_USED (0)
+#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST_WRITE_PORT_USED (0)
+#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST_COMMAND_PORT_USED (0)
diff --git a/arch/arm/boards/terasic-sockit/sequencer_auto.h b/arch/arm/boards/terasic-sockit/sequencer_auto.h
new file mode 100644
index 0000000..492706f
--- /dev/null
+++ b/arch/arm/boards/terasic-sockit/sequencer_auto.h
@@ -0,0 +1,173 @@
+#define __RW_MGR_ac_mrs1 0x04
+#define __RW_MGR_ac_mrs3 0x06
+#define __RW_MGR_ac_write_bank_0_col_0_nodata_wl_1 0x1C
+#define __RW_MGR_ac_act_1 0x11
+#define __RW_MGR_ac_write_postdata 0x1A
+#define __RW_MGR_ac_act_0 0x10
+#define __RW_MGR_ac_des 0x0D
+#define __RW_MGR_ac_init_reset_1_cke_0 0x01
+#define __RW_MGR_ac_write_data 0x19
+#define __RW_MGR_ac_init_reset_0_cke_0 0x00
+#define __RW_MGR_ac_read_bank_0_1_norden 0x22
+#define __RW_MGR_ac_pre_all 0x12
+#define __RW_MGR_ac_mrs0_user 0x02
+#define __RW_MGR_ac_mrs0_dll_reset 0x03
+#define __RW_MGR_ac_read_bank_0_0 0x1D
+#define __RW_MGR_ac_write_bank_0_col_1 0x16
+#define __RW_MGR_ac_read_bank_0_1 0x1F
+#define __RW_MGR_ac_write_bank_1_col_0 0x15
+#define __RW_MGR_ac_write_bank_1_col_1 0x17
+#define __RW_MGR_ac_write_bank_0_col_0 0x14
+#define __RW_MGR_ac_read_bank_1_0 0x1E
+#define __RW_MGR_ac_mrs1_mirr 0x0A
+#define __RW_MGR_ac_read_bank_1_1 0x20
+#define __RW_MGR_ac_des_odt_1 0x0E
+#define __RW_MGR_ac_mrs0_dll_reset_mirr 0x09
+#define __RW_MGR_ac_zqcl 0x07
+#define __RW_MGR_ac_write_predata 0x18
+#define __RW_MGR_ac_mrs0_user_mirr 0x08
+#define __RW_MGR_ac_ref 0x13
+#define __RW_MGR_ac_nop 0x0F
+#define __RW_MGR_ac_rdimm 0x23
+#define __RW_MGR_ac_mrs2_mirr 0x0B
+#define __RW_MGR_ac_write_bank_0_col_0_nodata 0x1B
+#define __RW_MGR_ac_read_en 0x21
+#define __RW_MGR_ac_mrs3_mirr 0x0C
+#define __RW_MGR_ac_mrs2 0x05
+#define __RW_MGR_CONTENT_ac_mrs1 0x10090006
+#define __RW_MGR_CONTENT_ac_mrs3 0x100B0000
+#define __RW_MGR_CONTENT_ac_write_bank_0_col_0_nodata_wl_1 0x18980000
+#define __RW_MGR_CONTENT_ac_act_1 0x106B0000
+#define __RW_MGR_CONTENT_ac_write_postdata 0x38780000
+#define __RW_MGR_CONTENT_ac_act_0 0x10680000
+#define __RW_MGR_CONTENT_ac_des 0x30780000
+#define __RW_MGR_CONTENT_ac_init_reset_1_cke_0 0x20780000
+#define __RW_MGR_CONTENT_ac_write_data 0x3CF80000
+#define __RW_MGR_CONTENT_ac_init_reset_0_cke_0 0x20700000
+#define __RW_MGR_CONTENT_ac_read_bank_0_1_norden 0x10580008
+#define __RW_MGR_CONTENT_ac_pre_all 0x10280400
+#define __RW_MGR_CONTENT_ac_mrs0_user 0x10080471
+#define __RW_MGR_CONTENT_ac_mrs0_dll_reset 0x10080570
+#define __RW_MGR_CONTENT_ac_read_bank_0_0 0x13580000
+#define __RW_MGR_CONTENT_ac_write_bank_0_col_1 0x1C980008
+#define __RW_MGR_CONTENT_ac_read_bank_0_1 0x13580008
+#define __RW_MGR_CONTENT_ac_write_bank_1_col_0 0x1C9B0000
+#define __RW_MGR_CONTENT_ac_write_bank_1_col_1 0x1C9B0008
+#define __RW_MGR_CONTENT_ac_write_bank_0_col_0 0x1C980000
+#define __RW_MGR_CONTENT_ac_read_bank_1_0 0x135B0000
+#define __RW_MGR_CONTENT_ac_mrs1_mirr 0x100A0006
+#define __RW_MGR_CONTENT_ac_read_bank_1_1 0x135B0008
+#define __RW_MGR_CONTENT_ac_des_odt_1 0x38780000
+#define __RW_MGR_CONTENT_ac_mrs0_dll_reset_mirr 0x100804E8
+#define __RW_MGR_CONTENT_ac_zqcl 0x10380400
+#define __RW_MGR_CONTENT_ac_write_predata 0x38F80000
+#define __RW_MGR_CONTENT_ac_mrs0_user_mirr 0x10080469
+#define __RW_MGR_CONTENT_ac_ref 0x10480000
+#define __RW_MGR_CONTENT_ac_nop 0x30780000
+#define __RW_MGR_CONTENT_ac_rdimm 0x10780000
+#define __RW_MGR_CONTENT_ac_mrs2_mirr 0x10090218
+#define __RW_MGR_CONTENT_ac_write_bank_0_col_0_nodata 0x18180000
+#define __RW_MGR_CONTENT_ac_read_en 0x33780000
+#define __RW_MGR_CONTENT_ac_mrs3_mirr 0x100B0000
+#define __RW_MGR_CONTENT_ac_mrs2 0x100A0218
+
+#define __RW_MGR_READ_B2B_WAIT2 0x6A
+#define __RW_MGR_LFSR_WR_RD_BANK_0_WAIT 0x31
+#define __RW_MGR_REFRESH_ALL 0x14
+#define __RW_MGR_ZQCL 0x06
+#define __RW_MGR_LFSR_WR_RD_BANK_0_NOP 0x22
+#define __RW_MGR_LFSR_WR_RD_BANK_0_DQS 0x23
+#define __RW_MGR_ACTIVATE_0_AND_1 0x0D
+#define __RW_MGR_MRS2_MIRR 0x0A
+#define __RW_MGR_INIT_RESET_0_CKE_0 0x6E
+#define __RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT 0x45
+#define __RW_MGR_ACTIVATE_1 0x0F
+#define __RW_MGR_MRS2 0x04
+#define __RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1 0x34
+#define __RW_MGR_MRS1 0x03
+#define __RW_MGR_IDLE_LOOP1 0x7C
+#define __RW_MGR_GUARANTEED_WRITE_WAIT2 0x18
+#define __RW_MGR_MRS3 0x05
+#define __RW_MGR_IDLE_LOOP2 0x7B
+#define __RW_MGR_GUARANTEED_WRITE_WAIT1 0x1E
+#define __RW_MGR_LFSR_WR_RD_BANK_0_DATA 0x24
+#define __RW_MGR_GUARANTEED_WRITE_WAIT3 0x1C
+#define __RW_MGR_RDIMM_CMD 0x7A
+#define __RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP 0x36
+#define __RW_MGR_GUARANTEED_WRITE_WAIT0 0x1A
+#define __RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA 0x38
+#define __RW_MGR_GUARANTEED_READ_CONT 0x53
+#define __RW_MGR_MRS3_MIRR 0x0B
+#define __RW_MGR_IDLE 0x00
+#define __RW_MGR_READ_B2B 0x58
+#define __RW_MGR_INIT_RESET_0_CKE_0_inloop 0x6F
+#define __RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS 0x37
+#define __RW_MGR_GUARANTEED_WRITE 0x17
+#define __RW_MGR_PRECHARGE_ALL 0x12
+#define __RW_MGR_INIT_RESET_1_CKE_0_inloop_1 0x74
+#define __RW_MGR_SGLE_READ 0x7E
+#define __RW_MGR_MRS0_USER_MIRR 0x0C
+#define __RW_MGR_RETURN 0x01
+#define __RW_MGR_LFSR_WR_RD_DM_BANK_0 0x35
+#define __RW_MGR_MRS0_USER 0x07
+#define __RW_MGR_GUARANTEED_READ 0x4B
+#define __RW_MGR_MRS0_DLL_RESET_MIRR 0x08
+#define __RW_MGR_INIT_RESET_1_CKE_0 0x73
+#define __RW_MGR_ACTIVATE_0_AND_1_WAIT2 0x10
+#define __RW_MGR_LFSR_WR_RD_BANK_0_WL_1 0x20
+#define __RW_MGR_MRS0_DLL_RESET 0x02
+#define __RW_MGR_ACTIVATE_0_AND_1_WAIT1 0x0E
+#define __RW_MGR_LFSR_WR_RD_BANK_0 0x21
+#define __RW_MGR_CLEAR_DQS_ENABLE 0x48
+#define __RW_MGR_MRS1_MIRR 0x09
+#define __RW_MGR_READ_B2B_WAIT1 0x60
+#define __RW_MGR_CONTENT_READ_B2B_WAIT2 0x00C680
+#define __RW_MGR_CONTENT_LFSR_WR_RD_BANK_0_WAIT 0x00A680
+#define __RW_MGR_CONTENT_REFRESH_ALL 0x000980
+#define __RW_MGR_CONTENT_ZQCL 0x008380
+#define __RW_MGR_CONTENT_LFSR_WR_RD_BANK_0_NOP 0x00E700
+#define __RW_MGR_CONTENT_LFSR_WR_RD_BANK_0_DQS 0x000C00
+#define __RW_MGR_CONTENT_ACTIVATE_0_AND_1 0x000800
+#define __RW_MGR_CONTENT_MRS2_MIRR 0x008580
+#define __RW_MGR_CONTENT_INIT_RESET_0_CKE_0 0x000000
+#define __RW_MGR_CONTENT_LFSR_WR_RD_DM_BANK_0_WAIT 0x00A680
+#define __RW_MGR_CONTENT_ACTIVATE_1 0x000880
+#define __RW_MGR_CONTENT_MRS2 0x008280
+#define __RW_MGR_CONTENT_LFSR_WR_RD_DM_BANK_0_WL_1 0x00CE00
+#define __RW_MGR_CONTENT_MRS1 0x008200
+#define __RW_MGR_CONTENT_IDLE_LOOP1 0x00A680
+#define __RW_MGR_CONTENT_GUARANTEED_WRITE_WAIT2 0x00CCE8
+#define __RW_MGR_CONTENT_MRS3 0x008300
+#define __RW_MGR_CONTENT_IDLE_LOOP2 0x008680
+#define __RW_MGR_CONTENT_GUARANTEED_WRITE_WAIT1 0x00AC88
+#define __RW_MGR_CONTENT_LFSR_WR_RD_BANK_0_DATA 0x020CE0
+#define __RW_MGR_CONTENT_GUARANTEED_WRITE_WAIT3 0x00EC88
+#define __RW_MGR_CONTENT_RDIMM_CMD 0x009180
+#define __RW_MGR_CONTENT_LFSR_WR_RD_DM_BANK_0_NOP 0x00E700
+#define __RW_MGR_CONTENT_GUARANTEED_WRITE_WAIT0 0x008CE8
+#define __RW_MGR_CONTENT_LFSR_WR_RD_DM_BANK_0_DATA 0x030CE0
+#define __RW_MGR_CONTENT_GUARANTEED_READ_CONT 0x001168
+#define __RW_MGR_CONTENT_MRS3_MIRR 0x008600
+#define __RW_MGR_CONTENT_IDLE 0x080000
+#define __RW_MGR_CONTENT_READ_B2B 0x040E88
+#define __RW_MGR_CONTENT_INIT_RESET_0_CKE_0_inloop 0x000000
+#define __RW_MGR_CONTENT_LFSR_WR_RD_DM_BANK_0_DQS 0x000C00
+#define __RW_MGR_CONTENT_GUARANTEED_WRITE 0x000B68
+#define __RW_MGR_CONTENT_PRECHARGE_ALL 0x000900
+#define __RW_MGR_CONTENT_INIT_RESET_1_CKE_0_inloop_1 0x000080
+#define __RW_MGR_CONTENT_SGLE_READ 0x040F08
+#define __RW_MGR_CONTENT_MRS0_USER_MIRR 0x008400
+#define __RW_MGR_CONTENT_RETURN 0x080680
+#define __RW_MGR_CONTENT_LFSR_WR_RD_DM_BANK_0 0x00CD80
+#define __RW_MGR_CONTENT_MRS0_USER 0x008100
+#define __RW_MGR_CONTENT_GUARANTEED_READ 0x001168
+#define __RW_MGR_CONTENT_MRS0_DLL_RESET_MIRR 0x008480
+#define __RW_MGR_CONTENT_INIT_RESET_1_CKE_0 0x000080
+#define __RW_MGR_CONTENT_ACTIVATE_0_AND_1_WAIT2 0x00A680
+#define __RW_MGR_CONTENT_LFSR_WR_RD_BANK_0_WL_1 0x00CE00
+#define __RW_MGR_CONTENT_MRS0_DLL_RESET 0x008180
+#define __RW_MGR_CONTENT_ACTIVATE_0_AND_1_WAIT1 0x008680
+#define __RW_MGR_CONTENT_LFSR_WR_RD_BANK_0 0x00CD80
+#define __RW_MGR_CONTENT_CLEAR_DQS_ENABLE 0x001158
+#define __RW_MGR_CONTENT_MRS1_MIRR 0x008500
+#define __RW_MGR_CONTENT_READ_B2B_WAIT1 0x00A680
diff --git a/arch/arm/boards/terasic-sockit/sequencer_auto_ac_init.c b/arch/arm/boards/terasic-sockit/sequencer_auto_ac_init.c
new file mode 100644
index 0000000..5b0c3f3
--- /dev/null
+++ b/arch/arm/boards/terasic-sockit/sequencer_auto_ac_init.c
@@ -0,0 +1,40 @@
+static const uint32_t ac_rom_init_size = 36;
+static const uint32_t ac_rom_init[36] =
+{
+ 0x20700000,
+ 0x20780000,
+ 0x10080471,
+ 0x10080570,
+ 0x10090006,
+ 0x100a0218,
+ 0x100b0000,
+ 0x10380400,
+ 0x10080469,
+ 0x100804e8,
+ 0x100a0006,
+ 0x10090218,
+ 0x100b0000,
+ 0x30780000,
+ 0x38780000,
+ 0x30780000,
+ 0x10680000,
+ 0x106b0000,
+ 0x10280400,
+ 0x10480000,
+ 0x1c980000,
+ 0x1c9b0000,
+ 0x1c980008,
+ 0x1c9b0008,
+ 0x38f80000,
+ 0x3cf80000,
+ 0x38780000,
+ 0x18180000,
+ 0x18980000,
+ 0x13580000,
+ 0x135b0000,
+ 0x13580008,
+ 0x135b0008,
+ 0x33780000,
+ 0x10580008,
+ 0x10780000
+};
diff --git a/arch/arm/boards/terasic-sockit/sequencer_auto_inst_init.c b/arch/arm/boards/terasic-sockit/sequencer_auto_inst_init.c
new file mode 100644
index 0000000..7815faa
--- /dev/null
+++ b/arch/arm/boards/terasic-sockit/sequencer_auto_inst_init.c
@@ -0,0 +1,134 @@
+#include <common.h>
+
+const uint32_t inst_rom_init_size = 128;
+const uint32_t inst_rom_init[128] =
+{
+ 0x80000,
+ 0x80680,
+ 0x8180,
+ 0x8200,
+ 0x8280,
+ 0x8300,
+ 0x8380,
+ 0x8100,
+ 0x8480,
+ 0x8500,
+ 0x8580,
+ 0x8600,
+ 0x8400,
+ 0x800,
+ 0x8680,
+ 0x880,
+ 0xa680,
+ 0x80680,
+ 0x900,
+ 0x80680,
+ 0x980,
+ 0x8680,
+ 0x80680,
+ 0xb68,
+ 0xcce8,
+ 0xae8,
+ 0x8ce8,
+ 0xb88,
+ 0xec88,
+ 0xa08,
+ 0xac88,
+ 0x80680,
+ 0xce00,
+ 0xcd80,
+ 0xe700,
+ 0xc00,
+ 0x20ce0,
+ 0x20ce0,
+ 0x20ce0,
+ 0x20ce0,
+ 0xd00,
+ 0x680,
+ 0x680,
+ 0x680,
+ 0x680,
+ 0x60e80,
+ 0x61080,
+ 0x61080,
+ 0x61080,
+ 0xa680,
+ 0x8680,
+ 0x80680,
+ 0xce00,
+ 0xcd80,
+ 0xe700,
+ 0xc00,
+ 0x30ce0,
+ 0x30ce0,
+ 0x30ce0,
+ 0x30ce0,
+ 0xd00,
+ 0x680,
+ 0x680,
+ 0x680,
+ 0x680,
+ 0x70e80,
+ 0x71080,
+ 0x71080,
+ 0x71080,
+ 0xa680,
+ 0x8680,
+ 0x80680,
+ 0x1158,
+ 0x6d8,
+ 0x80680,
+ 0x1168,
+ 0x7e8,
+ 0x7e8,
+ 0x87e8,
+ 0x40fe8,
+ 0x410e8,
+ 0x410e8,
+ 0x410e8,
+ 0x1168,
+ 0x7e8,
+ 0x7e8,
+ 0xa7e8,
+ 0x80680,
+ 0x40e88,
+ 0x41088,
+ 0x41088,
+ 0x41088,
+ 0x40f68,
+ 0x410e8,
+ 0x410e8,
+ 0x410e8,
+ 0xa680,
+ 0x40fe8,
+ 0x410e8,
+ 0x410e8,
+ 0x410e8,
+ 0x41008,
+ 0x41088,
+ 0x41088,
+ 0x41088,
+ 0x1100,
+ 0xc680,
+ 0x8680,
+ 0xe680,
+ 0x80680,
+ 0x0,
+ 0x0,
+ 0xa000,
+ 0x8000,
+ 0x80000,
+ 0x80,
+ 0x80,
+ 0x80,
+ 0x80,
+ 0xa080,
+ 0x8080,
+ 0x80080,
+ 0x9180,
+ 0x8680,
+ 0xa680,
+ 0x80680,
+ 0x40f08,
+ 0x80680
+};
diff --git a/arch/arm/boards/terasic-sockit/sequencer_defines.h b/arch/arm/boards/terasic-sockit/sequencer_defines.h
new file mode 100644
index 0000000..a59eed2
--- /dev/null
+++ b/arch/arm/boards/terasic-sockit/sequencer_defines.h
@@ -0,0 +1,118 @@
+#ifndef _SEQUENCER_DEFINES_H_
+#define _SEQUENCER_DEFINES_H_
+
+#define AC_ROM_MR1_MIRR 0000000000110
+#define AC_ROM_MR1_OCD_ENABLE
+#define AC_ROM_MR2_MIRR 0001000011000
+#define AC_ROM_MR3_MIRR 0000000000000
+#define AC_ROM_MR0_CALIB
+#define AC_ROM_MR0_DLL_RESET_MIRR 0010011101000
+#define AC_ROM_MR0_DLL_RESET 0010101110000
+#define AC_ROM_MR0_MIRR 0010001101001
+#define AC_ROM_MR0 0010001110001
+#define AC_ROM_MR1 0000000000110
+#define AC_ROM_MR2 0001000011000
+#define AC_ROM_MR3 0000000000000
+#define AFI_CLK_FREQ 401
+#define AFI_RATE_RATIO 1
+#define ARRIAVGZ 0
+#define ARRIAV 0
+#define AVL_CLK_FREQ 67
+#define BFM_MODE 0
+#define BURST2 0
+#define CALIBRATE_BIT_SLIPS 0
+#define CALIB_LFIFO_OFFSET 11
+#define CALIB_VFIFO_OFFSET 9
+#define CYCLONEV 1
+#define DDR2 0
+#define DDR3 1
+#define DDRX 1
+#define DM_PINS_ENABLED 1
+#define ENABLE_ASSERT 0
+#define ENABLE_BRINGUP_DEBUGGING 0
+#define ENABLE_DQS_IN_CENTERING 1
+#define ENABLE_DQS_OUT_CENTERING 0
+#define ENABLE_EXPORT_SEQ_DEBUG_BRIDGE 0
+#define ENABLE_INST_ROM_WRITE 1
+#define ENABLE_MARGIN_REPORT_GEN 0
+#define ENABLE_NON_DESTRUCTIVE_CALIB 0
+#define ENABLE_SUPER_QUICK_CALIBRATION 0
+#define ENABLE_TCL_DEBUG 0
+#define FULL_RATE 1
+#define GUARANTEED_READ_BRINGUP_TEST 0
+#define HALF_RATE 0
+#define HARD_PHY 1
+#define HARD_VFIFO 1
+#define HCX_COMPAT_MODE 0
+#define HHP_HPS_SIMULATION 0
+#define HHP_HPS_VERIFICATION 0
+#define HHP_HPS 1
+#define HPS_HW 1
+#define HR_DDIO_OUT_HAS_THREE_REGS 0
+#define IO_DELAY_PER_DCHAIN_TAP 25
+#define IO_DELAY_PER_DQS_EN_DCHAIN_TAP 25
+#define IO_DELAY_PER_OPA_TAP 312
+#define IO_DLL_CHAIN_LENGTH 8
+#define IO_DM_OUT_RESERVE 0
+#define IO_DQDQS_OUT_PHASE_MAX 0
+#define IO_DQS_EN_DELAY_MAX 31
+#define IO_DQS_EN_DELAY_OFFSET 0
+#define IO_DQS_EN_PHASE_MAX 7
+#define IO_DQS_IN_DELAY_MAX 31
+#define IO_DQS_IN_RESERVE 4
+#define IO_DQS_OUT_RESERVE 4
+#define IO_DQ_OUT_RESERVE 0
+#define IO_IO_IN_DELAY_MAX 31
+#define IO_IO_OUT1_DELAY_MAX 31
+#define IO_IO_OUT2_DELAY_MAX 0
+#define IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS 0
+#define LPDDR1 0
+#define LPDDR2 0
+#define LRDIMM 0
+#define MARGIN_VARIATION_TEST 0
+#define MAX_LATENCY_COUNT_WIDTH 5
+#define MEM_ADDR_WIDTH 13
+#define MULTIPLE_AFI_WLAT 0
+#define NUM_SHADOW_REGS 1
+#define QDRII 0
+#define QUARTER_RATE 0
+#define RDIMM 0
+#define READ_AFTER_WRITE_CALIBRATION 1
+#define READ_VALID_FIFO_SIZE 16
+#define REG_FILE_INIT_SEQ_SIGNATURE 0x55550482
+#define RLDRAM3 0
+#define RLDRAMII 0
+#define RLDRAMX 0
+#define RUNTIME_CAL_REPORT 0
+#define RW_MGR_MEM_ADDRESS_MIRRORING 0
+#define RW_MGR_MEM_ADDRESS_WIDTH 15
+#define RW_MGR_MEM_BANK_WIDTH 3
+#define RW_MGR_MEM_CHIP_SELECT_WIDTH 1
+#define RW_MGR_MEM_CLK_EN_WIDTH 1
+#define RW_MGR_MEM_CONTROL_WIDTH 1
+#define RW_MGR_MEM_DATA_MASK_WIDTH 4
+#define RW_MGR_MEM_DATA_WIDTH 32
+#define RW_MGR_MEM_DQ_PER_READ_DQS 8
+#define RW_MGR_MEM_DQ_PER_WRITE_DQS 8
+#define RW_MGR_MEM_IF_READ_DQS_WIDTH 4
+#define RW_MGR_MEM_IF_WRITE_DQS_WIDTH 4
+#define RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM 1
+#define RW_MGR_MEM_NUMBER_OF_RANKS 1
+#define RW_MGR_MEM_ODT_WIDTH 1
+#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS 1
+#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS 1
+#define RW_MGR_MR0_BL 1
+#define RW_MGR_MR0_CAS_LATENCY 7
+#define RW_MGR_TRUE_MEM_DATA_MASK_WIDTH 4
+#define RW_MGR_WRITE_TO_DEBUG_READ 1.0
+#define SKEW_CALIBRATION 0
+#define STATIC_FULL_CALIBRATION 1
+#define STATIC_SIM_FILESET 0
+#define STATIC_SKIP_MEM_INIT 0
+#define STRATIXV 0
+#define TRACKING_ERROR_TEST 0
+#define TRACKING_WATCH_TEST 0
+#define USE_DQS_TRACKING 1
+#define USE_SHADOW_REGS 0
+
+#endif /* _SEQUENCER_DEFINES_H_ */
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index d57db0e..7aaf61d 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -11,6 +11,7 @@ dtb-$(CONFIG_ARCH_IMX6) += imx6q-gk802.dtb \
imx6q-mba6x.dtb \
imx6q-phytec-pbab01.dtb
dtb-$(CONFIG_ARCH_MVEBU) += dove-cubox.dtb
+dtb-$(CONFIG_ARCH_SOCFPGA) += socfpga_cyclone5_sockit.dtb
BUILTIN_DTB := $(patsubst "%",%,$(CONFIG_BUILTIN_DTB_NAME))
obj-$(CONFIG_BUILTIN_DTB) += $(BUILTIN_DTB).dtb.o
@@ -24,6 +25,7 @@ pbl-$(CONFIG_MACH_REALQ7) += imx6q-dmo-realq7.dtb.o
pbl-$(CONFIG_MACH_SOLIDRUN_CUBOX) += dove-cubox.dtb.o
pbl-$(CONFIG_MACH_GK802) += imx6q-gk802.dtb.o
pbl-$(CONFIG_MACH_TQMA6X) += imx6dl-mba6x.dtb.o imx6q-mba6x.dtb.o
+pbl-$(CONFIG_MACH_SOCFPGA_TERASIC_SOCKIT) += socfpga_cyclone5_sockit.dtb.o
.SECONDARY: $(obj)/$(BUILTIN_DTB).dtb.S
.SECONDARY: $(patsubst %,$(obj)/%.S,$(dtb-y))
diff --git a/arch/arm/dts/socfpga_cyclone5_sockit.dts b/arch/arm/dts/socfpga_cyclone5_sockit.dts
new file mode 100644
index 0000000..e8e00ae
--- /dev/null
+++ b/arch/arm/dts/socfpga_cyclone5_sockit.dts
@@ -0,0 +1,121 @@
+/*
+ * Copyright (C) 2013 Steffen Trumtrar <s.trumtrar@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/include/ "socfpga_cyclone5.dtsi"
+
+/ {
+ model = "Terasic SoCkit";
+ compatible = "terasic,sockit", "altr,socfpga";
+
+ chosen {
+ };
+
+ memory {
+ name = "memory";
+ device_type = "memory";
+ reg = <0x0 0x0>;
+ };
+
+ leds: gpio-leds {
+ };
+
+ buttons: gpio-keys {
+ };
+};
+
+&leds {
+ compatible = "gpio-leds";
+
+ led@0 {
+ label = "0";
+ gpios = <&gpio1 24 0>;
+ linux,default-trigger = "heartbeat";
+ };
+
+ led@1 {
+ label = "1";
+ gpios = <&gpio1 25 0>;
+ };
+
+ led@2 {
+ label = "2";
+ gpios = <&gpio1 26 0>;
+ };
+
+ led@3 {
+ label = "3";
+ gpios = <&gpio1 27 0>;
+ };
+};
+
+&buttons {
+ compatible = "gpio-keys";
+
+ key@0 {
+ label = "F1";
+ gpios = <&gpio2 21 0>;
+ linux,code = <59>;
+ };
+
+ key@1 {
+ label = "F2";
+ gpios = <&gpio2 22 0>;
+ linux,code = <60>;
+ };
+
+ key@2 {
+ label = "F3";
+ gpios = <&gpio2 23 0>;
+ linux,code = <61>;
+ };
+
+ key@3 {
+ label = "F4";
+ gpios = <&gpio2 24 0>;
+ linux,code = <62>;
+ };
+};
+
+&gmac1 {
+ phy-mode = "rgmii";
+ status = "okay";
+};
+
+&mmc {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "disabled";
+
+ eeprom@51 {
+ compatible = "atmel,24c32";
+ reg = <0x51>;
+ pagesize = <0x20>;
+ };
+};
+
+&i2c1 {
+ status = "disabled";
+
+ adxl345@53 {
+ compatible = "adi,adxl34x";
+ reg = <0x53>;
+ interrupt-parent = <0x2>;
+ interrupts = <0x0 0xa6 0x4>;
+ };
+};
diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index eb99ef7..70d0a4d 100644
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -13,4 +13,8 @@ config ARCH_TEXT_BASE
hex
default 0x00100000 if MACH_SOCFPGA_CYCLONE5
+config MACH_SOCFPGA_TERASIC_SOCKIT
+ select HAVE_DEFAULT_ENVIRONMENT_NEW
+ bool "Terasic SoCKit"
+
endif
diff --git a/images/Makefile.socfpga b/images/Makefile.socfpga
index ef1cc64..66aec9d 100644
--- a/images/Makefile.socfpga
+++ b/images/Makefile.socfpga
@@ -11,6 +11,13 @@ $(obj)/%.socfpgaimg: $(obj)/% FORCE
$(call if_changed,socfpga_image)
# ----------------------- Cyclone5 based boards ---------------------------
+pblx-$(CONFIG_MACH_SOCFPGA_TERASIC_SOCKIT) += start_socfpga_sockit_xload
+FILE_barebox-socfpga-sockit-xload.img = start_socfpga_sockit_xload.pblx.socfpgaimg
+xload-$(CONFIG_MACH_SOCFPGA_TERASIC_SOCKIT) += barebox-socfpga-sockit-xload.img
+
+pblx-$(CONFIG_MACH_SOCFPGA_TERASIC_SOCKIT) += start_socfpga_sockit
+FILE_barebox-socfpga-sockit.img = start_socfpga_sockit.pblx
+barebox-$(CONFIG_MACH_SOCFPGA_TERASIC_SOCKIT) += barebox-socfpga-sockit.img
ifdef CONFIG_ARCH_SOCFPGA_XLOAD
image-y += $(xload-y)
--
1.8.4.rc3
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barebox@lists.infradead.org
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^ permalink raw reply related
* [PATCH 06/11] scripts: Add Altera SoCFPGA mkimage support
From: Sascha Hauer @ 2013-09-16 8:48 UTC (permalink / raw)
To: barebox
In-Reply-To: <1379321300-8085-1-git-send-email-s.hauer@pengutronix.de>
The Altera SoCFPGAs expect a simple header for their first stage
loaders. This adds a tool to generate images for the SoCFPGAs. The
header is either embedded into the image or optionally prepended
to the image. In this case code is added to jump over the image
header.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
scripts/.gitignore | 1 +
scripts/Makefile | 1 +
scripts/socfpga_mkimage.c | 287 ++++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 289 insertions(+)
create mode 100644 scripts/socfpga_mkimage.c
diff --git a/scripts/.gitignore b/scripts/.gitignore
index 6518c0f..516ea07 100644
--- a/scripts/.gitignore
+++ b/scripts/.gitignore
@@ -10,3 +10,4 @@ mkublheader
omap_signGP
omap4_usbboot
zynq_mkimage
+socfpga_mkimage
diff --git a/scripts/Makefile b/scripts/Makefile
index 307dc3d..97a5dab 100644
--- a/scripts/Makefile
+++ b/scripts/Makefile
@@ -14,6 +14,7 @@ hostprogs-$(CONFIG_ARCH_OMAP) += omap_signGP mk-am35xx-spi-image
hostprogs-$(CONFIG_ARCH_S5PCxx) += s5p_cksum
hostprogs-$(CONFIG_ARCH_DAVINCI) += mkublheader
hostprogs-$(CONFIG_ARCH_ZYNQ) += zynq_mkimage
+hostprogs-$(CONFIG_ARCH_SOCFPGA) += socfpga_mkimage
subdir-$(CONFIG_ARCH_IMX) += imx
HOSTLOADLIBES_omap4_usbboot = -lpthread
diff --git a/scripts/socfpga_mkimage.c b/scripts/socfpga_mkimage.c
new file mode 100644
index 0000000..bab1b1a
--- /dev/null
+++ b/scripts/socfpga_mkimage.c
@@ -0,0 +1,287 @@
+#include <stdio.h>
+#include <unistd.h>
+#include <getopt.h>
+#include <stdlib.h>
+#include <stdint.h>
+#include <string.h>
+#include <errno.h>
+#include <sys/types.h>
+#include <sys/stat.h>
+#include <fcntl.h>
+#include <endian.h>
+
+#define VALIDATION_WORD 0x31305341
+
+#define MAX_IMAGE_SIZE (60 * 1024 - 4)
+
+static int add_barebox_header;
+
+struct socfpga_header {
+ uint8_t validation_word[4];
+ uint8_t version;
+ uint8_t flags;
+ uint8_t program_length[2];
+ uint8_t spare[2];
+ uint8_t checksum[2];
+};
+
+static uint32_t bb_header[] = {
+ 0xea00007e, /* b 0x200 */
+ 0xeafffffe, /* 1: b 1b */
+ 0xeafffffe, /* 1: b 1b */
+ 0xeafffffe, /* 1: b 1b */
+ 0xeafffffe, /* 1: b 1b */
+ 0xeafffffe, /* 1: b 1b */
+ 0xeafffffe, /* 1: b 1b */
+ 0xeafffffe, /* 1: b 1b */
+ 0x65726162, /* 'bare' */
+ 0x00786f62, /* 'box\0' */
+ 0x00000000, /* padding */
+ 0x00000000, /* padding */
+ 0x00000000, /* padding */
+ 0x00000000, /* padding */
+ 0x00000000, /* padding */
+ 0x00000000, /* padding */
+ 0x00000000, /* socfpga header */
+ 0x00000000, /* socfpga header */
+ 0x00000000, /* socfpga header */
+ 0xea00006b, /* entry. b 0x200 */
+};
+
+static int read_full(int fd, void *buf, size_t size)
+{
+ size_t insize = size;
+ int now;
+ int total = 0;
+
+ while (size) {
+ now = read(fd, buf, size);
+ if (now == 0)
+ return total;
+ if (now < 0)
+ return now;
+ total += now;
+ size -= now;
+ buf += now;
+ }
+
+ return insize;
+}
+
+static int write_full(int fd, void *buf, size_t size)
+{
+ size_t insize = size;
+ int now;
+
+ while (size) {
+ now = write(fd, buf, size);
+ if (now <= 0)
+ return now;
+ size -= now;
+ buf += now;
+ }
+
+ return insize;
+}
+
+static uint32_t crc_table[256] = {
+ 0x00000000, 0x04c11db7, 0x09823b6e, 0x0d4326d9, 0x130476dc, 0x17c56b6b,
+ 0x1a864db2, 0x1e475005, 0x2608edb8, 0x22c9f00f, 0x2f8ad6d6, 0x2b4bcb61,
+ 0x350c9b64, 0x31cd86d3, 0x3c8ea00a, 0x384fbdbd, 0x4c11db70, 0x48d0c6c7,
+ 0x4593e01e, 0x4152fda9, 0x5f15adac, 0x5bd4b01b, 0x569796c2, 0x52568b75,
+ 0x6a1936c8, 0x6ed82b7f, 0x639b0da6, 0x675a1011, 0x791d4014, 0x7ddc5da3,
+ 0x709f7b7a, 0x745e66cd, 0x9823b6e0, 0x9ce2ab57, 0x91a18d8e, 0x95609039,
+ 0x8b27c03c, 0x8fe6dd8b, 0x82a5fb52, 0x8664e6e5, 0xbe2b5b58, 0xbaea46ef,
+ 0xb7a96036, 0xb3687d81, 0xad2f2d84, 0xa9ee3033, 0xa4ad16ea, 0xa06c0b5d,
+ 0xd4326d90, 0xd0f37027, 0xddb056fe, 0xd9714b49, 0xc7361b4c, 0xc3f706fb,
+ 0xceb42022, 0xca753d95, 0xf23a8028, 0xf6fb9d9f, 0xfbb8bb46, 0xff79a6f1,
+ 0xe13ef6f4, 0xe5ffeb43, 0xe8bccd9a, 0xec7dd02d, 0x34867077, 0x30476dc0,
+ 0x3d044b19, 0x39c556ae, 0x278206ab, 0x23431b1c, 0x2e003dc5, 0x2ac12072,
+ 0x128e9dcf, 0x164f8078, 0x1b0ca6a1, 0x1fcdbb16, 0x018aeb13, 0x054bf6a4,
+ 0x0808d07d, 0x0cc9cdca, 0x7897ab07, 0x7c56b6b0, 0x71159069, 0x75d48dde,
+ 0x6b93dddb, 0x6f52c06c, 0x6211e6b5, 0x66d0fb02, 0x5e9f46bf, 0x5a5e5b08,
+ 0x571d7dd1, 0x53dc6066, 0x4d9b3063, 0x495a2dd4, 0x44190b0d, 0x40d816ba,
+ 0xaca5c697, 0xa864db20, 0xa527fdf9, 0xa1e6e04e, 0xbfa1b04b, 0xbb60adfc,
+ 0xb6238b25, 0xb2e29692, 0x8aad2b2f, 0x8e6c3698, 0x832f1041, 0x87ee0df6,
+ 0x99a95df3, 0x9d684044, 0x902b669d, 0x94ea7b2a, 0xe0b41de7, 0xe4750050,
+ 0xe9362689, 0xedf73b3e, 0xf3b06b3b, 0xf771768c, 0xfa325055, 0xfef34de2,
+ 0xc6bcf05f, 0xc27dede8, 0xcf3ecb31, 0xcbffd686, 0xd5b88683, 0xd1799b34,
+ 0xdc3abded, 0xd8fba05a, 0x690ce0ee, 0x6dcdfd59, 0x608edb80, 0x644fc637,
+ 0x7a089632, 0x7ec98b85, 0x738aad5c, 0x774bb0eb, 0x4f040d56, 0x4bc510e1,
+ 0x46863638, 0x42472b8f, 0x5c007b8a, 0x58c1663d, 0x558240e4, 0x51435d53,
+ 0x251d3b9e, 0x21dc2629, 0x2c9f00f0, 0x285e1d47, 0x36194d42, 0x32d850f5,
+ 0x3f9b762c, 0x3b5a6b9b, 0x0315d626, 0x07d4cb91, 0x0a97ed48, 0x0e56f0ff,
+ 0x1011a0fa, 0x14d0bd4d, 0x19939b94, 0x1d528623, 0xf12f560e, 0xf5ee4bb9,
+ 0xf8ad6d60, 0xfc6c70d7, 0xe22b20d2, 0xe6ea3d65, 0xeba91bbc, 0xef68060b,
+ 0xd727bbb6, 0xd3e6a601, 0xdea580d8, 0xda649d6f, 0xc423cd6a, 0xc0e2d0dd,
+ 0xcda1f604, 0xc960ebb3, 0xbd3e8d7e, 0xb9ff90c9, 0xb4bcb610, 0xb07daba7,
+ 0xae3afba2, 0xaafbe615, 0xa7b8c0cc, 0xa379dd7b, 0x9b3660c6, 0x9ff77d71,
+ 0x92b45ba8, 0x9675461f, 0x8832161a, 0x8cf30bad, 0x81b02d74, 0x857130c3,
+ 0x5d8a9099, 0x594b8d2e, 0x5408abf7, 0x50c9b640, 0x4e8ee645, 0x4a4ffbf2,
+ 0x470cdd2b, 0x43cdc09c, 0x7b827d21, 0x7f436096, 0x7200464f, 0x76c15bf8,
+ 0x68860bfd, 0x6c47164a, 0x61043093, 0x65c52d24, 0x119b4be9, 0x155a565e,
+ 0x18197087, 0x1cd86d30, 0x029f3d35, 0x065e2082, 0x0b1d065b, 0x0fdc1bec,
+ 0x3793a651, 0x3352bbe6, 0x3e119d3f, 0x3ad08088, 0x2497d08d, 0x2056cd3a,
+ 0x2d15ebe3, 0x29d4f654, 0xc5a92679, 0xc1683bce, 0xcc2b1d17, 0xc8ea00a0,
+ 0xd6ad50a5, 0xd26c4d12, 0xdf2f6bcb, 0xdbee767c, 0xe3a1cbc1, 0xe760d676,
+ 0xea23f0af, 0xeee2ed18, 0xf0a5bd1d, 0xf464a0aa, 0xf9278673, 0xfde69bc4,
+ 0x89b8fd09, 0x8d79e0be, 0x803ac667, 0x84fbdbd0, 0x9abc8bd5, 0x9e7d9662,
+ 0x933eb0bb, 0x97ffad0c, 0xafb010b1, 0xab710d06, 0xa6322bdf, 0xa2f33668,
+ 0xbcb4666d, 0xb8757bda, 0xb5365d03, 0xb1f740b4
+};
+
+uint32_t crc32(uint32_t crc, void *_buf, int length)
+{
+ uint8_t *buf = _buf;
+
+ while (length--)
+ crc = crc << 8 ^ crc_table[(crc >> 24 ^ *(buf++)) & 0xff];
+
+ return crc;
+}
+
+static int add_socfpga_header(void *buf, int size)
+{
+ struct socfpga_header *header = buf + 0x40;
+ uint8_t *buf_header = buf + 0x40;
+ uint32_t *crc;
+ unsigned checksum;
+ int length = size >> 2;
+ int i;
+
+ if (size & 0x3) {
+ fprintf(stderr, "%s: size must be multiple of 4\n", __func__);
+ return -EINVAL;
+ }
+
+ header->validation_word[0] = VALIDATION_WORD & 0xff;
+ header->validation_word[1] = (VALIDATION_WORD >> 8) & 0xff;
+ header->validation_word[2] = (VALIDATION_WORD >> 16) & 0xff;
+ header->validation_word[3] = (VALIDATION_WORD >> 24) & 0xff;
+ header->version = 0;
+ header->flags = 0;
+ header->program_length[0] = length & 0xff;
+ header->program_length[1] = (length >> 8) & 0xff;
+ header->spare[0] = 0;
+ header->spare[1] = 0;
+
+ checksum = 0;
+ for (i = 0; i < sizeof(*header) - 2; i++)
+ checksum += buf_header[i];
+
+ header->checksum[0] = checksum & 0xff;;
+ header->checksum[1] = (checksum >> 8) & 0xff;;
+
+ crc = buf + size - sizeof(uint32_t);
+
+ *crc = crc32(0xffffffff, buf, size - sizeof(uint32_t));
+ *crc ^= 0xffffffff;
+
+ return 0;
+}
+
+static void usage(const char *prgname)
+{
+ fprintf(stderr, "usage: %s [OPTIONS] <infile>\n", prgname);
+}
+
+int main(int argc, char *argv[])
+{
+ int opt, ret;
+ const char *outfile = NULL, *infile;
+ struct stat s;
+ void *buf;
+ int fd;
+ int min_image_size = 80;
+ int max_image_size = MAX_IMAGE_SIZE;
+ int addsize = 0, pad;
+
+ while ((opt = getopt(argc, argv, "o:hb")) != -1) {
+ switch (opt) {
+ case 'b':
+ add_barebox_header = 1;
+ min_image_size = 0;
+ max_image_size = MAX_IMAGE_SIZE - 512;
+ addsize = 512;
+ break;
+ case 'h':
+ usage(argv[0]);
+ exit(0);
+ case 'o':
+ outfile = optarg;
+ break;
+ default:
+ exit(1);
+ }
+ }
+
+ if (optind == argc) {
+ usage(argv[0]);
+ exit(1);
+ }
+
+ infile = argv[optind];
+
+ ret = stat(infile, &s);
+ if (ret) {
+ perror("stat");
+ exit(1);
+ }
+
+ if (s.st_size < min_image_size) {
+ fprintf(stderr, "input image too small. Minimum is 80 bytes\n");
+ exit(1);
+ }
+
+ if (s.st_size > max_image_size) {
+ fprintf(stderr, "input image too big. Maximum is %d bytes\n",
+ MAX_IMAGE_SIZE);
+ exit(1);
+ }
+
+ fd = open(infile, O_RDONLY);
+ if (fd < 0) {
+ perror("open infile");
+ exit(1);
+ }
+
+ pad = s.st_size & 0x3;
+ if (pad)
+ pad = 4 - pad;
+
+ buf = calloc(s.st_size + 4 + addsize + pad, 1);
+ if (!buf) {
+ perror("malloc");
+ exit(1);
+ }
+
+ ret = read_full(fd, buf + addsize, s.st_size);
+ if (ret < 0) {
+ perror("read infile");
+ exit(1);
+ }
+
+ close(fd);
+
+ if (add_barebox_header) {
+ memcpy(buf, bb_header, sizeof(bb_header));
+ }
+
+ ret = add_socfpga_header(buf, s.st_size + 4 + addsize + pad);
+ if (ret)
+ exit(1);
+
+ fd = open(outfile, O_WRONLY | O_CREAT | O_TRUNC, 0644);
+ if (fd < 0) {
+ perror("open outfile");
+ exit(1);
+ }
+
+ ret = write_full(fd, buf, s.st_size + 4 + addsize + pad);
+ if (ret < 0) {
+ perror("write outfile");
+ exit(1);
+ }
+
+ exit(0);
+}
--
1.8.4.rc3
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^ permalink raw reply related
* [PATCH 08/11] ARM: socfpga: Add FPGA programming command
From: Sascha Hauer @ 2013-09-16 8:48 UTC (permalink / raw)
To: barebox
In-Reply-To: <1379321300-8085-1-git-send-email-s.hauer@pengutronix.de>
This adds a simple socfpga specific 'fpga' command to load a firmware
to the FPGA. For the moment this is enough, but should we get more
FPGA support it might be a good idea to introduce some generic framework
and command.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/mach-socfpga/Kconfig | 5 +
arch/arm/mach-socfpga/Makefile | 1 +
arch/arm/mach-socfpga/fpga.c | 422 ++++++++++++++++++++++
arch/arm/mach-socfpga/include/mach/socfpga-regs.h | 2 +
4 files changed, 430 insertions(+)
create mode 100644 arch/arm/mach-socfpga/fpga.c
diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index e6c4c34..eb99ef7 100644
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -4,6 +4,11 @@ config ARCH_SOCFPGA_XLOAD
bool
prompt "Build preloader image"
+config ARCH_SOCFPGA_FPGA
+ depends on COMMAND_SUPPORT
+ bool
+ prompt "Enable FPGA load command"
+
config ARCH_TEXT_BASE
hex
default 0x00100000 if MACH_SOCFPGA_CYCLONE5
diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index d8bf067..12585c5 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -2,3 +2,4 @@ obj-y += generic.o nic301.o bootsource.o reset-manager.o
pbl-y += init.o freeze-controller.o scan-manager.o system-manager.o
pbl-y += clock-manager.o iocsr-config-cyclone5.o
obj-$(CONFIG_ARCH_SOCFPGA_XLOAD) += xload.o
+obj-$(CONFIG_ARCH_SOCFPGA_FPGA) += fpga.o
diff --git a/arch/arm/mach-socfpga/fpga.c b/arch/arm/mach-socfpga/fpga.c
new file mode 100644
index 0000000..6828001
--- /dev/null
+++ b/arch/arm/mach-socfpga/fpga.c
@@ -0,0 +1,422 @@
+/*
+ *
+ * Copyright (C) 2012 Altera Corporation <www.altera.com>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * - Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * - Neither the name of the Altera Corporation nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL ALTERA CORPORATION BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#define pr_fmt(fmt) "fpgamgr: " fmt
+
+#include <command.h>
+#include <common.h>
+#include <malloc.h>
+#include <clock.h>
+#include <fcntl.h>
+#include <fs.h>
+#include <io.h>
+#include <mach/socfpga-regs.h>
+#include <mach/reset-manager.h>
+#include <mach/system-manager.h>
+#include <mach/sdram.h>
+
+#define FPGAMGRREGS_STAT 0x0
+#define FPGAMGRREGS_CTRL 0x4
+#define FPGAMGRREGS_DCLKCNT 0x8
+#define FPGAMGRREGS_DCLKSTAT 0xc
+
+#define FPGAMGRREGS_MON_GPIO_PORTA_EOI_ADDRESS 0x84c
+#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_ADDRESS 0x850
+
+#define FPGAMGRREGS_CTRL_CFGWDTH_MASK 0x200
+#define FPGAMGRREGS_CTRL_AXICFGEN_MASK 0x100
+#define FPGAMGRREGS_CTRL_NCONFIGPULL_MASK 0x4
+#define FPGAMGRREGS_CTRL_NCE_MASK 0x2
+#define FPGAMGRREGS_CTRL_EN_MASK 0x1
+#define FPGAMGRREGS_CTRL_CDRATIO_LSB 6
+
+#define FPGAMGRREGS_STAT_MODE_MASK 0x7
+#define FPGAMGRREGS_STAT_MSEL_MASK 0xf8
+#define FPGAMGRREGS_STAT_MSEL_LSB 3
+
+#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_CRC_MASK 0x8
+#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_ID_MASK 0x4
+#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_CD_MASK 0x2
+#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_NS_MASK 0x1
+
+/* FPGA Mode */
+#define FPGAMGRREGS_MODE_FPGAOFF 0x0
+#define FPGAMGRREGS_MODE_RESETPHASE 0x1
+#define FPGAMGRREGS_MODE_CFGPHASE 0x2
+#define FPGAMGRREGS_MODE_INITPHASE 0x3
+#define FPGAMGRREGS_MODE_USERMODE 0x4
+#define FPGAMGRREGS_MODE_UNKNOWN 0x5
+
+/* FPGA CD Ratio Value */
+#define CDRATIO_x1 0x0
+#define CDRATIO_x2 0x1
+#define CDRATIO_x4 0x2
+#define CDRATIO_x8 0x3
+
+static void __iomem *fpgamgr_base = (void *)CYCLONE5_FPGAMGRREGS_ADDRESS;
+
+/* Get the FPGA mode */
+static uint32_t fpgamgr_get_mode(void)
+{
+ return readl(fpgamgr_base + FPGAMGRREGS_STAT) & FPGAMGRREGS_STAT_MODE_MASK;
+}
+
+static int fpgamgr_dclkcnt_set(unsigned long cnt)
+{
+ uint64_t start;
+
+ /* clear any existing done status */
+ if (readl(fpgamgr_base + FPGAMGRREGS_DCLKSTAT))
+ writel(0x1, fpgamgr_base + FPGAMGRREGS_DCLKSTAT);
+
+ writel(cnt, fpgamgr_base + FPGAMGRREGS_DCLKCNT);
+
+ /* wait till the dclkcnt done */
+ start = get_time_ns();
+ while (1) {
+ if (readl(fpgamgr_base + FPGAMGRREGS_DCLKSTAT)) {
+ writel(0x1, fpgamgr_base + FPGAMGRREGS_DCLKSTAT);
+ return 0;
+ }
+
+ if (is_timeout(start, 100 * MSECOND))
+ return -ETIMEDOUT;
+ }
+}
+
+/* Start the FPGA programming by initialize the FPGA Manager */
+static int fpgamgr_program_init(void)
+{
+ unsigned long reg;
+ uint32_t ctrl = 0, ratio;
+ uint64_t start;
+
+ /* get the MSEL value */
+ reg = readl(fpgamgr_base + FPGAMGRREGS_STAT);
+ reg = ((reg & FPGAMGRREGS_STAT_MSEL_MASK) >> FPGAMGRREGS_STAT_MSEL_LSB);
+
+ if (reg & 0x8)
+ ctrl |= FPGAMGRREGS_CTRL_CFGWDTH_MASK;
+ else
+ ctrl &= ~FPGAMGRREGS_CTRL_CFGWDTH_MASK;
+
+ switch (reg & 0xb) {
+ case 0xa:
+ ratio = CDRATIO_x8;
+ break;
+ case 0x2:
+ case 0x9:
+ ratio = CDRATIO_x4;
+ break;
+ case 0x1:
+ ratio = CDRATIO_x2;
+ break;
+ case 0x8:
+ case 0xb:
+ default:
+ ratio = CDRATIO_x1;
+ break;
+ }
+
+ ctrl |= ratio << FPGAMGRREGS_CTRL_CDRATIO_LSB;
+
+ /* to enable FPGA Manager drive over configuration line */
+ ctrl |= FPGAMGRREGS_CTRL_EN_MASK;
+
+ /* put FPGA into reset phase */
+ ctrl |= FPGAMGRREGS_CTRL_NCONFIGPULL_MASK;
+
+ writel(ctrl, fpgamgr_base + FPGAMGRREGS_CTRL);
+
+ /* (1) wait until FPGA enter reset phase */
+ start = get_time_ns();
+ while (1) {
+ if (fpgamgr_get_mode() == FPGAMGRREGS_MODE_RESETPHASE)
+ break;
+ if (is_timeout(start, 100 * MSECOND))
+ return -ETIMEDOUT;
+ }
+
+ /* release FPGA from reset phase */
+ ctrl = readl(fpgamgr_base + FPGAMGRREGS_CTRL);
+ ctrl &= ~FPGAMGRREGS_CTRL_NCONFIGPULL_MASK;
+ writel(ctrl, fpgamgr_base + FPGAMGRREGS_CTRL);
+
+ /* (2) wait until FPGA enter configuration phase */
+ start = get_time_ns();
+ while (1) {
+ if (fpgamgr_get_mode() == FPGAMGRREGS_MODE_CFGPHASE)
+ break;
+ if (is_timeout(start, 100 * MSECOND))
+ return -ETIMEDOUT;
+ }
+
+ /* clear all interrupt in CB Monitor */
+ writel(0xFFF, (fpgamgr_base + FPGAMGRREGS_MON_GPIO_PORTA_EOI_ADDRESS));
+
+ /* enable AXI configuration */
+ ctrl = readl(fpgamgr_base + FPGAMGRREGS_CTRL);
+ ctrl |= FPGAMGRREGS_CTRL_AXICFGEN_MASK;
+ writel(ctrl, fpgamgr_base + FPGAMGRREGS_CTRL);
+
+ return 0;
+}
+
+/* Write the RBF data to FPGA Manager */
+static void fpgamgr_program_write_buf(const void *buf, int size)
+{
+ const uint32_t *buf32 = buf;
+
+ /* write to FPGA Manager AXI data */
+ while (size) {
+ writel(*buf32, CYCLONE5_FPGAMGRDATA_ADDRESS);
+ readl(fpgamgr_base + FPGAMGRREGS_MON_GPIO_EXT_PORTA_ADDRESS);
+ buf32++;
+ size -= sizeof(uint32_t);
+ }
+}
+
+/* Ensure the FPGA entering config done */
+static int fpgamgr_program_poll_cd(void)
+{
+ unsigned long reg;
+ uint32_t val;
+ uint64_t start;
+
+ /* (3) wait until full config done */
+ start = get_time_ns();
+ while (1) {
+ reg = readl(fpgamgr_base + FPGAMGRREGS_MON_GPIO_EXT_PORTA_ADDRESS);
+
+ /* config error */
+ if (!(reg & FPGAMGRREGS_MON_GPIO_EXT_PORTA_NS_MASK) &&
+ !(reg & FPGAMGRREGS_MON_GPIO_EXT_PORTA_CD_MASK))
+ return -EIO;
+
+ /* config done without error */
+ if ((reg & FPGAMGRREGS_MON_GPIO_EXT_PORTA_NS_MASK) &&
+ (reg & FPGAMGRREGS_MON_GPIO_EXT_PORTA_CD_MASK))
+ break;
+
+ if (is_timeout(start, 100 * MSECOND))
+ return -ETIMEDOUT;
+ }
+
+ /* disable AXI configuration */
+ val = readl(fpgamgr_base + FPGAMGRREGS_CTRL);
+ val &= ~FPGAMGRREGS_CTRL_AXICFGEN_MASK;
+ writel(val, fpgamgr_base + FPGAMGRREGS_CTRL);
+
+ return 0;
+}
+
+/* Ensure the FPGA entering init phase */
+static int fpgamgr_program_poll_initphase(void)
+{
+ uint64_t start;
+
+ /* additional clocks for the CB to enter initialization phase */
+ if (fpgamgr_dclkcnt_set(0x4) != 0)
+ return -5;
+
+ /* (4) wait until FPGA enter init phase or user mode */
+ start = get_time_ns();
+ while (1) {
+ int mode = fpgamgr_get_mode();
+
+ if (mode == FPGAMGRREGS_MODE_INITPHASE ||
+ mode == FPGAMGRREGS_MODE_USERMODE)
+ break;
+
+ if (is_timeout(start, 100 * MSECOND))
+ return -ETIMEDOUT;
+ }
+
+ return 0;
+}
+
+/* Ensure the FPGA entering user mode */
+static int fpgamgr_program_poll_usermode(void)
+{
+ uint32_t val;
+ uint64_t start;
+
+ /* additional clocks for the CB to exit initialization phase */
+ if (fpgamgr_dclkcnt_set(0x5000) != 0)
+ return -7;
+
+ /* (5) wait until FPGA enter user mode */
+ start = get_time_ns();
+ while (1) {
+ if (fpgamgr_get_mode() == FPGAMGRREGS_MODE_USERMODE)
+ break;
+ if (is_timeout(start, 100 * MSECOND))
+ return -ETIMEDOUT;
+ }
+
+ /* to release FPGA Manager drive over configuration line */
+ val = readl(fpgamgr_base + FPGAMGRREGS_CTRL);
+ val &= ~FPGAMGRREGS_CTRL_EN_MASK;
+ writel(val, fpgamgr_base + FPGAMGRREGS_CTRL);
+
+ return 0;
+}
+
+/*
+ * Using FPGA Manager to program the FPGA
+ * Return 0 for sucess
+ */
+static int fpgamgr_program_start(void)
+{
+ int status;
+
+ /* prior programming the FPGA, all bridges need to be shut off */
+
+ /* disable all signals from hps peripheral controller to fpga */
+ writel(0, SYSMGR_FPGAINTF_MODULE);
+
+ /* disable all signals from fpga to hps sdram */
+ writel(0, (CYCLONE5_SDR_ADDRESS + SDR_CTRLGRP_FPGAPORTRST_ADDRESS));
+
+ /* disable all axi bridge (hps2fpga, lwhps2fpga & fpga2hps) */
+ writel(~0, CYCLONE5_RSTMGR_ADDRESS + RESET_MGR_BRG_MOD_RESET_OFS);
+
+ /* unmap the bridges from NIC-301 */
+ writel(0x1, CYCLONE5_L3REGS_ADDRESS);
+
+ pr_debug("start programming...\n");
+
+ /* initialize the FPGA Manager */
+ status = fpgamgr_program_init();
+ if (status) {
+ pr_err("program init failed with: %s\n",
+ strerror(-status));
+ return status;
+ }
+
+ return 0;
+}
+
+static int fpgamgr_program_finish(void)
+{
+ int status;
+
+ /* Ensure the FPGA entering config done */
+ status = fpgamgr_program_poll_cd();
+ if (status) {
+ pr_err("poll for config done failed with: %s\n",
+ strerror(-status));
+ return status;
+ }
+
+ pr_debug("waiting for init phase...\n");
+
+ /* Ensure the FPGA entering init phase */
+ status = fpgamgr_program_poll_initphase();
+ if (status) {
+ pr_err("poll for init phase failed with: %s\n",
+ strerror(-status));
+ return status;
+ }
+
+ pr_debug("waiting for user mode...\n");
+
+ /* Ensure the FPGA entering user mode */
+ status = fpgamgr_program_poll_usermode();
+ if (status) {
+ pr_err("poll for user mode with: %s\n", strerror(-status));
+ return status;
+ }
+
+ return 0;
+}
+
+static int fpgamgr_program_file(const char *filename)
+{
+ int ret, fd;
+ void *buf;
+ int bufsiz = 4096;
+
+ fd = open(filename, O_RDONLY);
+ if (fd < 0)
+ return fd;
+
+ buf = xzalloc(bufsiz);
+
+ ret = fpgamgr_program_start();
+ if (ret)
+ goto err;
+
+ while (1) {
+ int now = read(fd, buf, bufsiz);
+ if (now < 0) {
+ ret = now;
+ goto err;
+ }
+
+ if (!now)
+ break;
+
+ fpgamgr_program_write_buf(buf, now);
+ }
+
+ ret = fpgamgr_program_finish();
+ if (ret)
+ goto err;
+
+ ret = 0;
+err:
+ close(fd);
+ free(buf);
+
+ return ret;
+}
+
+static int do_fpga(int argc, char *argv[])
+{
+ int ret;
+
+ if (argc != 2)
+ return COMMAND_ERROR_USAGE;
+
+ ret = fpgamgr_program_file(argv[1]);
+ if (!ret)
+ printf("FPGA successfully programmed\n");
+
+ return ret;
+}
+
+BAREBOX_CMD_HELP_START(fpga)
+BAREBOX_CMD_HELP_USAGE("fpga <firmware>\n")
+BAREBOX_CMD_HELP_USAGE("firmware is a file in RBF format\n")
+BAREBOX_CMD_HELP_END
+
+BAREBOX_CMD_START(fpga)
+ .cmd = do_fpga,
+ .usage = "load FPGA firmware",
+ BAREBOX_CMD_HELP(cmd_fpga_help)
+BAREBOX_CMD_END
diff --git a/arch/arm/mach-socfpga/include/mach/socfpga-regs.h b/arch/arm/mach-socfpga/include/mach/socfpga-regs.h
index 9d1e677..b124ed6 100644
--- a/arch/arm/mach-socfpga/include/mach/socfpga-regs.h
+++ b/arch/arm/mach-socfpga/include/mach/socfpga-regs.h
@@ -2,10 +2,12 @@
#define __MACH_SOCFPGA_REGS_H
#define CYCLONE5_SDMMC_ADDRESS 0xff704000
+#define CYCLONE5_FPGAMGRREGS_ADDRESS 0xff706000
#define CYCLONE5_GPIO0_BASE 0xff708000
#define CYCLONE5_GPIO1_BASE 0xff709000
#define CYCLONE5_GPIO2_BASE 0xff70A000
#define CYCLONE5_L3REGS_ADDRESS 0xff800000
+#define CYCLONE5_FPGAMGRDATA_ADDRESS 0xffb90000
#define CYCLONE5_UART0_ADDRESS 0xffc02000
#define CYCLONE5_UART1_ADDRESS 0xffc03000
#define CYCLONE5_SDR_ADDRESS 0xffc20000
--
1.8.4.rc3
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^ permalink raw reply related
* [PATCH 05/11] clk: Add Altera SoCFPGA clk support
From: Sascha Hauer @ 2013-09-16 8:48 UTC (permalink / raw)
To: barebox
In-Reply-To: <1379321300-8085-1-git-send-email-s.hauer@pengutronix.de>
The SoCFPGA currently has all clocks described in the devicetree which
makes common clock support a straight forward task.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
drivers/clk/Kconfig | 5 +
drivers/clk/Makefile | 1 +
drivers/clk/socfpga.c | 412 ++++++++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 418 insertions(+)
create mode 100644 drivers/clk/socfpga.c
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 2978c2e..1cf0ccb 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -12,3 +12,8 @@ config COMMON_CLK_OF_PROVIDER
bool
help
Clock driver provides OF-Tree based clock lookup.
+
+config CLK_SOCFPGA
+ bool
+ select COMMON_CLK_OF_PROVIDER
+ default y if ARCH_SOCFPGA && OFDEVICE
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index a121947..f5c0592 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -5,3 +5,4 @@ obj-$(CONFIG_CLKDEV_LOOKUP) += clkdev.o
obj-$(CONFIG_ARCH_MVEBU) += mvebu/
obj-$(CONFIG_ARCH_MXS) += mxs/
obj-$(CONFIG_ARCH_TEGRA) += tegra/
+obj-$(CONFIG_CLK_SOCFPGA) += socfpga.o
diff --git a/drivers/clk/socfpga.c b/drivers/clk/socfpga.c
new file mode 100644
index 0000000..33a55cb
--- /dev/null
+++ b/drivers/clk/socfpga.c
@@ -0,0 +1,412 @@
+/*
+ * Copyright (C) 2013 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <common.h>
+#include <init.h>
+#include <driver.h>
+#include <linux/clk.h>
+#include <io.h>
+#include <malloc.h>
+#include <linux/clkdev.h>
+#include <linux/err.h>
+
+/* Clock Manager offsets */
+#define CLKMGR_CTRL 0x0
+#define CLKMGR_BYPASS 0x4
+#define CLKMGR_L4SRC 0x70
+#define CLKMGR_PERPLL_SRC 0xAC
+
+/* Clock bypass bits */
+#define MAINPLL_BYPASS (1<<0)
+#define SDRAMPLL_BYPASS (1<<1)
+#define SDRAMPLL_SRC_BYPASS (1<<2)
+#define PERPLL_BYPASS (1<<3)
+#define PERPLL_SRC_BYPASS (1<<4)
+
+#define SOCFPGA_PLL_BG_PWRDWN 0
+#define SOCFPGA_PLL_EXT_ENA 1
+#define SOCFPGA_PLL_PWR_DOWN 2
+#define SOCFPGA_PLL_DIVF_MASK 0x0000FFF8
+#define SOCFPGA_PLL_DIVF_SHIFT 3
+#define SOCFPGA_PLL_DIVQ_MASK 0x003F0000
+#define SOCFPGA_PLL_DIVQ_SHIFT 16
+#define SOCFGPA_MAX_PARENTS 3
+
+#define SOCFPGA_DB_CLK "gpio_db_clk"
+
+#define div_mask(width) ((1 << (width)) - 1)
+#define streq(a, b) (strcmp((a), (b)) == 0)
+
+static void __iomem *clk_mgr_base_addr;
+
+char *of_clk_get_parent_name(struct device_node *np, unsigned int index)
+{
+ struct of_phandle_args clkspec;
+ const char *clk_name;
+ int rc;
+
+ rc = of_parse_phandle_with_args(np, "clocks", "#clock-cells", index,
+ &clkspec);
+ if (rc)
+ return NULL;
+
+ if (of_property_read_string_index(clkspec.np, "clock-output-names",
+ clkspec.args_count ? clkspec.args[0] : 0,
+ &clk_name) < 0)
+ clk_name = clkspec.np->name;
+
+ return xstrdup(clk_name);
+}
+
+static struct clk *socfpga_fixed_clk(struct device_node *node)
+{
+ uint32_t f = 0;
+
+ of_property_read_u32(node, "clock-frequency", &f);
+
+ return clk_fixed(node->name, f);
+}
+
+struct clk_pll {
+ struct clk clk;
+ const char *parent;
+ unsigned regofs;
+};
+
+static unsigned long clk_pll_recalc_rate(struct clk *clk,
+ unsigned long parent_rate)
+{
+ struct clk_pll *pll = container_of(clk, struct clk_pll, clk);
+ unsigned long divf, divq, vco_freq, reg;
+ unsigned long bypass;
+
+ reg = readl(clk_mgr_base_addr + pll->regofs);
+
+ bypass = readl(clk_mgr_base_addr + CLKMGR_BYPASS);
+ if (bypass & MAINPLL_BYPASS)
+ return parent_rate;
+
+ divf = (reg & SOCFPGA_PLL_DIVF_MASK) >> SOCFPGA_PLL_DIVF_SHIFT;
+ divq = (reg & SOCFPGA_PLL_DIVQ_MASK) >> SOCFPGA_PLL_DIVQ_SHIFT;
+ vco_freq = parent_rate * (divf + 1);
+
+ return vco_freq / (1 + divq);
+}
+
+static struct clk_ops clk_pll_ops = {
+ .recalc_rate = clk_pll_recalc_rate,
+};
+
+static struct clk *socfpga_pll_clk(struct device_node *node)
+{
+ struct clk_pll *pll;
+ int ret;
+
+ pll = xzalloc(sizeof(*pll));
+
+ pll->parent = of_clk_get_parent_name(node, 0);
+ if (!pll->parent)
+ return ERR_PTR(-EINVAL);
+
+ pll->clk.parent_names = &pll->parent;
+ pll->clk.num_parents = 1;
+ pll->clk.name = xstrdup(node->name);
+ pll->clk.ops = &clk_pll_ops;
+
+ of_property_read_u32(node, "reg", &pll->regofs);
+
+ ret = clk_register(&pll->clk);
+ if (ret) {
+ free(pll);
+ return ERR_PTR(ret);
+ }
+
+ return &pll->clk;
+}
+
+struct clk_periph {
+ struct clk clk;
+ const char *parent;
+ unsigned regofs;
+ unsigned int fixed_div;
+};
+
+static unsigned long clk_periph_recalc_rate(struct clk *clk,
+ unsigned long parent_rate)
+{
+ struct clk_periph *periph = container_of(clk, struct clk_periph, clk);
+ u32 div;
+
+ if (periph->fixed_div)
+ div = periph->fixed_div;
+ else
+ div = ((readl(clk_mgr_base_addr + periph->regofs) & 0x1ff) + 1);
+
+ return parent_rate / div;
+}
+
+static struct clk_ops clk_periph_ops = {
+ .recalc_rate = clk_periph_recalc_rate,
+};
+
+static struct clk *socfpga_periph_clk(struct device_node *node)
+{
+ struct clk_periph *periph;
+ int ret;
+
+ periph = xzalloc(sizeof(*periph));
+
+ periph->parent = of_clk_get_parent_name(node, 0);
+ if (!periph->parent)
+ return ERR_PTR(-EINVAL);
+
+ periph->clk.parent_names = &periph->parent;
+ periph->clk.num_parents = 1;
+ periph->clk.name = xstrdup(node->name);
+ periph->clk.ops = &clk_periph_ops;
+
+ of_property_read_u32(node, "reg", &periph->regofs);
+ of_property_read_u32(node, "fixed-divider", &periph->fixed_div);
+
+ ret = clk_register(&periph->clk);
+ if (ret) {
+ free(periph);
+ return ERR_PTR(ret);
+ }
+
+ return &periph->clk;
+}
+
+struct clk_socfpga {
+ struct clk clk;
+ const char *parent;
+ void __iomem *reg;
+ void __iomem *div_reg;
+ void __iomem *parent_reg;
+ unsigned int fixed_div;
+ unsigned int bit_idx;
+ unsigned int shift;
+ unsigned int width;
+ unsigned int parent_shift;
+ unsigned int parent_width;
+ const char *parent_names[SOCFGPA_MAX_PARENTS];
+};
+
+static int clk_socfpga_enable(struct clk *clk)
+{
+ struct clk_socfpga *cs = container_of(clk, struct clk_socfpga, clk);
+ u32 val;
+
+ val = readl(cs->reg);
+ val |= 1 << cs->shift;
+ writel(val, cs->reg);
+
+ return 0;
+}
+
+static void clk_socfpga_disable(struct clk *clk)
+{
+ struct clk_socfpga *cs = container_of(clk, struct clk_socfpga, clk);
+ u32 val;
+
+ val = readl(cs->reg);
+ val &= ~(1 << cs->shift);
+ writel(val, cs->reg);
+}
+
+static int clk_socfpga_is_enabled(struct clk *clk)
+{
+ struct clk_socfpga *cs = container_of(clk, struct clk_socfpga, clk);
+ u32 val;
+
+ val = readl(cs->reg);
+
+ if (val & (1 << cs->shift))
+ return 1;
+ else
+ return 0;
+}
+
+static unsigned long clk_socfpga_recalc_rate(struct clk *clk,
+ unsigned long parent_rate)
+{
+ struct clk_socfpga *cs = container_of(clk, struct clk_socfpga, clk);
+ u32 div = 1, val;
+
+ if (cs->fixed_div) {
+ div = cs->fixed_div;
+ } else if (cs->div_reg) {
+ val = readl(cs->div_reg) >> cs->shift;
+ val &= div_mask(cs->width);
+ if (streq(clk->name, SOCFPGA_DB_CLK))
+ div = val + 1;
+ else
+ div = (1 << val);
+ }
+
+ return parent_rate / div;
+}
+
+static int clk_socfpga_get_parent(struct clk *clk)
+{
+ struct clk_socfpga *cs = container_of(clk, struct clk_socfpga, clk);
+
+ return readl(cs->parent_reg) >> cs->parent_shift &
+ ((1 << cs->parent_width) - 1);
+}
+
+static int clk_socfpga_set_parent(struct clk *clk, u8 parent)
+{
+ struct clk_socfpga *cs = container_of(clk, struct clk_socfpga, clk);
+ uint32_t val;
+
+ val = readl(cs->parent_reg);
+ val &= ~(((1 << cs->parent_width) - 1) << cs->parent_shift);
+ val |= parent << cs->parent_shift;
+ writel(val, cs->parent_reg);
+
+ return 0;
+}
+
+static struct clk_ops clk_socfpga_ops = {
+ .recalc_rate = clk_socfpga_recalc_rate,
+ .enable = clk_socfpga_enable,
+ .disable = clk_socfpga_disable,
+ .is_enabled = clk_socfpga_is_enabled,
+ .get_parent = clk_socfpga_get_parent,
+ .set_parent = clk_socfpga_set_parent,
+};
+
+static struct clk *socfpga_gate_clk(struct device_node *node)
+{
+ u32 clk_gate[2];
+ u32 div_reg[3];
+ u32 parent_reg[3];
+ u32 fixed_div;
+ struct clk_socfpga *cs;
+ int ret;
+ int i = 0;
+
+ cs = xzalloc(sizeof(*cs));
+
+ ret = of_property_read_u32_array(node, "clk-gate", clk_gate, 2);
+ if (ret)
+ clk_gate[0] = 0;
+
+ if (clk_gate[0]) {
+ cs->reg = clk_mgr_base_addr + clk_gate[0];
+ cs->bit_idx = clk_gate[1];
+ }
+
+ ret = of_property_read_u32(node, "fixed-divider", &fixed_div);
+ if (ret)
+ cs->fixed_div = 0;
+ else
+ cs->fixed_div = fixed_div;
+
+ ret = of_property_read_u32_array(node, "div-reg", div_reg, 3);
+ if (!ret) {
+ cs->div_reg = clk_mgr_base_addr + div_reg[0];
+ cs->shift = div_reg[1];
+ cs->width = div_reg[2];
+ }
+
+ ret = of_property_read_u32_array(node, "parent-reg", parent_reg, 3);
+ if (!ret) {
+ cs->parent_reg = clk_mgr_base_addr + parent_reg[0];
+ cs->parent_shift = parent_reg[1];
+ cs->parent_width = parent_reg[2];
+ }
+
+ for (i = 0; i < SOCFGPA_MAX_PARENTS; i++) {
+ cs->parent_names[i] = of_clk_get_parent_name(node, i);
+ if (!cs->parent_names[i])
+ break;
+ }
+
+ cs->clk.parent_names = cs->parent_names;
+ cs->clk.num_parents = i;
+ cs->clk.name = xstrdup(node->name);
+ cs->clk.ops = &clk_socfpga_ops;
+
+ ret = clk_register(&cs->clk);
+ if (ret) {
+ free(cs);
+ return ERR_PTR(ret);
+ }
+
+ return &cs->clk;
+}
+
+static void socfpga_register_clocks(struct device_d *dev, struct device_node *node)
+{
+ struct device_node *child;
+ struct clk *clk;
+
+ for_each_child_of_node(node, child) {
+ socfpga_register_clocks(dev, child);
+ }
+
+ if (of_device_is_compatible(node, "fixed-clock"))
+ clk = socfpga_fixed_clk(node);
+ else if (of_device_is_compatible(node, "altr,socfpga-pll-clock"))
+ clk = socfpga_pll_clk(node);
+ else if (of_device_is_compatible(node, "altr,socfpga-perip-clk"))
+ clk = socfpga_periph_clk(node);
+ else if (of_device_is_compatible(node, "altr,socfpga-gate-clk"))
+ clk = socfpga_gate_clk(node);
+ else
+ return;
+
+ of_clk_add_provider(node, of_clk_src_simple_get, clk);
+}
+
+static int socfpga_ccm_probe(struct device_d *dev)
+{
+ void __iomem *regs;
+ struct device_node *clknode;
+
+ regs = dev_request_mem_region(dev, 0);
+ if (!regs)
+ return -EBUSY;
+
+ clk_mgr_base_addr = regs;
+
+ clknode = of_get_child_by_name(dev->device_node, "clocks");
+ if (!clknode)
+ return -EINVAL;
+
+ socfpga_register_clocks(dev, clknode);
+
+ return 0;
+}
+
+static __maybe_unused struct of_device_id socfpga_ccm_dt_ids[] = {
+ {
+ .compatible = "altr,clk-mgr",
+ }, {
+ /* sentinel */
+ }
+};
+
+static struct driver_d socfpga_ccm_driver = {
+ .probe = socfpga_ccm_probe,
+ .name = "socfpga-ccm",
+ .of_compatible = DRV_OF_COMPAT(socfpga_ccm_dt_ids),
+};
+
+static int socfpga_ccm_init(void)
+{
+ return platform_driver_register(&socfpga_ccm_driver);
+}
+core_initcall(socfpga_ccm_init);
--
1.8.4.rc3
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^ permalink raw reply related
* [PATCH] Altera SoCFPGA support
From: Sascha Hauer @ 2013-09-16 8:48 UTC (permalink / raw)
To: barebox
The following adds Altera SoCFPGA support to barebox. The port has
been tested on two boards, The Terasic SoCkit and and EBV SoCrates.
With the patches previously merged Console, SD/MMC and network is supported
which is enough for booting and developing.
The SoCFPGA supports loading of the initial image into SRAM. The usable
size in the SRAM is less than 64KiB, so the SoCFPGA has a two staged
bootstrap like the OMAP/AM33xx boards. The good thing is that only two
configs are required, one for the 1st stage loader (I called it xload
like the OMAPs do) and one for the regular build. Both configs support
both boards, so there are no board config files but only socfpga_xload_defconfig
and socfpga_defconfig.
The port should be relatively clean apart from the SDRAM setup. The SDRAM
setup is a huge blob which is controlled by defines which directly fall
out of the Altera Quartus/Qsys toolchain. As users are used to the Altera
toolchain I used the files that Quartus generates for barebox aswell, so
supporting a new board should be a straight forward task.
Sascha
----------------------------------------------------------------
Sascha Hauer (11):
ARM: invalidate caches thoroughly
clk: of: introduce of_clk_src_simple_get
of: partition: Check for valid partition name
serial: ns16550: Add compatible entry for snps,dw-apb-uart
clk: Add Altera SoCFPGA clk support
scripts: Add Altera SoCFPGA mkimage support
ARM: Add Altera SoCFPGA support
ARM: socfpga: Add FPGA programming command
ARM: SoCFPGA: Add Terasic SoCkit board support
ARM: SoCFPGA: Add EBV SoCrates board support
ARM: Altera SoCFPGA: Add defconfig files
arch/arm/Kconfig | 12 +
arch/arm/Makefile | 1 +
arch/arm/boards/Makefile | 2 +
arch/arm/boards/ebv-socrates/Makefile | 2 +
arch/arm/boards/ebv-socrates/board.c | 37 +
arch/arm/boards/ebv-socrates/config.h | 1 +
arch/arm/boards/ebv-socrates/lowlevel.c | 99 +
arch/arm/boards/ebv-socrates/pinmux_config.c | 210 +
arch/arm/boards/ebv-socrates/pll_config.h | 97 +
arch/arm/boards/ebv-socrates/sdram_config.h | 73 +
arch/arm/boards/ebv-socrates/sequencer_auto.h | 174 +
.../boards/ebv-socrates/sequencer_auto_ac_init.c | 40 +
.../boards/ebv-socrates/sequencer_auto_inst_init.c | 132 +
arch/arm/boards/ebv-socrates/sequencer_defines.h | 118 +
arch/arm/boards/terasic-sockit/Makefile | 2 +
arch/arm/boards/terasic-sockit/board.c | 37 +
arch/arm/boards/terasic-sockit/config.h | 1 +
arch/arm/boards/terasic-sockit/lowlevel.c | 99 +
arch/arm/boards/terasic-sockit/pinmux_config.c | 211 +
arch/arm/boards/terasic-sockit/pll_config.h | 98 +
arch/arm/boards/terasic-sockit/sdram_config.h | 69 +
arch/arm/boards/terasic-sockit/sequencer_auto.h | 173 +
.../boards/terasic-sockit/sequencer_auto_ac_init.c | 40 +
.../terasic-sockit/sequencer_auto_inst_init.c | 134 +
arch/arm/boards/terasic-sockit/sequencer_defines.h | 118 +
arch/arm/configs/socfpga-xload_defconfig | 30 +
arch/arm/configs/socfpga_defconfig | 89 +
arch/arm/cpu/Makefile | 6 +-
arch/arm/cpu/start.c | 4 +-
arch/arm/cpu/uncompress.c | 2 +
arch/arm/dts/Makefile | 4 +
arch/arm/dts/socfpga.dtsi | 648 +++
arch/arm/dts/socfpga_cyclone5.dtsi | 78 +
arch/arm/dts/socfpga_cyclone5_sockit.dts | 121 +
arch/arm/dts/socfpga_cyclone5_socrates.dts | 64 +
arch/arm/include/asm/cache.h | 10 -
arch/arm/mach-socfpga/Kconfig | 24 +
arch/arm/mach-socfpga/Makefile | 5 +
arch/arm/mach-socfpga/bootsource.c | 57 +
arch/arm/mach-socfpga/clock-manager.c | 285 ++
arch/arm/mach-socfpga/fpga.c | 422 ++
arch/arm/mach-socfpga/freeze-controller.c | 218 +
arch/arm/mach-socfpga/generic.c | 116 +
arch/arm/mach-socfpga/include/mach/clkdev.h | 7 +
arch/arm/mach-socfpga/include/mach/clock-manager.h | 188 +
arch/arm/mach-socfpga/include/mach/debug_ll.h | 55 +
.../mach-socfpga/include/mach/freeze-controller.h | 85 +
arch/arm/mach-socfpga/include/mach/generic.h | 16 +
arch/arm/mach-socfpga/include/mach/nic301.h | 34 +
arch/arm/mach-socfpga/include/mach/pll_config.h | 53 +
arch/arm/mach-socfpga/include/mach/reset-manager.h | 93 +
arch/arm/mach-socfpga/include/mach/scan-manager.h | 131 +
arch/arm/mach-socfpga/include/mach/sdram.h | 399 ++
arch/arm/mach-socfpga/include/mach/sdram_config.h | 161 +
arch/arm/mach-socfpga/include/mach/sequencer.c | 4324 ++++++++++++++++++++
arch/arm/mach-socfpga/include/mach/sequencer.h | 448 ++
arch/arm/mach-socfpga/include/mach/socfpga-regs.h | 20 +
.../arm/mach-socfpga/include/mach/system-manager.h | 68 +
arch/arm/mach-socfpga/init.c | 58 +
arch/arm/mach-socfpga/iocsr-config-cyclone5.c | 649 +++
arch/arm/mach-socfpga/nic301.c | 40 +
arch/arm/mach-socfpga/reset-manager.c | 51 +
arch/arm/mach-socfpga/scan-manager.c | 220 +
arch/arm/mach-socfpga/system-manager.c | 33 +
arch/arm/mach-socfpga/xload.c | 125 +
drivers/clk/Kconfig | 5 +
drivers/clk/Makefile | 1 +
drivers/clk/clk.c | 7 +
drivers/clk/socfpga.c | 412 ++
drivers/of/partition.c | 3 +
drivers/serial/serial_ns16550.c | 2 +
images/.gitignore | 1 +
images/Makefile | 3 +-
images/Makefile.socfpga | 34 +
include/linux/clk.h | 1 +
scripts/.gitignore | 1 +
scripts/Makefile | 1 +
scripts/socfpga_mkimage.c | 287 ++
78 files changed, 12164 insertions(+), 15 deletions(-)
create mode 100644 arch/arm/boards/ebv-socrates/Makefile
create mode 100644 arch/arm/boards/ebv-socrates/board.c
create mode 100644 arch/arm/boards/ebv-socrates/config.h
create mode 100644 arch/arm/boards/ebv-socrates/lowlevel.c
create mode 100644 arch/arm/boards/ebv-socrates/pinmux_config.c
create mode 100644 arch/arm/boards/ebv-socrates/pll_config.h
create mode 100644 arch/arm/boards/ebv-socrates/sdram_config.h
create mode 100644 arch/arm/boards/ebv-socrates/sequencer_auto.h
create mode 100644 arch/arm/boards/ebv-socrates/sequencer_auto_ac_init.c
create mode 100644 arch/arm/boards/ebv-socrates/sequencer_auto_inst_init.c
create mode 100644 arch/arm/boards/ebv-socrates/sequencer_defines.h
create mode 100644 arch/arm/boards/terasic-sockit/Makefile
create mode 100644 arch/arm/boards/terasic-sockit/board.c
create mode 100644 arch/arm/boards/terasic-sockit/config.h
create mode 100644 arch/arm/boards/terasic-sockit/lowlevel.c
create mode 100644 arch/arm/boards/terasic-sockit/pinmux_config.c
create mode 100644 arch/arm/boards/terasic-sockit/pll_config.h
create mode 100644 arch/arm/boards/terasic-sockit/sdram_config.h
create mode 100644 arch/arm/boards/terasic-sockit/sequencer_auto.h
create mode 100644 arch/arm/boards/terasic-sockit/sequencer_auto_ac_init.c
create mode 100644 arch/arm/boards/terasic-sockit/sequencer_auto_inst_init.c
create mode 100644 arch/arm/boards/terasic-sockit/sequencer_defines.h
create mode 100644 arch/arm/configs/socfpga-xload_defconfig
create mode 100644 arch/arm/configs/socfpga_defconfig
create mode 100644 arch/arm/dts/socfpga.dtsi
create mode 100644 arch/arm/dts/socfpga_cyclone5.dtsi
create mode 100644 arch/arm/dts/socfpga_cyclone5_sockit.dts
create mode 100644 arch/arm/dts/socfpga_cyclone5_socrates.dts
create mode 100644 arch/arm/mach-socfpga/Kconfig
create mode 100644 arch/arm/mach-socfpga/Makefile
create mode 100644 arch/arm/mach-socfpga/bootsource.c
create mode 100644 arch/arm/mach-socfpga/clock-manager.c
create mode 100644 arch/arm/mach-socfpga/fpga.c
create mode 100644 arch/arm/mach-socfpga/freeze-controller.c
create mode 100644 arch/arm/mach-socfpga/generic.c
create mode 100644 arch/arm/mach-socfpga/include/mach/clkdev.h
create mode 100644 arch/arm/mach-socfpga/include/mach/clock-manager.h
create mode 100644 arch/arm/mach-socfpga/include/mach/debug_ll.h
create mode 100644 arch/arm/mach-socfpga/include/mach/freeze-controller.h
create mode 100644 arch/arm/mach-socfpga/include/mach/generic.h
create mode 100644 arch/arm/mach-socfpga/include/mach/nic301.h
create mode 100644 arch/arm/mach-socfpga/include/mach/pll_config.h
create mode 100644 arch/arm/mach-socfpga/include/mach/reset-manager.h
create mode 100644 arch/arm/mach-socfpga/include/mach/scan-manager.h
create mode 100644 arch/arm/mach-socfpga/include/mach/sdram.h
create mode 100644 arch/arm/mach-socfpga/include/mach/sdram_config.h
create mode 100644 arch/arm/mach-socfpga/include/mach/sequencer.c
create mode 100644 arch/arm/mach-socfpga/include/mach/sequencer.h
create mode 100644 arch/arm/mach-socfpga/include/mach/socfpga-regs.h
create mode 100644 arch/arm/mach-socfpga/include/mach/system-manager.h
create mode 100644 arch/arm/mach-socfpga/init.c
create mode 100644 arch/arm/mach-socfpga/iocsr-config-cyclone5.c
create mode 100644 arch/arm/mach-socfpga/nic301.c
create mode 100644 arch/arm/mach-socfpga/reset-manager.c
create mode 100644 arch/arm/mach-socfpga/scan-manager.c
create mode 100644 arch/arm/mach-socfpga/system-manager.c
create mode 100644 arch/arm/mach-socfpga/xload.c
create mode 100644 drivers/clk/socfpga.c
create mode 100644 images/Makefile.socfpga
create mode 100644 scripts/socfpga_mkimage.c
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* [PATCH 01/11] ARM: invalidate caches thoroughly
From: Sascha Hauer @ 2013-09-16 8:48 UTC (permalink / raw)
To: barebox
In-Reply-To: <1379321300-8085-1-git-send-email-s.hauer@pengutronix.de>
The data caches should be invalided once during startup. This should
also be done when we do not have the MMU enabled in barebox because
the Kernel does not invalidate the caches during start.
To make this sure this patch enables the arm_early_mmu_cache_invalidate
function even if MMU support is disabled. Additionally this patch adds
calls to arm_early_mmu_cache_invalidate in start.c and uncompress.c.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/cpu/Makefile | 6 +++---
arch/arm/cpu/start.c | 4 +++-
arch/arm/cpu/uncompress.c | 2 ++
arch/arm/include/asm/cache.h | 10 ----------
4 files changed, 8 insertions(+), 14 deletions(-)
diff --git a/arch/arm/cpu/Makefile b/arch/arm/cpu/Makefile
index c3635a1..aba201b 100644
--- a/arch/arm/cpu/Makefile
+++ b/arch/arm/cpu/Makefile
@@ -10,7 +10,7 @@ obj-$(CONFIG_CMD_ARM_CPUINFO) += cpuinfo.o
obj-$(CONFIG_CMD_ARM_MMUINFO) += mmuinfo.o
obj-$(CONFIG_OFDEVICE) += dtb.o
obj-$(CONFIG_MMU) += mmu.o cache.o mmu-early.o
-pbl-$(CONFIG_MMU) += cache.o mmu-early.o
+pbl-$(CONFIG_MMU) += mmu-early.o
obj-$(CONFIG_CPU_32v4T) += cache-armv4.o
pbl-$(CONFIG_CPU_32v4T) += cache-armv4.o
obj-$(CONFIG_CPU_32v5) += cache-armv5.o
@@ -25,7 +25,7 @@ pbl-y += setupc.o
pbl-$(CONFIG_PBL_SINGLE_IMAGE) += start-pbl.o
pbl-$(CONFIG_PBL_MULTI_IMAGES) += start-images.o uncompress.o
-obj-y += common.o
-pbl-y += common.o
+obj-y += common.o cache.o
+pbl-y += common.o cache.o
lwl-y += lowlevel.o
diff --git a/arch/arm/cpu/start.c b/arch/arm/cpu/start.c
index 1f397ec..f8d343f 100644
--- a/arch/arm/cpu/start.c
+++ b/arch/arm/cpu/start.c
@@ -70,8 +70,10 @@ static noinline __noreturn void __start(uint32_t membase, uint32_t memsize,
endmem &= ~0x3fff;
endmem -= SZ_16K; /* ttb */
- if (!IS_ENABLED(CONFIG_PBL_IMAGE))
+ if (!IS_ENABLED(CONFIG_PBL_IMAGE)) {
+ arm_early_mmu_cache_invalidate();
mmu_early_enable(membase, memsize, endmem);
+ }
}
/*
diff --git a/arch/arm/cpu/uncompress.c b/arch/arm/cpu/uncompress.c
index b401f8e..b0819c7 100644
--- a/arch/arm/cpu/uncompress.c
+++ b/arch/arm/cpu/uncompress.c
@@ -54,6 +54,8 @@ static void noinline uncompress(uint32_t membase,
uint32_t *ptr;
void *pg_start;
+ arm_early_mmu_cache_invalidate();
+
endmem -= STACK_SIZE; /* stack */
if (IS_ENABLED(CONFIG_PBL_RELOCATABLE))
diff --git a/arch/arm/include/asm/cache.h b/arch/arm/include/asm/cache.h
index f5f8bf3..2f6eab0 100644
--- a/arch/arm/include/asm/cache.h
+++ b/arch/arm/include/asm/cache.h
@@ -8,17 +8,7 @@ static inline void flush_icache(void)
int arm_set_cache_functions(void);
-#ifdef CONFIG_MMU
void arm_early_mmu_cache_flush(void);
void arm_early_mmu_cache_invalidate(void);
-#else
-static inline void arm_early_mmu_cache_flush(void)
-{
-}
-
-static inline void arm_early_mmu_cache_invalidate(void)
-{
-}
-#endif
#endif
--
1.8.4.rc3
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* [PATCH 11/11] ARM: Altera SoCFPGA: Add defconfig files
From: Sascha Hauer @ 2013-09-16 8:48 UTC (permalink / raw)
To: barebox
In-Reply-To: <1379321300-8085-1-git-send-email-s.hauer@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/configs/socfpga-xload_defconfig | 30 +++++++++++
arch/arm/configs/socfpga_defconfig | 89 ++++++++++++++++++++++++++++++++
2 files changed, 119 insertions(+)
create mode 100644 arch/arm/configs/socfpga-xload_defconfig
create mode 100644 arch/arm/configs/socfpga_defconfig
diff --git a/arch/arm/configs/socfpga-xload_defconfig b/arch/arm/configs/socfpga-xload_defconfig
new file mode 100644
index 0000000..716b2ac
--- /dev/null
+++ b/arch/arm/configs/socfpga-xload_defconfig
@@ -0,0 +1,30 @@
+CONFIG_ARCH_SOCFPGA=y
+CONFIG_ARCH_SOCFPGA_XLOAD=y
+CONFIG_MACH_SOCFPGA_TERASIC_SOCKIT=y
+CONFIG_MACH_SOCFPGA_EBV_SOCRATES=y
+CONFIG_THUMB2_BAREBOX=y
+# CONFIG_CMD_ARM_CPUINFO is not set
+CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
+# CONFIG_ARM_EXCEPTIONS is not set
+# CONFIG_MEMINFO is not set
+CONFIG_PBL_IMAGE=y
+CONFIG_PBL_RELOCATABLE=y
+CONFIG_MMU=y
+CONFIG_TEXT_BASE=0x0
+CONFIG_MALLOC_SIZE=0x0
+CONFIG_MALLOC_DUMMY=y
+CONFIG_RELOCATABLE=y
+CONFIG_SHELL_NONE=y
+# CONFIG_ERRNO_MESSAGES is not set
+# CONFIG_TIMESTAMP is not set
+# CONFIG_DEFAULT_ENVIRONMENT is not set
+CONFIG_DRIVER_SERIAL_NS16550=y
+CONFIG_MCI=y
+CONFIG_MCI_STARTUP=y
+# CONFIG_MCI_WRITE is not set
+CONFIG_MCI_DW=y
+CONFIG_MFD_MC13XXX=y
+CONFIG_EEPROM_AT25=y
+# CONFIG_FS_RAMFS is not set
+# CONFIG_FS_DEVFS is not set
+CONFIG_FS_FAT=y
diff --git a/arch/arm/configs/socfpga_defconfig b/arch/arm/configs/socfpga_defconfig
new file mode 100644
index 0000000..0c5a6a7
--- /dev/null
+++ b/arch/arm/configs/socfpga_defconfig
@@ -0,0 +1,89 @@
+CONFIG_ARCH_SOCFPGA=y
+CONFIG_ARCH_SOCFPGA_FPGA=y
+CONFIG_MACH_SOCFPGA_EBV_SOCRATES=y
+CONFIG_MACH_SOCFPGA_TERASIC_SOCKIT=y
+CONFIG_THUMB2_BAREBOX=y
+CONFIG_CMD_ARM_MMUINFO=y
+CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
+CONFIG_ARM_UNWIND=y
+CONFIG_MMU=y
+CONFIG_TEXT_BASE=0x0
+CONFIG_MALLOC_SIZE=0x0
+CONFIG_MALLOC_TLSF=y
+CONFIG_KALLSYMS=y
+CONFIG_RELOCATABLE=y
+CONFIG_LONGHELP=y
+CONFIG_HUSH_FANCY_PROMPT=y
+CONFIG_CMDLINE_EDITING=y
+CONFIG_AUTO_COMPLETE=y
+CONFIG_MENU=y
+# CONFIG_TIMESTAMP is not set
+CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y
+CONFIG_CMD_EDIT=y
+CONFIG_CMD_SLEEP=y
+CONFIG_CMD_MSLEEP=y
+CONFIG_CMD_SAVEENV=y
+CONFIG_CMD_EXPORT=y
+CONFIG_CMD_PRINTENV=y
+CONFIG_CMD_READLINE=y
+CONFIG_CMD_LET=y
+CONFIG_CMD_MENU=y
+CONFIG_CMD_MENU_MANAGEMENT=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_LN=y
+CONFIG_CMD_FILETYPE=y
+CONFIG_CMD_ECHO_E=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_IOMEM=y
+CONFIG_CMD_MM=y
+CONFIG_CMD_CRC=y
+CONFIG_CMD_CRC_CMP=y
+CONFIG_CMD_MD5SUM=y
+CONFIG_CMD_BOOTM_SHOW_TYPE=y
+CONFIG_CMD_BOOTM_VERBOSE=y
+CONFIG_CMD_BOOTM_INITRD=y
+CONFIG_CMD_BOOTM_OFTREE=y
+CONFIG_CMD_RESET=y
+CONFIG_CMD_GO=y
+CONFIG_CMD_OFTREE=y
+CONFIG_CMD_OF_PROPERTY=y
+CONFIG_CMD_OF_NODE=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_BAREBOX_UPDATE=y
+CONFIG_CMD_TIMEOUT=y
+CONFIG_CMD_PARTITION=y
+CONFIG_CMD_MAGICVAR=y
+CONFIG_CMD_MAGICVAR_HELP=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_UNCOMPRESS=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_LED=y
+CONFIG_CMD_LED_TRIGGER=y
+CONFIG_CMD_MIITOOL=y
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DETECT=y
+CONFIG_NET=y
+CONFIG_NET_DHCP=y
+CONFIG_NET_PING=y
+CONFIG_NET_NETCONSOLE=y
+CONFIG_NET_RESOLV=y
+CONFIG_OFDEVICE=y
+CONFIG_OF_BAREBOX_DRIVERS=y
+CONFIG_DRIVER_SERIAL_NS16550=y
+CONFIG_DRIVER_NET_DESIGNWARE=y
+CONFIG_MCI=y
+CONFIG_MCI_DW=y
+CONFIG_MFD_MC13XXX=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_LED_GPIO_OF=y
+CONFIG_LED_TRIGGERS=y
+CONFIG_EEPROM_AT25=y
+CONFIG_KEYBOARD_GPIO=y
+CONFIG_GPIO_DESIGNWARE=y
+CONFIG_FS_EXT4=y
+CONFIG_FS_TFTP=y
+CONFIG_FS_NFS=y
+CONFIG_FS_FAT=y
+CONFIG_FS_FAT_WRITE=y
+CONFIG_FS_FAT_LFN=y
--
1.8.4.rc3
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* [PATCH 04/11] serial: ns16550: Add compatible entry for snps, dw-apb-uart
From: Sascha Hauer @ 2013-09-16 8:48 UTC (permalink / raw)
To: barebox
In-Reply-To: <1379321300-8085-1-git-send-email-s.hauer@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
drivers/serial/serial_ns16550.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/serial/serial_ns16550.c b/drivers/serial/serial_ns16550.c
index 5899d57..bb1c2ae 100644
--- a/drivers/serial/serial_ns16550.c
+++ b/drivers/serial/serial_ns16550.c
@@ -310,6 +310,8 @@ err:
static struct of_device_id ns16550_serial_dt_ids[] = {
{
.compatible = "ns16550a",
+ },{
+ .compatible = "snps,dw-apb-uart",
}, {
/* sentinel */
},
--
1.8.4.rc3
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* [PATCH 02/11] clk: of: introduce of_clk_src_simple_get
From: Sascha Hauer @ 2013-09-16 8:48 UTC (permalink / raw)
To: barebox
In-Reply-To: <1379321300-8085-1-git-send-email-s.hauer@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
drivers/clk/clk.c | 7 +++++++
include/linux/clk.h | 1 +
2 files changed, 8 insertions(+)
diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
index 7ec3d93..5942e29 100644
--- a/drivers/clk/clk.c
+++ b/drivers/clk/clk.c
@@ -273,6 +273,13 @@ struct of_clk_provider {
static LIST_HEAD(of_clk_providers);
+struct clk *of_clk_src_simple_get(struct of_phandle_args *clkspec,
+ void *data)
+{
+ return data;
+}
+EXPORT_SYMBOL_GPL(of_clk_src_simple_get);
+
struct clk *of_clk_src_onecell_get(struct of_phandle_args *clkspec, void *data)
{
struct clk_onecell_data *clk_data = data;
diff --git a/include/linux/clk.h b/include/linux/clk.h
index 6aed1de..4778400 100644
--- a/include/linux/clk.h
+++ b/include/linux/clk.h
@@ -290,6 +290,7 @@ struct clk_onecell_data {
unsigned int clk_num;
};
struct clk *of_clk_src_onecell_get(struct of_phandle_args *clkspec, void *data);
+struct clk *of_clk_src_simple_get(struct of_phandle_args *clkspec, void *data);
struct clk *of_clk_get(struct device_node *np, int index);
struct clk *of_clk_get_by_name(struct device_node *np, const char *name);
--
1.8.4.rc3
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* [PATCH 03/11] of: partition: Check for valid partition name
From: Sascha Hauer @ 2013-09-16 8:48 UTC (permalink / raw)
To: barebox
In-Reply-To: <1379321300-8085-1-git-send-email-s.hauer@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
drivers/of/partition.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/of/partition.c b/drivers/of/partition.c
index 7199eff..5ed44a8 100644
--- a/drivers/of/partition.c
+++ b/drivers/of/partition.c
@@ -47,6 +47,9 @@ struct cdev *of_parse_partition(struct cdev *cdev, struct device_node *node)
partname = of_get_property(node, "label", &len);
if (!partname)
partname = of_get_property(node, "name", &len);
+ if (!partname)
+ return NULL;
+
name = (char *)partname;
debug("add partition: %s.%s 0x%08lx 0x%08lx\n", cdev->name, partname, offset, size);
--
1.8.4.rc3
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* Re: [PATCH 2/4] login: disable input console if password wrong
From: Sascha Hauer @ 2013-09-16 8:33 UTC (permalink / raw)
To: Jean-Christophe PLAGNIOL-VILLARD; +Cc: barebox
In-Reply-To: <1379244654-30716-2-git-send-email-plagnioj@jcrosoft.com>
On Sun, Sep 15, 2013 at 01:30:52PM +0200, Jean-Christophe PLAGNIOL-VILLARD wrote:
> so we guarantee that barebox is secured again user interaction
>
> +static bool console_input_allow = false;
> +
> +static int console_input_allow_set(struct device_d *dev, struct param_d *p, const char *val)
> +{
> + int ret = dev_param_set_generic(dev, p, val);
> +
> + if (val && simple_strtoul(val, NULL, 10))
> + console_input_allow = true;
> + else
> + console_input_allow = false;
> +
> + return ret;
> +}
> +
> +static int console_global_init(void)
> +{
> + globalvar_add("console.input_allow", console_input_allow_set, NULL, 0);
> +
> + if (IS_ENABLED(CONFIG_CMD_LOGIN) && is_passwd_enable())
> + setenv("global.console.input_allow", "0");
> + else
> + setenv("global.console.input_allow", "1");
> +
> + return 0;
> +}
> +late_initcall(console_global_init);
With the attached patch applied the above would go down to:
static int console_input_allow;
static int console_global_init(void)
{
dev_add_param_bool(&global_device, "console.input_allow",
NULL, NULL, &console_input_allow, NULL);
return 0;
}
late_initcall(console_global_init);
8<----------------------------------------------------------------------
From ae4a37fce8637280751fa75a58ea658b61c3a190 Mon Sep 17 00:00:00 2001
From: Sascha Hauer <s.hauer@pengutronix.de>
Date: Mon, 16 Sep 2013 10:17:26 +0200
Subject: [PATCH] globalvar: Make global_device global
This makes global_device accessible globally so that global variables
of a certain type can be added with dev_add_param_*
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
common/globalvar.c | 2 +-
include/globalvar.h | 3 +++
2 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/common/globalvar.c b/common/globalvar.c
index edb66dd..6ef4a6a 100644
--- a/common/globalvar.c
+++ b/common/globalvar.c
@@ -6,7 +6,7 @@
#include <magicvar.h>
#include <generated/utsrelease.h>
-static struct device_d global_device = {
+struct device_d global_device = {
.name = "global",
.id = DEVICE_ID_SINGLE,
};
diff --git a/include/globalvar.h b/include/globalvar.h
index c2a13b3..a9d01d4 100644
--- a/include/globalvar.h
+++ b/include/globalvar.h
@@ -2,6 +2,9 @@
#define __GLOBALVAR_H
#include <param.h>
+#include <driver.h>
+
+extern struct device_d global_device;
#ifdef CONFIG_GLOBALVAR
int globalvar_add_simple(const char *name, const char *value);
--
1.8.4.rc3
--
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* Re: [PATCH 1/4] login: add globalvar timeout support
From: Sascha Hauer @ 2013-09-16 8:02 UTC (permalink / raw)
To: Jean-Christophe PLAGNIOL-VILLARD; +Cc: barebox
In-Reply-To: <1379244654-30716-1-git-send-email-plagnioj@jcrosoft.com>
On Sun, Sep 15, 2013 at 01:30:51PM +0200, Jean-Christophe PLAGNIOL-VILLARD wrote:
> Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
> ---
> commands/login.c | 26 ++++++++++++++++++++++++++
> 1 file changed, 26 insertions(+)
>
> diff --git a/commands/login.c b/commands/login.c
> index fb6bb35..f5429bc 100644
> --- a/commands/login.c
> +++ b/commands/login.c
> @@ -20,6 +20,10 @@
> #include <complete.h>
> #include <password.h>
> #include <getopt.h>
> +#include <environment.h>
> +#include <globalvar.h>
> +#include <magicvar.h>
> +#include <init.h>
>
> #define PASSWD_MAX_LENGTH (128 + 1)
>
> @@ -31,6 +35,16 @@
> #define LOGIN_MODE HIDE
> #endif
>
> +static void login_getenv_int(const char *name, int *i)
> +{
> + const char* str = getenv(name);
> +
> + if (!str)
> + return;
> +
> + *i = simple_strtoul(str, NULL, 10);
> +}
We already have getenv_ull. Should we use it here?
> +
> static int do_login(int argc, char *argv[])
> {
> unsigned char passwd[PASSWD_MAX_LENGTH];
> @@ -38,6 +52,8 @@ static int do_login(int argc, char *argv[])
> int timeout = 0;
> char *timeout_cmd = "boot";
>
> + login_getenv_int("global.login.timeout", &timeout);
> +
> if (!is_passwd_enable()) {
> puts("login: password not set\n");
> return 0;
> @@ -80,3 +96,13 @@ BAREBOX_CMD_START(login)
> BAREBOX_CMD_HELP(cmd_login_help)
> BAREBOX_CMD_COMPLETE(empty_complete)
> BAREBOX_CMD_END
> +
> +static int login_global_init(void)
> +{
> + globalvar_add_simple("login.timeout");
globalvar_add_simple now takes an initial value, like this:
int globalvar_add_simple(const char *name, const char *value)
Sascha
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
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^ permalink raw reply
* Re: [PATCH 1/1] genenv: ignore *.orig file too
From: Sascha Hauer @ 2013-09-16 7:55 UTC (permalink / raw)
To: Jean-Christophe PLAGNIOL-VILLARD; +Cc: barebox
In-Reply-To: <1379175785-6885-1-git-send-email-plagnioj@jcrosoft.com>
On Sat, Sep 14, 2013 at 06:23:05PM +0200, Jean-Christophe PLAGNIOL-VILLARD wrote:
> Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
> ---
> scripts/genenv | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/scripts/genenv b/scripts/genenv
> index 374db6d..02af767 100755
> --- a/scripts/genenv
> +++ b/scripts/genenv
> @@ -24,7 +24,7 @@ for i in $*; do
> done
> )
>
> -find $tempdir -name '.svn' -o -name '*~' | xargs --no-run-if-empty rm -r
> +find $tempdir -name '*.orig' -o -name '.svn' -o -name '*~' | xargs --no-run-if-empty rm -r
Should we ignore *.rej aswell?
Sascha
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
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^ permalink raw reply
* [PATCH 3/4] login/passwd: add default password support
From: Jean-Christophe PLAGNIOL-VILLARD @ 2013-09-15 11:30 UTC (permalink / raw)
To: barebox
In-Reply-To: <1379244654-30716-1-git-send-email-plagnioj@jcrosoft.com>
even if the env is broken you will have a password
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
---
commands/passwd.c | 8 ++---
common/Kconfig | 5 +++
common/Makefile | 18 +++++++++++
common/password.c | 94 ++++++++++++++++++++++++++++++++++++++++++++++--------
include/password.h | 22 ++++++++++---
5 files changed, 125 insertions(+), 22 deletions(-)
diff --git a/commands/passwd.c b/commands/passwd.c
index baccfa6..368c401 100644
--- a/commands/passwd.c
+++ b/commands/passwd.c
@@ -63,7 +63,7 @@ static int do_passwd(int argc, char *argv[])
goto err;
}
- ret = set_passwd(passwd1, passwd1_len);
+ ret = set_env_passwd(passwd1, passwd1_len);
if (ret < 0) {
puts("Sorry, passwords write failed\n");
@@ -78,15 +78,15 @@ err:
return 1;
disable:
- passwd_disable();
+ passwd_env_disable();
puts("passwd: password disabled\n");
return ret;
}
static const __maybe_unused char cmd_passwd_help[] =
"Usage: passwd\n"
-"passwd allow you to specify a password\n"
-"to disable it put an empty password\n"
+"passwd allow you to specify a password in the env\n"
+"to disable it put an empty password will still use the default password if set\n"
;
BAREBOX_CMD_START(passwd)
diff --git a/common/Kconfig b/common/Kconfig
index dd70578..5d92284 100644
--- a/common/Kconfig
+++ b/common/Kconfig
@@ -385,6 +385,11 @@ config PASSWORD
help
allow you to have password protection framework
+config PASSWORD_DEFAULT
+ string
+ prompt "Password default"
+ depends on PASSWORD
+
if PASSWORD
choice
diff --git a/common/Makefile b/common/Makefile
index 64eacc3..f8e2dee 100644
--- a/common/Makefile
+++ b/common/Makefile
@@ -114,6 +114,24 @@ cmd_env_h = cat $< | (cd $(obj) && $(objtree)/scripts/bin2c default_environment)
$(obj)/barebox_default_env.h: $(obj)/barebox_default_env$(barebox_default_env_comp) FORCE
$(call if_changed,env_h)
+quiet_cmd_pwd_h = PWDH $@
+ifneq ($(CONFIG_PASSWORD_DEFAULT),"")
+PASSWD_FILE := $(shell cd $(srctree); find $(CONFIG_PASSWORD_DEFAULT) -type f)
+cmd_pwd_h = echo -n "const char default_passwd[] = \"" > $@; \
+ cat $< | tr -d '\n' >> $@; \
+ echo "\";" >> $@
+
+include/generated/passwd.h: $(PASSWD_FILE)
+ $(call if_changed,pwd_h)
+else
+cmd_pwd_h = echo "const char default_passwd[] = \"\";" > $@
+
+include/generated/passwd.h: FORCE
+ $(call if_changed,pwd_h)
+endif
+
+$(obj)/password.o: include/generated/passwd.h
+
# dependencies on generated files need to be listed explicitly
$(obj)/version.o: include/generated/compile.h
diff --git a/common/password.c b/common/password.c
index d157a11..9c1e54a 100644
--- a/common/password.c
+++ b/common/password.c
@@ -25,6 +25,7 @@
#include <malloc.h>
#include <xfuncs.h>
#include <clock.h>
+#include <generated/passwd.h>
#if defined(CONFIG_PASSWD_SUM_MD5)
#define PASSWD_SUM "md5"
@@ -97,7 +98,13 @@ int password(unsigned char *passwd, size_t length, int flags, int timeout)
}
EXPORT_SYMBOL(password);
-int is_passwd_enable(void)
+int is_passwd_default_enable(void)
+{
+ return strlen(default_passwd) > 0;
+}
+EXPORT_SYMBOL(is_passwd_default_enable);
+
+int is_passwd_env_enable(void)
{
int fd;
@@ -110,13 +117,13 @@ int is_passwd_enable(void)
return 1;
}
-EXPORT_SYMBOL(is_passwd_enable);
+EXPORT_SYMBOL(is_passwd_env_enable);
-int passwd_disable(void)
+int passwd_env_disable(void)
{
return unlink(PASSWD_FILE);
}
-EXPORT_SYMBOL(passwd_disable);
+EXPORT_SYMBOL(passwd_env_disable);
static unsigned char to_digit(unsigned char c)
{
@@ -140,6 +147,43 @@ static unsigned char to_hexa(unsigned char c)
int read_passwd(unsigned char *sum, size_t length)
{
+ if (is_passwd_env_enable())
+ return read_env_passwd(sum, length);
+ else if (is_passwd_default_enable())
+ return read_default_passwd(sum, length);
+ else
+ return -EINVAL;
+}
+
+int read_default_passwd(unsigned char *sum, size_t length)
+{
+ int i = 0;
+ int len = strlen(default_passwd);
+ unsigned char *buf = (unsigned char *)default_passwd;
+ unsigned char c;
+
+ if (!sum || length < 1)
+ return -EINVAL;
+
+ for (i = 0; i < len && length > 0; i++) {
+ c = buf[i];
+ i++;
+
+ *sum = to_digit(c) << 4;
+
+ c = buf[i];
+
+ *sum |= to_digit(c);
+ sum++;
+ length--;
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL(read_default_passwd);
+
+int read_env_passwd(unsigned char *sum, size_t length)
+{
int fd;
int ret = 0;
unsigned char c;
@@ -178,9 +222,9 @@ exit:
return ret;
}
-EXPORT_SYMBOL(read_passwd);
+EXPORT_SYMBOL(read_env_passwd);
-int write_passwd(unsigned char *sum, size_t length)
+int write_env_passwd(unsigned char *sum, size_t length)
{
int fd;
unsigned char c;
@@ -227,9 +271,9 @@ exit:
return ret;
}
-EXPORT_SYMBOL(write_passwd);
+EXPORT_SYMBOL(write_env_passwd);
-int check_passwd(unsigned char* passwd, size_t length)
+static int __check_passwd(unsigned char* passwd, size_t length, int std)
{
struct digest *d;
unsigned char *passwd1_sum;
@@ -256,7 +300,10 @@ int check_passwd(unsigned char* passwd, size_t length)
d->final(d, passwd1_sum);
- ret = read_passwd(passwd2_sum, d->length);
+ if (std)
+ ret = read_env_passwd(passwd2_sum, d->length);
+ else
+ ret = read_default_passwd(passwd2_sum, d->length);
if (ret < 0)
goto err2;
@@ -271,9 +318,30 @@ err1:
return ret;
}
-EXPORT_SYMBOL(check_passwd);
-int set_passwd(unsigned char* passwd, size_t length)
+int check_default_passwd(unsigned char* passwd, size_t length)
+{
+ return __check_passwd(passwd, length, 0);
+}
+EXPORT_SYMBOL(check_default_passwd);
+
+int check_env_passwd(unsigned char* passwd, size_t length)
+{
+ return __check_passwd(passwd, length, 1);
+}
+EXPORT_SYMBOL(check_env_passwd);
+
+int check_passwd(unsigned char* passwd, size_t length)
+{
+ if (is_passwd_env_enable())
+ return check_env_passwd(passwd, length);
+ else if (is_passwd_default_enable())
+ return check_default_passwd(passwd, length);
+ else
+ return -EINVAL;
+}
+
+int set_env_passwd(unsigned char* passwd, size_t length)
{
struct digest *d;
unsigned char *passwd_sum;
@@ -292,10 +360,10 @@ int set_passwd(unsigned char* passwd, size_t length)
d->final(d, passwd_sum);
- ret = write_passwd(passwd_sum, d->length);
+ ret = write_env_passwd(passwd_sum, d->length);
free(passwd_sum);
return ret;
}
-EXPORT_SYMBOL(set_passwd);
+EXPORT_SYMBOL(set_env_passwd);
diff --git a/include/password.h b/include/password.h
index df03cd7..0dd1054 100644
--- a/include/password.h
+++ b/include/password.h
@@ -28,11 +28,23 @@
int password(unsigned char *passwd, size_t length, int flags, int timeout);
int read_passwd(unsigned char *sum, size_t length);
-int write_passwd(unsigned char *sum, size_t length);
-
-int is_passwd_enable(void);
-int passwd_disable(void);
int check_passwd(unsigned char* passwd, size_t length);
-int set_passwd(unsigned char* passwd, size_t length);
+
+int read_env_passwd(unsigned char *sum, size_t length);
+int write_env_passwd(unsigned char *sum, size_t length);
+
+int read_default_passwd(unsigned char *sum, size_t length);
+int is_passwd_default_enable(void);
+int check_default_passwd(unsigned char* passwd, size_t length);
+
+int is_passwd_env_enable(void);
+int passwd_env_disable(void);
+int check_env_passwd(unsigned char* passwd, size_t length);
+int set_env_passwd(unsigned char* passwd, size_t length);
+
+static inline int is_passwd_enable(void)
+{
+ return is_passwd_default_enable() || is_passwd_env_enable();
+}
#endif /* __PASSWORD_H__ */
--
1.8.4.rc1
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^ permalink raw reply related
* [PATCH 2/4] login: disable input console if password wrong
From: Jean-Christophe PLAGNIOL-VILLARD @ 2013-09-15 11:30 UTC (permalink / raw)
To: barebox
In-Reply-To: <1379244654-30716-1-git-send-email-plagnioj@jcrosoft.com>
so we guarantee that barebox is secured again user interaction
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
---
commands/login.c | 6 +++++-
common/console.c | 6 ++++++
common/console_common.c | 45 +++++++++++++++++++++++++++++++++++++++++++++
common/console_simple.c | 9 ++++++++-
common/startup.c | 2 ++
include/console.h | 3 +++
6 files changed, 69 insertions(+), 2 deletions(-)
diff --git a/commands/login.c b/commands/login.c
index f5429bc..cc11afb 100644
--- a/commands/login.c
+++ b/commands/login.c
@@ -24,6 +24,7 @@
#include <globalvar.h>
#include <magicvar.h>
#include <init.h>
+#include <console.h>
#define PASSWD_MAX_LENGTH (128 + 1)
@@ -54,6 +55,7 @@ static int do_login(int argc, char *argv[])
login_getenv_int("global.login.timeout", &timeout);
+ console_allow_input(true);
if (!is_passwd_enable()) {
puts("login: password not set\n");
return 0;
@@ -74,8 +76,10 @@ static int do_login(int argc, char *argv[])
puts("Password: ");
passwd_len = password(passwd, PASSWD_MAX_LENGTH, LOGIN_MODE, timeout);
- if (passwd_len < 0)
+ if (passwd_len < 0) {
+ console_allow_input(false);
run_command(timeout_cmd, 0);
+ }
if (check_passwd(passwd, passwd_len))
return 0;
diff --git a/common/console.c b/common/console.c
index 6ca94e2..4931829 100644
--- a/common/console.c
+++ b/common/console.c
@@ -236,6 +236,9 @@ int getc(void)
unsigned char ch;
uint64_t start;
+ if (unlikely(!console_is_input_allow()))
+ return -EPERM;
+
/*
* For 100us we read the characters from the serial driver
* into a kfifo. This helps us not to lose characters
@@ -270,6 +273,9 @@ EXPORT_SYMBOL(fgetc);
int tstc(void)
{
+ if (unlikely(!console_is_input_allow()))
+ return 0;
+
return kfifo_len(console_input_fifo) || tstc_raw();
}
EXPORT_SYMBOL(tstc);
diff --git a/common/console_common.c b/common/console_common.c
index d139d1a..f8046b1 100644
--- a/common/console_common.c
+++ b/common/console_common.c
@@ -21,9 +21,54 @@
#include <common.h>
#include <fs.h>
#include <errno.h>
+#include <console.h>
+#include <init.h>
+#include <environment.h>
+#include <globalvar.h>
+#include <magicvar.h>
+#include <password.h>
#ifndef CONFIG_CONSOLE_NONE
+static bool console_input_allow = false;
+
+static int console_input_allow_set(struct device_d *dev, struct param_d *p, const char *val)
+{
+ int ret = dev_param_set_generic(dev, p, val);
+
+ if (val && simple_strtoul(val, NULL, 10))
+ console_input_allow = true;
+ else
+ console_input_allow = false;
+
+ return ret;
+}
+
+static int console_global_init(void)
+{
+ globalvar_add("console.input_allow", console_input_allow_set, NULL, 0);
+
+ if (IS_ENABLED(CONFIG_CMD_LOGIN) && is_passwd_enable())
+ setenv("global.console.input_allow", "0");
+ else
+ setenv("global.console.input_allow", "1");
+
+ return 0;
+}
+late_initcall(console_global_init);
+
+BAREBOX_MAGICVAR_NAMED(global_console_input_allow, global.console.input_allow, "console input allowed");
+
+bool console_is_input_allow(void)
+{
+ return console_input_allow;
+}
+
+void console_allow_input(bool val)
+{
+ console_input_allow = val;
+}
+
int printf(const char *fmt, ...)
{
va_list args;
diff --git a/common/console_simple.c b/common/console_simple.c
index 101064b..bf6491d 100644
--- a/common/console_simple.c
+++ b/common/console_simple.c
@@ -3,6 +3,7 @@
#include <fs.h>
#include <errno.h>
#include <debug_ll.h>
+#include <console.h>
LIST_HEAD(console_list);
EXPORT_SYMBOL(console_list);
@@ -40,6 +41,9 @@ EXPORT_SYMBOL(console_putc);
int tstc(void)
{
+ if (unlikely(!console_is_input_allow()))
+ return 0;
+
if (!console)
return 0;
@@ -48,7 +52,10 @@ int tstc(void)
EXPORT_SYMBOL(tstc);
int getc(void)
-{
+
+ if (unlikely(!console_is_input_allow()))
+ return -EPERM;
+
if (!console)
return -EINVAL;
return console->getc(console);
diff --git a/common/startup.c b/common/startup.c
index 9b33a92..0a36c07 100644
--- a/common/startup.c
+++ b/common/startup.c
@@ -138,6 +138,8 @@ void __noreturn start_barebox(void)
run_command("source /env/bin/init", 0);
} else {
pr_err("/env/bin/init not found\n");
+ if (IS_ENABLED(CONFIG_CMD_LOGIN))
+ while(run_command("login -t 0", 0));
}
}
diff --git a/include/console.h b/include/console.h
index 72cf99f..e94c5ae 100644
--- a/include/console.h
+++ b/include/console.h
@@ -54,4 +54,7 @@ extern struct list_head console_list;
#define CFG_PBSIZE (CONFIG_CBSIZE+sizeof(CONFIG_PROMPT)+16)
+bool console_is_input_allow(void);
+void console_allow_input(bool val);
+
#endif
--
1.8.4.rc1
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^ permalink raw reply related
* [PATCH 4/4] defaultenv-2: add login support
From: Jean-Christophe PLAGNIOL-VILLARD @ 2013-09-15 11:30 UTC (permalink / raw)
To: barebox
In-Reply-To: <1379244654-30716-1-git-send-email-plagnioj@jcrosoft.com>
request password to login is a timeout is specified and /env/etc/passwd
present
ensure we have not console access execpt when allowed
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
---
defaultenv-2/base/bin/init | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/defaultenv-2/base/bin/init b/defaultenv-2/base/bin/init
index ca02ba6..4b132bc 100644
--- a/defaultenv-2/base/bin/init
+++ b/defaultenv-2/base/bin/init
@@ -16,14 +16,22 @@ global editcmd=sedit
[ -e /env/config-board ] && /env/config-board
/env/config
+# request password to login is a timeout is specified and /env/etc/passwd present
+[ -n ${global.login.timeout} ] && login_cmd=login
+# allow the input if not
+[ -n ${global.console.input_allow} ] && global.console.input_allow=1
+
# allow to stop the boot before execute the /env/init/*
# but without waiting
timeout -s -a -v key 0
if [ "${key}" = "q" ]; then
+ ${login_cmd}
exit
fi
+[ -n ${global.login.timeout} ] && global.console.input_allow=0
+
for i in /env/init/*; do
. $i
done
@@ -34,10 +42,15 @@ else
echo -e -n "\nHit any key to stop autoboot: "
fi
+[ -n ${global.login.timeout} ] && global.console.input_allow=1
+
timeout -a $global.autoboot_timeout -v key
autoboot="$?"
+[ -n ${global.login.timeout} ] && global.console.input_allow=0
+
if [ "${key}" = "q" ]; then
+ ${login_cmd}
exit
fi
@@ -46,9 +59,12 @@ if [ "$autoboot" = 0 ]; then
fi
if [ -e /env/menu ]; then
+ ${login_cmd}
if [ "${key}" != "m" ]; then
echo -e "\ntype exit to get to the menu"
sh
fi
/env/menu/mainmenu
fi
+
+${login_cmd}
--
1.8.4.rc1
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^ permalink raw reply related
* [PATCH 1/4] login: add globalvar timeout support
From: Jean-Christophe PLAGNIOL-VILLARD @ 2013-09-15 11:30 UTC (permalink / raw)
To: barebox
In-Reply-To: <20130915112850.GC21829@ns203013.ovh.net>
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
---
commands/login.c | 26 ++++++++++++++++++++++++++
1 file changed, 26 insertions(+)
diff --git a/commands/login.c b/commands/login.c
index fb6bb35..f5429bc 100644
--- a/commands/login.c
+++ b/commands/login.c
@@ -20,6 +20,10 @@
#include <complete.h>
#include <password.h>
#include <getopt.h>
+#include <environment.h>
+#include <globalvar.h>
+#include <magicvar.h>
+#include <init.h>
#define PASSWD_MAX_LENGTH (128 + 1)
@@ -31,6 +35,16 @@
#define LOGIN_MODE HIDE
#endif
+static void login_getenv_int(const char *name, int *i)
+{
+ const char* str = getenv(name);
+
+ if (!str)
+ return;
+
+ *i = simple_strtoul(str, NULL, 10);
+}
+
static int do_login(int argc, char *argv[])
{
unsigned char passwd[PASSWD_MAX_LENGTH];
@@ -38,6 +52,8 @@ static int do_login(int argc, char *argv[])
int timeout = 0;
char *timeout_cmd = "boot";
+ login_getenv_int("global.login.timeout", &timeout);
+
if (!is_passwd_enable()) {
puts("login: password not set\n");
return 0;
@@ -80,3 +96,13 @@ BAREBOX_CMD_START(login)
BAREBOX_CMD_HELP(cmd_login_help)
BAREBOX_CMD_COMPLETE(empty_complete)
BAREBOX_CMD_END
+
+static int login_global_init(void)
+{
+ globalvar_add_simple("login.timeout");
+
+ return 0;
+}
+late_initcall(login_global_init);
+
+BAREBOX_MAGICVAR_NAMED(global_login_timeout, global.login.timeout, "timeout to type the password");
--
1.8.4.rc1
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^ permalink raw reply related
* [PATCH 0/2 v2] defaultenv-2: add login support
From: Jean-Christophe PLAGNIOL-VILLARD @ 2013-09-15 11:28 UTC (permalink / raw)
To: barebox
HI,
this will allow to request password when try to interrupt barebox auto
boot
This will also allow to set a default password if none in the env
and if no /env/bin/init is present request a login
Jean-Christophe PLAGNIOL-VILLARD (4):
login: add globalvar timeout support
login: disable input console if password wrong
login/passwd: add default password support
defaultenv-2: add login support
commands/login.c | 32 +++++++++++++++++++++++++++++++-
commands/passwd.c | 8 ++++----
common/Kconfig | 5 +++++
common/Makefile | 18 ++++++++++++++++++
common/console.c | 6 ++++++
common/console_common.c | 45 +++++++++++++++++++++++++++++++++++++++++++++
common/console_simple.c | 9 ++++++++-
common/password.c | 94 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++-------------
common/startup.c | 2 ++
defaultenv-2/base/bin/init | 16 ++++++++++++++++
include/console.h | 3 +++
include/password.h | 22 +++++++++++++++++-----
12 files changed, 236 insertions(+), 24 deletions(-)
Best Regards,
J.
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^ permalink raw reply
* [PATCH 1/1] genenv: ignore *.orig file too
From: Jean-Christophe PLAGNIOL-VILLARD @ 2013-09-14 16:23 UTC (permalink / raw)
To: barebox
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
---
scripts/genenv | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/scripts/genenv b/scripts/genenv
index 374db6d..02af767 100755
--- a/scripts/genenv
+++ b/scripts/genenv
@@ -24,7 +24,7 @@ for i in $*; do
done
)
-find $tempdir -name '.svn' -o -name '*~' | xargs --no-run-if-empty rm -r
+find $tempdir -name '*.orig' -o -name '.svn' -o -name '*~' | xargs --no-run-if-empty rm -r
$objtree/scripts/bareboxenv -s $tempdir $target
--
1.8.4.rc1
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* [PATCH 1/2] add fix size tools
From: Jean-Christophe PLAGNIOL-VILLARD @ 2013-09-14 12:27 UTC (permalink / raw)
To: barebox
In-Reply-To: <20130914120725.GB21829@ns203013.ovh.net>
this will allow to write the size of barebox at an offset of the binary
this is needed for ARM when using relocated binary
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
---
scripts/Makefile | 1 +
scripts/fix_size.c | 81 ++++++++++++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 82 insertions(+)
create mode 100644 scripts/fix_size.c
diff --git a/scripts/Makefile b/scripts/Makefile
index 307dc3d..61f31db 100644
--- a/scripts/Makefile
+++ b/scripts/Makefile
@@ -7,6 +7,7 @@
hostprogs-$(CONFIG_KALLSYMS) += kallsyms
hostprogs-y += bin2c
hostprogs-y += mkimage
+hostprogs-y += fix_size
hostprogs-y += bareboxenv
hostprogs-$(CONFIG_ARCH_MVEBU) += kwbimage kwboot
hostprogs-$(CONFIG_ARCH_NETX) += gen_netx_image
diff --git a/scripts/fix_size.c b/scripts/fix_size.c
new file mode 100644
index 0000000..869ae7e
--- /dev/null
+++ b/scripts/fix_size.c
@@ -0,0 +1,81 @@
+#include <stdlib.h>
+#include <stdio.h>
+#include <sys/types.h>
+#include <sys/stat.h>
+#include <unistd.h>
+#include <stdint.h>
+#include <fcntl.h>
+#ifndef _BSD_SOURCE
+#define _BSD_SOURCE /* See feature_test_macros(7) */
+#endif
+#include <endian.h>
+
+int main(int argc, char**argv)
+{
+ struct stat s;
+ int c;
+ int fd;
+ uint64_t offset = 0;
+ uint32_t size = 0;
+ char *file = NULL;
+ int ret = 1;
+ int is_bigendian = 0;
+
+ while ((c = getopt (argc, argv, "hf:o:b")) != -1) {
+ switch (c) {
+ case 'f':
+ file = optarg;
+ break;
+ case 'o':
+ offset = strtoul(optarg, NULL, 16);
+ break;
+ case 'b':
+ is_bigendian = 1;
+ break;
+ }
+ }
+
+ if (!file) {
+ fprintf(stderr, "missing file\n");
+ return 1;
+ }
+
+ if (stat(file, &s)) {
+ perror("stat");
+ return 1;
+ }
+
+ fd = open(file, O_WRONLY);
+ if (fd < 0) {
+ perror("open");
+ return 1;
+ }
+
+ ret = lseek(fd, offset, SEEK_SET);
+ if (ret < 0) {
+ perror("lseek");
+ ret = 1;
+ goto err;
+ }
+
+ size = s.st_size;
+
+ if (is_bigendian)
+ size = htobe32(size);
+ else
+ size = htole32(size);
+
+ ret = write(fd, &size, 4);
+ if (ret != 4) {
+ perror("write");
+ ret = 1;
+ goto err;
+ }
+
+ ret = 0;
+err:
+
+ close(fd);
+
+ return ret;
+}
--
1.8.4.rc1
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^ permalink raw reply related
* [PATCH 2/2] ARM: PBL: fix binary size
From: Jean-Christophe PLAGNIOL-VILLARD @ 2013-09-14 12:27 UTC (permalink / raw)
To: barebox
In-Reply-To: <1379161639-27488-1-git-send-email-plagnioj@jcrosoft.com>
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
---
arch/arm/pbl/Makefile | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm/pbl/Makefile b/arch/arm/pbl/Makefile
index f4b3471..f89c56b 100644
--- a/arch/arm/pbl/Makefile
+++ b/arch/arm/pbl/Makefile
@@ -13,9 +13,17 @@ targets := zbarebox.lds zbarebox zbarebox.bin zbarebox.S \
# Make sure files are removed during clean
extra-y += piggy.gzip piggy.lz4 piggy.lzo piggy.lzma piggy.xzkern piggy.shipped zbarebox.map
+ifeq ($(CONFIG_CPU_BIG_ENDIAN),y)
+FIX_SIZE=-b
+else
+FIX_SIZE=
+endif
+
$(obj)/zbarebox.bin: $(obj)/zbarebox FORCE
$(call if_changed,objcopy)
$(call cmd,check_file_size,$(CONFIG_BAREBOX_MAX_IMAGE_SIZE))
+ $(Q)$(kecho) ' Barebox: fix size'
+ $(Q)$(objtree)/scripts/fix_size -f $(objtree)/$@ -o 0x2c $(FIX_SIZE)
$(Q)$(kecho) ' Barebox: $@ is ready'
$(obj)/zbarebox.S: $(obj)/zbarebox FORCE
--
1.8.4.rc1
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^ permalink raw reply related
* [RFC] [PATCH 0/2] fix barebox size when using a relocated pbl
From: Jean-Christophe PLAGNIOL-VILLARD @ 2013-09-14 12:07 UTC (permalink / raw)
To: barebox
Hi,
today if we use a relocatable pbl we have 0 at 0x2c on ARM
as the linker script can not calculte the size correctly
so fix it post zbarebox.bin generation
Jean-Christophe PLAGNIOL-VILLARD (2):
add fix size tools
ARM: PBL: fix binary size
arch/arm/pbl/Makefile | 8 ++++++++
scripts/Makefile | 1 +
scripts/fix_size.c | 81 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 90 insertions(+)
create mode 100644 scripts/fix_size.c
Best Regards,
J.
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^ permalink raw reply
* [PATCH v2] mci: add designware mmc controller support
From: Sascha Hauer @ 2013-09-11 10:21 UTC (permalink / raw)
To: barebox
Based on the U-Boot driver.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
changes since v1:
- propagate supported buswidths to framework
- fix buswidth setting
- user proper timeout loops
drivers/mci/Kconfig | 8 +
drivers/mci/Makefile | 1 +
drivers/mci/dw_mmc.c | 609 +++++++++++++++++++++++++++++++++++++++++
include/platform_data/dw_mmc.h | 9 +
4 files changed, 627 insertions(+)
create mode 100644 drivers/mci/dw_mmc.c
create mode 100644 include/platform_data/dw_mmc.h
diff --git a/drivers/mci/Kconfig b/drivers/mci/Kconfig
index 7aff7df..f34c119 100644
--- a/drivers/mci/Kconfig
+++ b/drivers/mci/Kconfig
@@ -34,6 +34,14 @@ config MCI_MMC_BOOT_PARTITIONS
comment "--- MCI host drivers ---"
+config MCI_DW
+ bool "Synopsys DesignWare Memory Card Interface"
+ depends on ARM
+ help
+ This selects support for the Synopsys DesignWare Mobile Storage IP
+ block, this provides host support for SD and MMC interfaces, in both
+ PIO and external DMA modes.
+
config MCI_MXS
bool "i.MX23/i.MX28"
depends on ARCH_MXS
diff --git a/drivers/mci/Makefile b/drivers/mci/Makefile
index df06a08..c13dad3 100644
--- a/drivers/mci/Makefile
+++ b/drivers/mci/Makefile
@@ -8,3 +8,4 @@ obj-$(CONFIG_MCI_OMAP_HSMMC) += omap_hsmmc.o
obj-$(CONFIG_MCI_PXA) += pxamci.o
obj-$(CONFIG_MCI_S3C) += s3c.o
obj-$(CONFIG_MCI_SPI) += mci_spi.o
+obj-$(CONFIG_MCI_DW) += dw_mmc.o
diff --git a/drivers/mci/dw_mmc.c b/drivers/mci/dw_mmc.c
new file mode 100644
index 0000000..cd2fbb5
--- /dev/null
+++ b/drivers/mci/dw_mmc.c
@@ -0,0 +1,609 @@
+/*
+ * Copyright (C) 2013 Altera Corporation <www.altera.com>
+ *
+ * (C) Copyright 2012 SAMSUNG Electronics
+ * Jaehoon Chung <jh80.chung@samsung.com>
+ * Rajeshawari Shinde <rajeshwari.s@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <driver.h>
+#include <malloc.h>
+#include <clock.h>
+#include <init.h>
+#include <mci.h>
+#include <io.h>
+#include <platform_data/dw_mmc.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <asm-generic/errno.h>
+#include <asm/mmu.h>
+
+#define DWMCI_CTRL 0x000
+#define DWMCI_PWREN 0x004
+#define DWMCI_CLKDIV 0x008
+#define DWMCI_CLKSRC 0x00C
+#define DWMCI_CLKENA 0x010
+#define DWMCI_TMOUT 0x014
+#define DWMCI_CTYPE 0x018
+#define DWMCI_BLKSIZ 0x01C
+#define DWMCI_BYTCNT 0x020
+#define DWMCI_INTMASK 0x024
+#define DWMCI_CMDARG 0x028
+#define DWMCI_CMD 0x02C
+#define DWMCI_RESP0 0x030
+#define DWMCI_RESP1 0x034
+#define DWMCI_RESP2 0x038
+#define DWMCI_RESP3 0x03C
+#define DWMCI_MINTSTS 0x040
+#define DWMCI_RINTSTS 0x044
+#define DWMCI_STATUS 0x048
+#define DWMCI_FIFOTH 0x04C
+#define DWMCI_CDETECT 0x050
+#define DWMCI_WRTPRT 0x054
+#define DWMCI_GPIO 0x058
+#define DWMCI_TCMCNT 0x05C
+#define DWMCI_TBBCNT 0x060
+#define DWMCI_DEBNCE 0x064
+#define DWMCI_USRID 0x068
+#define DWMCI_VERID 0x06C
+#define DWMCI_HCON 0x070
+#define DWMCI_UHS_REG 0x074
+#define DWMCI_BMOD 0x080
+#define DWMCI_PLDMND 0x084
+#define DWMCI_DBADDR 0x088
+#define DWMCI_IDSTS 0x08C
+#define DWMCI_IDINTEN 0x090
+#define DWMCI_DSCADDR 0x094
+#define DWMCI_BUFADDR 0x098
+#define DWMCI_DATA 0x200
+
+/* Interrupt Mask register */
+#define DWMCI_INTMSK_ALL 0xffffffff
+#define DWMCI_INTMSK_RE (1 << 1)
+#define DWMCI_INTMSK_CDONE (1 << 2)
+#define DWMCI_INTMSK_DTO (1 << 3)
+#define DWMCI_INTMSK_TXDR (1 << 4)
+#define DWMCI_INTMSK_RXDR (1 << 5)
+#define DWMCI_INTMSK_RCRC (1 << 6)
+#define DWMCI_INTMSK_DCRC (1 << 7)
+#define DWMCI_INTMSK_RTO (1 << 8)
+#define DWMCI_INTMSK_DRTO (1 << 9)
+#define DWMCI_INTMSK_HTO (1 << 10)
+#define DWMCI_INTMSK_FRUN (1 << 11)
+#define DWMCI_INTMSK_HLE (1 << 12)
+#define DWMCI_INTMSK_SBE (1 << 13)
+#define DWMCI_INTMSK_ACD (1 << 14)
+#define DWMCI_INTMSK_EBE (1 << 15)
+
+/* Raw interrupt Register */
+#define DWMCI_DATA_ERR (DWMCI_INTMSK_EBE | DWMCI_INTMSK_SBE | DWMCI_INTMSK_HLE |\
+ DWMCI_INTMSK_FRUN | DWMCI_INTMSK_DCRC)
+#define DWMCI_DATA_TOUT (DWMCI_INTMSK_HTO | DWMCI_INTMSK_DRTO)
+
+/* CTRL register */
+#define DWMCI_CTRL_RESET (1 << 0)
+#define DWMCI_CTRL_FIFO_RESET (1 << 1)
+#define DWMCI_CTRL_DMA_RESET (1 << 2)
+#define DWMCI_DMA_EN (1 << 5)
+#define DWMCI_CTRL_SEND_AS_CCSD (1 << 10)
+#define DWMCI_IDMAC_EN (1 << 25)
+#define DWMCI_RESET_ALL (DWMCI_CTRL_RESET | DWMCI_CTRL_FIFO_RESET |\
+ DWMCI_CTRL_DMA_RESET)
+
+/* CMD register */
+#define DWMCI_CMD_RESP_EXP (1 << 6)
+#define DWMCI_CMD_RESP_LENGTH (1 << 7)
+#define DWMCI_CMD_CHECK_CRC (1 << 8)
+#define DWMCI_CMD_DATA_EXP (1 << 9)
+#define DWMCI_CMD_RW (1 << 10)
+#define DWMCI_CMD_SEND_STOP (1 << 12)
+#define DWMCI_CMD_ABORT_STOP (1 << 14)
+#define DWMCI_CMD_PRV_DAT_WAIT (1 << 13)
+#define DWMCI_CMD_UPD_CLK (1 << 21)
+#define DWMCI_CMD_USE_HOLD_REG (1 << 29)
+#define DWMCI_CMD_START (1 << 31)
+
+/* CLKENA register */
+#define DWMCI_CLKEN_ENABLE (1 << 0)
+#define DWMCI_CLKEN_LOW_PWR (1 << 16)
+
+/* Card-type register */
+#define DWMCI_CTYPE_1BIT 0
+#define DWMCI_CTYPE_4BIT (1 << 0)
+#define DWMCI_CTYPE_8BIT (1 << 16)
+
+/* Status Register */
+#define DWMCI_STATUS_BUSY (1 << 9)
+
+/* FIFOTH Register */
+#define DWMCI_FIFOTH_MSIZE(x) ((x) << 28)
+#define DWMCI_FIFOTH_RX_WMARK(x) ((x) << 16)
+#define DWMCI_FIFOTH_TX_WMARK(x) (x)
+#define DWMCI_FIFOTH_FIFO_DEPTH(x) ((((x) >> 16) & 0x3ff) + 1)
+
+#define DWMCI_IDMAC_OWN (1 << 31)
+#define DWMCI_IDMAC_CH (1 << 4)
+#define DWMCI_IDMAC_FS (1 << 3)
+#define DWMCI_IDMAC_LD (1 << 2)
+
+/* Bus Mode Register */
+#define DWMCI_BMOD_IDMAC_RESET (1 << 0)
+#define DWMCI_BMOD_IDMAC_FB (1 << 1)
+#define DWMCI_BMOD_IDMAC_EN (1 << 7)
+
+struct dwmci_host {
+ struct mci_host mci;
+ struct device_d *dev;
+ struct clk *clk_biu, *clk_ciu;
+ void *ioaddr;
+ unsigned int fifo_size_bytes;
+
+ struct dwmci_idmac *idmac;
+ unsigned long clkrate;
+ int ciu_div;
+};
+
+struct dwmci_idmac {
+ uint32_t flags;
+ uint32_t cnt;
+ uint32_t addr;
+ uint32_t next_addr;
+};
+
+static inline void dwmci_writel(struct dwmci_host *host, int reg, uint32_t val)
+{
+ writel(val, host->ioaddr + reg);
+}
+
+static inline uint32_t dwmci_readl(struct dwmci_host *host, int reg)
+{
+ return readl(host->ioaddr + reg);
+}
+
+#define DW_MMC_NUM_IDMACS (PAGE_SIZE / sizeof(struct dwmci_idmac))
+
+static inline struct dwmci_host *to_dwmci_host(struct mci_host *mci)
+{
+ return container_of(mci, struct dwmci_host, mci);
+}
+
+static int dwmci_wait_reset(struct dwmci_host *host, uint32_t value)
+{
+ uint64_t start;
+ uint32_t ctrl;
+
+ start = get_time_ns();
+
+ dwmci_writel(host, DWMCI_CTRL, value);
+
+ while (!is_timeout(start, SECOND)) {
+ ctrl = dwmci_readl(host, DWMCI_CTRL);
+ if (!(ctrl & DWMCI_RESET_ALL))
+ return 0;
+ }
+
+ return -EIO;
+}
+
+static int dwmci_prepare_data(struct dwmci_host *host,
+ struct mci_data *data)
+{
+ unsigned long ctrl;
+ unsigned int i = 0, flags, cnt, blk_cnt;
+ unsigned long data_start, start_addr;
+ struct dwmci_idmac *desc = host->idmac;
+
+ blk_cnt = data->blocks;
+
+ if (blk_cnt > DW_MMC_NUM_IDMACS)
+ return -EINVAL;
+
+ dwmci_wait_reset(host, DWMCI_CTRL_FIFO_RESET);
+
+ data_start = (uint32_t)desc;
+ dwmci_writel(host, DWMCI_DBADDR, (uint32_t)desc);
+
+ if (data->flags & MMC_DATA_READ)
+ start_addr = (uint32_t)data->dest;
+ else
+ start_addr = (uint32_t)data->src;
+
+ do {
+ flags = DWMCI_IDMAC_OWN | DWMCI_IDMAC_CH;
+ flags |= (i == 0) ? DWMCI_IDMAC_FS : 0;
+
+ if (blk_cnt <= 8) {
+ flags |= DWMCI_IDMAC_LD;
+ cnt = data->blocksize * blk_cnt;
+ } else {
+ cnt = data->blocksize * 8;
+ }
+
+ desc->flags = flags;
+ desc->cnt = cnt;
+ desc->addr = start_addr + (i * PAGE_SIZE);
+ desc->next_addr = (uint32_t)(desc + 1);
+
+ dev_dbg(host->dev, "desc@ 0x%p 0x%08x 0x%08x 0x%08x 0x%08x\n",
+ desc, flags, cnt, desc->addr, desc->next_addr);
+ if (blk_cnt < 8)
+ break;
+
+ blk_cnt -= 8;
+ desc++;
+ i++;
+ } while (1);
+
+ ctrl = dwmci_readl(host, DWMCI_CTRL);
+ ctrl |= DWMCI_IDMAC_EN | DWMCI_DMA_EN;
+ dwmci_writel(host, DWMCI_CTRL, ctrl);
+
+ ctrl = dwmci_readl(host, DWMCI_BMOD);
+ ctrl |= DWMCI_BMOD_IDMAC_FB | DWMCI_BMOD_IDMAC_EN;
+ dwmci_writel(host, DWMCI_BMOD, ctrl);
+
+ dwmci_writel(host, DWMCI_BLKSIZ, data->blocksize);
+ dwmci_writel(host, DWMCI_BYTCNT, data->blocksize * data->blocks);
+
+ return 0;
+}
+
+static int dwmci_set_transfer_mode(struct dwmci_host *host,
+ struct mci_data *data)
+{
+ unsigned long mode;
+
+ mode = DWMCI_CMD_DATA_EXP;
+ if (data->flags & MMC_DATA_WRITE)
+ mode |= DWMCI_CMD_RW;
+
+ return mode;
+}
+
+static int
+dwmci_cmd(struct mci_host *mci, struct mci_cmd *cmd, struct mci_data *data)
+{
+ struct dwmci_host *host = to_dwmci_host(mci);
+ int flags = 0;
+ uint32_t mask, ctrl;
+ uint64_t start;
+ int ret;
+ unsigned int num_bytes = 0;
+ const void *writebuf = NULL;
+
+ start = get_time_ns();
+ while (1) {
+ if (!(dwmci_readl(host, DWMCI_STATUS) & DWMCI_STATUS_BUSY))
+ break;
+
+ if (is_timeout(start, 100 * MSECOND)) {
+ dev_dbg(host->dev, "Timeout on data busy\n");
+ return -ETIMEDOUT;
+ }
+ }
+
+ dwmci_writel(host, DWMCI_RINTSTS, DWMCI_INTMSK_ALL);
+
+ if (data) {
+ num_bytes = data->blocks * data->blocksize;
+
+ if (data->flags & MMC_DATA_WRITE) {
+ dma_flush_range((unsigned long)data->src,
+ (unsigned long)(data->src + data->blocks * 512));
+
+ writebuf = data->src;
+ }
+
+ ret = dwmci_prepare_data(host, data);
+ if (ret)
+ return ret;
+ }
+
+ dwmci_writel(host, DWMCI_CMDARG, cmd->cmdarg);
+
+ if (data)
+ flags = dwmci_set_transfer_mode(host, data);
+
+ if ((cmd->resp_type & MMC_RSP_136) && (cmd->resp_type & MMC_RSP_BUSY))
+ return -EINVAL;
+
+ if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
+ flags |= DWMCI_CMD_ABORT_STOP;
+ else
+ flags |= DWMCI_CMD_PRV_DAT_WAIT;
+
+ if (cmd->resp_type & MMC_RSP_PRESENT) {
+ flags |= DWMCI_CMD_RESP_EXP;
+ if (cmd->resp_type & MMC_RSP_136)
+ flags |= DWMCI_CMD_RESP_LENGTH;
+ }
+
+ if (cmd->resp_type & MMC_RSP_CRC)
+ flags |= DWMCI_CMD_CHECK_CRC;
+
+ flags |= (cmd->cmdidx | DWMCI_CMD_START | DWMCI_CMD_USE_HOLD_REG);
+
+ dev_dbg(host->dev, "Sending CMD%d\n", cmd->cmdidx);
+
+ dwmci_writel(host, DWMCI_CMD, flags);
+
+ start = get_time_ns();
+ while (1) {
+ mask = dwmci_readl(host, DWMCI_RINTSTS);
+ if (mask & DWMCI_INTMSK_CDONE) {
+ if (!data)
+ dwmci_writel(host, DWMCI_RINTSTS, mask);
+ break;
+ }
+ if (is_timeout(start, 100 * MSECOND))
+ return -ETIMEDOUT;
+ }
+
+ if (mask & DWMCI_INTMSK_RTO) {
+ dev_dbg(host->dev, "Response Timeout..\n");
+ return -ETIMEDOUT;
+ } else if (mask & DWMCI_INTMSK_RE) {
+ dev_dbg(host->dev, "Response Error..\n");
+ return -EIO;
+ }
+
+ if (cmd->resp_type & MMC_RSP_PRESENT) {
+ if (cmd->resp_type & MMC_RSP_136) {
+ cmd->response[0] = dwmci_readl(host, DWMCI_RESP3);
+ cmd->response[1] = dwmci_readl(host, DWMCI_RESP2);
+ cmd->response[2] = dwmci_readl(host, DWMCI_RESP1);
+ cmd->response[3] = dwmci_readl(host, DWMCI_RESP0);
+ } else {
+ cmd->response[0] = dwmci_readl(host, DWMCI_RESP0);
+ }
+ }
+
+ if (data) {
+ start = get_time_ns();
+ do {
+ mask = dwmci_readl(host, DWMCI_RINTSTS);
+ if (mask & (DWMCI_DATA_ERR | DWMCI_DATA_TOUT)) {
+ dev_dbg(host->dev, "DATA ERROR!\n");
+ return -EIO;
+ }
+ if (is_timeout(start, SECOND))
+ return -ETIMEDOUT;
+ } while (!(mask & DWMCI_INTMSK_DTO));
+
+ dwmci_writel(host, DWMCI_RINTSTS, mask);
+
+ ctrl = dwmci_readl(host, DWMCI_CTRL);
+ ctrl &= ~(DWMCI_DMA_EN);
+ dwmci_writel(host, DWMCI_CTRL, ctrl);
+
+ if (data->flags & MMC_DATA_READ) {
+ dma_inv_range((unsigned long)data->dest,
+ (unsigned long)(data->dest + data->blocks * 512));
+ }
+ }
+
+ udelay(100);
+
+ return 0;
+}
+
+static int dwmci_send_cmd(struct dwmci_host *host, u32 cmd, u32 arg)
+{
+ uint64_t start = get_time_ns();
+ uint32_t status;
+
+ dwmci_writel(host, DWMCI_CMDARG, arg);
+
+ dwmci_writel(host, DWMCI_CMD, cmd | DWMCI_CMD_START);
+
+ while (1) {
+ status = dwmci_readl(host, DWMCI_CMD);
+ if (!(status & DWMCI_CMD_START))
+ return 0;
+
+ if (is_timeout(start, 100 * MSECOND)) {
+ dev_err(host->dev, "TIMEOUT error!!\n");
+ return -ETIMEDOUT;
+ }
+ }
+}
+
+static int dwmci_setup_bus(struct dwmci_host *host, uint32_t freq)
+{
+ uint32_t div;
+ unsigned long sclk;
+
+ sclk = host->clkrate / host->ciu_div;
+
+ div = DIV_ROUND_UP(sclk, freq);
+ if (div > 510)
+ div = 510;
+
+ div >>= 1;
+
+ dwmci_writel(host, DWMCI_CLKENA, 0);
+ dwmci_writel(host, DWMCI_CLKSRC, 0);
+
+ dwmci_writel(host, DWMCI_CLKDIV, div);
+
+ dwmci_send_cmd(host, DWMCI_CMD_PRV_DAT_WAIT | DWMCI_CMD_UPD_CLK, 0);
+
+ dwmci_writel(host, DWMCI_CLKENA, DWMCI_CLKEN_ENABLE);
+
+ dwmci_send_cmd(host, DWMCI_CMD_PRV_DAT_WAIT | DWMCI_CMD_UPD_CLK, 0);
+
+ return 0;
+}
+
+static void dwmci_set_ios(struct mci_host *mci, struct mci_ios *ios)
+{
+ struct dwmci_host *host = to_dwmci_host(mci);
+ uint32_t ctype;
+
+ dev_dbg(host->dev, "Buswidth = %d, clock: %d\n", ios->bus_width, ios->clock);
+
+ if (ios->clock)
+ dwmci_setup_bus(host, ios->clock);
+
+ switch (ios->bus_width) {
+ case MMC_BUS_WIDTH_8:
+ ctype = DWMCI_CTYPE_8BIT;
+ break;
+ case MMC_BUS_WIDTH_4:
+ ctype = DWMCI_CTYPE_4BIT;
+ break;
+ default:
+ ctype = DWMCI_CTYPE_1BIT;
+ break;
+ }
+
+ dwmci_writel(host, DWMCI_CTYPE, ctype);
+}
+
+static int dwmci_card_present(struct mci_host *mci)
+{
+ return 1;
+}
+
+static int dwmci_init(struct mci_host *mci, struct device_d *dev)
+{
+ struct dwmci_host *host = to_dwmci_host(mci);
+ uint32_t fifo_size, fifoth_val;
+
+ dwmci_writel(host, DWMCI_PWREN, 1);
+
+ if (dwmci_wait_reset(host, DWMCI_RESET_ALL)) {
+ dev_err(host->dev, "reset failed\n");
+ return -EIO;
+ }
+
+ dwmci_writel(host, DWMCI_RINTSTS, 0xffffffff);
+ dwmci_writel(host, DWMCI_INTMASK, 0);
+
+ dwmci_writel(host, DWMCI_TMOUT, 0xffffffff);
+
+ dwmci_writel(host, DWMCI_IDINTEN, 0);
+ dwmci_writel(host, DWMCI_BMOD, 1);
+
+ fifo_size = dwmci_readl(host, DWMCI_FIFOTH);
+
+ /*
+ * Use reset default of the rx_wmark field to determine the
+ * fifo depth.
+ */
+ fifo_size = DWMCI_FIFOTH_FIFO_DEPTH(fifo_size);
+ host->fifo_size_bytes = fifo_size * 4;
+
+ fifoth_val = DWMCI_FIFOTH_MSIZE(0x2) |
+ DWMCI_FIFOTH_RX_WMARK(fifo_size / 2 - 1) |
+ DWMCI_FIFOTH_TX_WMARK(fifo_size / 2);
+
+ dwmci_writel(host, DWMCI_FIFOTH, fifoth_val);
+
+ dwmci_writel(host, DWMCI_CLKENA, 0);
+ dwmci_writel(host, DWMCI_CLKSRC, 0);
+
+ return 0;
+}
+
+static int dw_mmc_detect(struct device_d *dev)
+{
+ struct dwmci_host *host = dev->priv;
+
+ return mci_detect_card(&host->mci);
+}
+
+static int dw_mmc_probe(struct device_d *dev)
+{
+ struct dwmci_host *host;
+ struct mci_host *mci;
+ struct dw_mmc_platform_data *pdata = dev->platform_data;
+
+ host = xzalloc(sizeof(*host));
+ mci = &host->mci;
+
+ host->clk_biu = clk_get(dev, "biu");
+ if (IS_ERR(host->clk_biu))
+ return PTR_ERR(host->clk_biu);
+
+ host->clk_ciu = clk_get(dev, "ciu");
+ if (IS_ERR(host->clk_ciu))
+ return PTR_ERR(host->clk_ciu);
+
+ clk_enable(host->clk_biu);
+ clk_enable(host->clk_ciu);
+
+ host->dev = dev;
+ host->ioaddr = dev_request_mem_region(dev, 0);
+ if (!host->ioaddr)
+ return -EBUSY;
+
+ if (pdata) {
+ mci->devname = pdata->devname;
+ host->ciu_div = pdata->ciu_div;
+ } else if (dev->device_node) {
+ const char *alias = of_alias_get(dev->device_node);
+ if (alias)
+ mci->devname = xstrdup(alias);
+ of_property_read_u32(dev->device_node, "dw-mshc-ciu-div",
+ &host->ciu_div);
+ }
+
+ /* divider is 0 based in pdata and 1 based in our private struct */
+ host->ciu_div++;
+
+ host->idmac = dma_alloc_coherent(sizeof(*host->idmac) * DW_MMC_NUM_IDMACS);
+
+ host->mci.send_cmd = dwmci_cmd;
+ host->mci.set_ios = dwmci_set_ios;
+ host->mci.init = dwmci_init;
+ host->mci.card_present = dwmci_card_present;
+ host->mci.hw_dev = dev;
+ host->mci.voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
+ host->mci.host_caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA;
+
+ dev->detect = dw_mmc_detect;
+
+ host->clkrate = clk_get_rate(host->clk_ciu);
+ host->mci.f_min = host->clkrate / 510 / host->ciu_div;
+ if (host->mci.f_min < 200000)
+ host->mci.f_min = 200000;
+ host->mci.f_max = host->clkrate / host->ciu_div;
+
+ mci_of_parse(&host->mci);
+
+ dev->priv = host;
+
+ return mci_register(&host->mci);
+}
+
+static __maybe_unused struct of_device_id dw_mmc_compatible[] = {
+ {
+ .compatible = "altr,socfpga-dw-mshc",
+ }, {
+ /* sentinel */
+ }
+};
+
+static struct driver_d dw_mmc_driver = {
+ .name = "dw_mmc",
+ .probe = dw_mmc_probe,
+ .of_compatible = DRV_OF_COMPAT(dw_mmc_compatible),
+};
+device_platform_driver(dw_mmc_driver);
diff --git a/include/platform_data/dw_mmc.h b/include/platform_data/dw_mmc.h
new file mode 100644
index 0000000..48faa76
--- /dev/null
+++ b/include/platform_data/dw_mmc.h
@@ -0,0 +1,9 @@
+#ifndef __INCLUDE_PLATFORM_DATA_DW_MMC_H
+#define __INCLUDE_PLATFORM_DATA_DW_MMC_H
+
+struct dw_mmc_platform_data {
+ char *devname;
+ int ciu_div;
+};
+
+#endif /* __INCLUDE_PLATFORM_DATA_DW_MMC_H */
--
1.8.4.rc3
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^ permalink raw reply related
* Re: imx-usb-image write to usb error
From: Sascha Hauer @ 2013-09-11 7:00 UTC (permalink / raw)
To: Jason Cooper; +Cc: barebox
In-Reply-To: <20130909174117.GA12927@titan.lakedaemon.net>
On Mon, Sep 09, 2013 at 01:41:17PM -0400, Jason Cooper wrote:
> On Thu, Sep 05, 2013 at 08:46:39AM +0200, Sascha Hauer wrote:
> > Hi Jason,
> >
> > On Wed, Sep 04, 2013 at 09:04:36PM -0400, Jason Cooper wrote:
> > > All,
> > >
> > > This is the first I've messed with i.MX, so I'm a little lost. :)
> > >
> > > I'm putting together a patch to add support for the SanDisk Connect
> > > Wireless Media Drive [1], code dump from SanDisk is here [2]. It turns
> > > out when you unplug the battery, it'll show up as the Freescale hid.
> > >
> > > Here's what I get:
> > >
> > > $ ./scripts/imx/imx-image -c \
> > > arch/arm/boards/sandisk-connect-wmd/flash-header-lpddr1.imxcfg -f \
> > > barebox.bin -o barebox.imx
> > > $ sudo ./scripts/imx/imx-usb-loader -vvvvv ./barebox.imx
> > > found i.MX50 USB device [15a2:0052]
> >
> > I never tested this on an i.MX50 due to lack of hardware. Have a look
> > at scripts/imx/imx-usb-loader.c at imx_ids. i.MX50 is very similar to
> > i.MX51. The i.MX51 has:
> >
> > {
> > .vid = 0x15a2,
> > .pid = 0x0041,
> > .name = "i.MX51",
> > .header_type = HDR_MX51,
> > .mode = MODE_BULK,
> > .max_transfer = 64,
> > },
> >
> > The header_type, mode and max_transfer fields are missing for i.MX50. I
> > assume that's the problem.
>
> Well, it looks like it works, but I'm unable to get a barebox prompt on
> the tty. (patches to come once I get a prompt). So I decided to try
> tackling the problem from the other end for a bit. Namely booting a
> mainline kernel from the installed u-boot.
>
> Something is confusing me though. The part number on the chip is
> MCIMX502CVK8B. Which, iiuc, is an imx51. The provided kernel spits out
> this:
>
> [ 0.000000] MXC_Early serial console at MMIO 0x53fbc000 (options '115200')
>
> However, the only imx SoCs using that address range are imx53 and imx25,
> according to arch/arm/boot/dts/ in Linux, at least.
>
> In addition, the docs for the imx50 clearly state that it uses DCD v2
> (version = 0x40) [1] (Table 6-27, DCD Header), but the code in barebox's
> imx-image.c says imx51 uses DCD v1...
The i.MX53 is not much more than a moderately improved i.MX51. The i.MX50
is somewhere in between. Maybe it already uses the v2 header format.
Have you tried copying the values from the i.MX53?
>
> Anyone with more experience with Freescale SoCs care to fill in the
> blanks? The first hint I'm on the wrong path is that I feel like I need
> to write a whole dtsi file from scratch. :-/
The i.MX51 and i.MX53 have a very similar memory map. Only the AIPS1/2
base addresses are different to allow for bigger SDRAM on the i.MX53.
The i.MX50 memory map seems to be a subset of the i.MX53.
What I'm afraid is really different between i.MX50 and i.MX53 is the
clock controller.
Sascha
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