From: Dave Thaler <dthaler1968@googlemail.com>
To: bpf@vger.kernel.org
Cc: bpf@ietf.org, Dave Thaler <dthaler1968@gmail.com>
Subject: [PATCH bpf-next] bpf, docs: Clarify that MOVSX is only for BPF_X not BPF_K
Date: Thu, 18 Jan 2024 15:29:54 -0800 [thread overview]
Message-ID: <20240118232954.27206-1-dthaler1968@gmail.com> (raw)
Per discussion on the mailing list at
https://mailarchive.ietf.org/arch/msg/bpf/uQiqhURdtxV_ZQOTgjCdm-seh74/
the MOVSX operation is only defined to support register extension.
The document didn't previously state this and incorrectly implied
that one could use an immediate value.
Signed-off-by: Dave Thaler <dthaler1968@gmail.com>
---
Documentation/bpf/standardization/instruction-set.rst | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/Documentation/bpf/standardization/instruction-set.rst b/Documentation/bpf/standardization/instruction-set.rst
index eb0f234a8..d17a96c62 100644
--- a/Documentation/bpf/standardization/instruction-set.rst
+++ b/Documentation/bpf/standardization/instruction-set.rst
@@ -317,7 +317,8 @@ The ``BPF_MOVSX`` instruction does a move operation with sign extension.
``BPF_ALU | BPF_MOVSX`` :term:`sign extends<Sign Extend>` 8-bit and 16-bit operands into 32
bit operands, and zeroes the remaining upper 32 bits.
``BPF_ALU64 | BPF_MOVSX`` :term:`sign extends<Sign Extend>` 8-bit, 16-bit, and 32-bit
-operands into 64 bit operands.
+operands into 64 bit operands. Unlike other arithmetic instructions,
+``BPF_MOVSX`` is only defined for register source operands (``BPF_X``).
Shift operations use a mask of 0x3F (63) for 64-bit operations and 0x1F (31)
for 32-bit operations.
--
2.40.1
WARNING: multiple messages have this Message-ID (diff)
From: Dave Thaler <dthaler1968=40googlemail.com@dmarc.ietf.org>
To: bpf@vger.kernel.org
Cc: bpf@ietf.org, Dave Thaler <dthaler1968@gmail.com>
Subject: [Bpf] [PATCH bpf-next] bpf, docs: Clarify that MOVSX is only for BPF_X not BPF_K
Date: Thu, 18 Jan 2024 15:29:54 -0800 [thread overview]
Message-ID: <20240118232954.27206-1-dthaler1968@gmail.com> (raw)
Message-ID: <20240118232954.YFfYglPvtzSqKJONpBKEIg_CK7zDxQz2Ce6wSrkELrM@z> (raw)
Per discussion on the mailing list at
https://mailarchive.ietf.org/arch/msg/bpf/uQiqhURdtxV_ZQOTgjCdm-seh74/
the MOVSX operation is only defined to support register extension.
The document didn't previously state this and incorrectly implied
that one could use an immediate value.
Signed-off-by: Dave Thaler <dthaler1968@gmail.com>
---
Documentation/bpf/standardization/instruction-set.rst | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/Documentation/bpf/standardization/instruction-set.rst b/Documentation/bpf/standardization/instruction-set.rst
index eb0f234a8..d17a96c62 100644
--- a/Documentation/bpf/standardization/instruction-set.rst
+++ b/Documentation/bpf/standardization/instruction-set.rst
@@ -317,7 +317,8 @@ The ``BPF_MOVSX`` instruction does a move operation with sign extension.
``BPF_ALU | BPF_MOVSX`` :term:`sign extends<Sign Extend>` 8-bit and 16-bit operands into 32
bit operands, and zeroes the remaining upper 32 bits.
``BPF_ALU64 | BPF_MOVSX`` :term:`sign extends<Sign Extend>` 8-bit, 16-bit, and 32-bit
-operands into 64 bit operands.
+operands into 64 bit operands. Unlike other arithmetic instructions,
+``BPF_MOVSX`` is only defined for register source operands (``BPF_X``).
Shift operations use a mask of 0x3F (63) for 64-bit operations and 0x1F (31)
for 32-bit operations.
--
2.40.1
--
Bpf mailing list
Bpf@ietf.org
https://www.ietf.org/mailman/listinfo/bpf
next reply other threads:[~2024-01-18 23:30 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-01-18 23:29 Dave Thaler [this message]
2024-01-18 23:29 ` [Bpf] [PATCH bpf-next] bpf, docs: Clarify that MOVSX is only for BPF_X not BPF_K Dave Thaler
2024-01-18 23:45 ` David Vernet
2024-01-18 23:45 ` David Vernet
2024-01-18 23:53 ` Yonghong Song
2024-01-18 23:53 ` Yonghong Song
2024-01-23 23:40 ` patchwork-bot+netdevbpf
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