[Buildroot] [PATCH v3 1/6] target: add symbols for i386/x86_64 cpu features

Buildroot Archive on lore.kernel.org
 help / color / mirror / Atom feed

From: Samuel Martin <s.martin49@gmail.com>
To: buildroot@busybox.net
Subject: [Buildroot] [PATCH v3 1/6] target: add symbols for i386/x86_64 cpu features
Date: Sun, 10 Jun 2012 13:46:48 +0200	[thread overview]
Message-ID: <1339328813-6269-4-git-send-email-s.martin49@gmail.com> (raw)
In-Reply-To: <1339328813-6269-1-git-send-email-s.martin49@gmail.com>

Selecting the target architecture variant automatically selects the
appropriated set of features.

Signed-off-by: Samuel Martin <s.martin49@gmail.com>

diff --git a/target/Config.in.arch b/target/Config.in.arch
index 25ff750..49c01e5 100644
--- a/target/Config.in.arch
+++ b/target/Config.in.arch
@@ -242,7 +242,7 @@ choice
 	default BR2_mips_1 if BR2_mipsel
 	help
 	  Specific CPU variant to use
-	
+
 	  64bit cabable: 3, 4, 64, 64r2
 	  non-64bit capable: 1, 2, 32, 32r2
 
@@ -325,6 +325,31 @@ endchoice
 # gcc builds libstdc++ differently depending on the
 # host tuplet given to it, so let people choose
 #
+
+# i386/x86_64 cpu features
+config BR2_X86_CPU_HAS_MMX
+	bool
+config BR2_X86_CPU_HAS_SSE
+	bool
+config BR2_X86_CPU_HAS_SSE2
+	bool
+config BR2_X86_CPU_HAS_SSE3
+	bool
+config BR2_X86_CPU_HAS_SSSE3
+	bool
+config BR2_X86_CPU_HAS_SSE41
+	bool
+config BR2_X86_CPU_HAS_SSE42
+	bool
+config BR2_X86_CPU_HAS_SSE4
+	bool
+config BR2_X86_CPU_HAS_SSE4A
+	bool
+config BR2_X86_CPU_HAS_3DNOW
+	bool
+config BR2_X86_CPU_HAS_ABM
+	bool
+
 choice
 	prompt "Target Architecture Variant"
 	depends on BR2_i386
@@ -344,46 +369,106 @@ config BR2_x86_pentiumpro
 	bool "pentium pro"
 config BR2_x86_pentium_mmx
 	bool "pentium MMX"
+	select BR2_X86_CPU_HAS_MMX
 config BR2_x86_pentium_m
 	bool "pentium mobile"
 config BR2_x86_pentium2
 	bool "pentium2"
+	select BR2_X86_CPU_HAS_MMX
 config BR2_x86_pentium3
 	bool "pentium3"
+	select BR2_X86_CPU_HAS_MMX
+	select BR2_X86_CPU_HAS_SSE
 config BR2_x86_pentium4
 	bool "pentium4"
+	select BR2_X86_CPU_HAS_MMX
+	select BR2_X86_CPU_HAS_SSE
+	select BR2_X86_CPU_HAS_SSE2
 config BR2_x86_prescott
 	bool "prescott"
+	select BR2_X86_CPU_HAS_MMX
+	select BR2_X86_CPU_HAS_SSE
+	select BR2_X86_CPU_HAS_SSE2
+	select BR2_X86_CPU_HAS_SSE3
 config BR2_x86_nocona
 	bool "nocona"
+	select BR2_X86_CPU_HAS_MMX
+	select BR2_X86_CPU_HAS_SSE
+	select BR2_X86_CPU_HAS_SSE2
+	select BR2_X86_CPU_HAS_SSE3
 config BR2_x86_core2
 	bool "core2"
+	select BR2_X86_CPU_HAS_MMX
+	select BR2_X86_CPU_HAS_SSE
+	select BR2_X86_CPU_HAS_SSE2
+	select BR2_X86_CPU_HAS_SSE3
+	select BR2_X86_CPU_HAS_SSSE3
 config BR2_x86_atom
 	bool "atom"
+	select BR2_X86_CPU_HAS_MMX
+	select BR2_X86_CPU_HAS_SSE
+	select BR2_X86_CPU_HAS_SSE2
+	select BR2_X86_CPU_HAS_SSE3
+	select BR2_X86_CPU_HAS_SSSE3
 config BR2_x86_k6
 	bool "k6"
+	select BR2_X86_CPU_HAS_MMX
 config BR2_x86_k6_2
 	bool "k6-2"
+	select BR2_X86_CPU_HAS_MMX
+	select BR2_X86_CPU_HAS_3DNOW
 config BR2_x86_athlon
 	bool "athlon"
+	select BR2_X86_CPU_HAS_MMX
+	select BR2_X86_CPU_HAS_3DNOW
 config BR2_x86_athlon_4
 	bool "athlon-4"
+	select BR2_X86_CPU_HAS_MMX
+	select BR2_X86_CPU_HAS_3DNOW
+	select BR2_X86_CPU_HAS_SSE
 config BR2_x86_opteron
 	bool "opteron"
+	select BR2_X86_CPU_HAS_MMX
+	select BR2_X86_CPU_HAS_3DNOW
+	select BR2_X86_CPU_HAS_SSE
+	select BR2_X86_CPU_HAS_SSE2
 config BR2_x86_opteron_sse3
 	bool "opteron w/ SSE3"
+	select BR2_X86_CPU_HAS_MMX
+	select BR2_X86_CPU_HAS_3DNOW
+	select BR2_X86_CPU_HAS_SSE
+	select BR2_X86_CPU_HAS_SSE2
+	select BR2_X86_CPU_HAS_SSE3
 config BR2_x86_barcelona
 	bool "barcelona"
+	select BR2_X86_CPU_HAS_MMX
+	select BR2_X86_CPU_HAS_3DNOW
+	select BR2_X86_CPU_HAS_SSE
+	select BR2_X86_CPU_HAS_SSE2
+	select BR2_X86_CPU_HAS_SSE3
+	select BR2_X86_CPU_HAS_SSE4A
+	select BR2_X86_CPU_HAS_ABM
 config BR2_x86_geode
 	bool "geode"
+	# Don't include MMX support because there several variant of geode
+	# processor, some with MMX support, some without.
+	# See: http://en.wikipedia.org/wiki/Geode_%28processor%29
+	select BR2_X86_CPU_HAS_3DNOW
 config BR2_x86_c3
 	bool "Via/Cyrix C3 (Samuel/Ezra cores)"
+	select BR2_X86_CPU_HAS_MMX
+	select BR2_X86_CPU_HAS_3DNOW
 config BR2_x86_c32
 	bool "Via C3-2 (Nehemiah cores)"
+	select BR2_X86_CPU_HAS_MMX
+	select BR2_X86_CPU_HAS_SSE
 config BR2_x86_winchip_c6
 	bool "IDT Winchip C6"
+	select BR2_X86_CPU_HAS_MMX
 config BR2_x86_winchip2
 	bool "IDT Winchip 2"
+	select BR2_X86_CPU_HAS_MMX
+	select BR2_X86_CPU_HAS_3DNOW
 endchoice
 
 choice
@@ -397,16 +482,46 @@ config BR2_x86_64_generic
 	bool "generic"
 config BR2_x86_64_barcelona
 	bool "barcelona"
+	select BR2_X86_CPU_HAS_MMX
+	select BR2_X86_CPU_HAS_3DNOW
+	select BR2_X86_CPU_HAS_SSE
+	select BR2_X86_CPU_HAS_SSE2
+	select BR2_X86_CPU_HAS_SSE3
+	select BR2_X86_CPU_HAS_SSE4A
+	select BR2_X86_CPU_HAS_ABM
 config BR2_x86_64_opteron_sse3
 	bool "opteron w/ sse3"
+	select BR2_X86_CPU_HAS_MMX
+	select BR2_X86_CPU_HAS_3DNOW
+	select BR2_X86_CPU_HAS_SSE
+	select BR2_X86_CPU_HAS_SSE2
+	select BR2_X86_CPU_HAS_SSE3
 config BR2_x86_64_opteron
 	bool "opteron"
+	select BR2_X86_CPU_HAS_MMX
+	select BR2_X86_CPU_HAS_3DNOW
+	select BR2_X86_CPU_HAS_SSE
+	select BR2_X86_CPU_HAS_SSE2
 config BR2_x86_64_nocona
 	bool "nocona"
+	select BR2_X86_CPU_HAS_MMX
+	select BR2_X86_CPU_HAS_SSE
+	select BR2_X86_CPU_HAS_SSE2
+	select BR2_X86_CPU_HAS_SSE3
 config BR2_x86_64_core2
 	bool "core2"
+	select BR2_X86_CPU_HAS_MMX
+	select BR2_X86_CPU_HAS_SSE
+	select BR2_X86_CPU_HAS_SSE2
+	select BR2_X86_CPU_HAS_SSE3
+	select BR2_X86_CPU_HAS_SSSE3
 config BR2_x86_64_atom
 	bool "atom"
+	select BR2_X86_CPU_HAS_MMX
+	select BR2_X86_CPU_HAS_SSE
+	select BR2_X86_CPU_HAS_SSE2
+	select BR2_X86_CPU_HAS_SSE3
+	select BR2_X86_CPU_HAS_SSSE3
 endchoice
 
 choice
-- 
1.7.10.4

next prev parent reply	other threads:[~2012-06-10 11:46 UTC|newest]

Thread overview: 21+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2012-06-10 11:46 [Buildroot] [PATCH 1/1] omap-u-boot-utils: fix visibility in menuconfig Samuel Martin
2012-06-10 11:46 ` [Buildroot] [PATCH v2 1/1] libplayer: fix cflags Samuel Martin
2012-06-10 20:23   ` Peter Korsgaard
2012-06-12 19:27     ` Samuel Martin
2012-06-13  6:41       ` Peter Korsgaard
2012-06-10 11:46 ` [Buildroot] [PATCH v3 0/6] OpenCV update and CPU fetures Samuel Martin
2012-06-10 11:46 ` Samuel Martin [this message]
2012-06-12  6:02   ` [Buildroot] [PATCH v3 1/6] target: add symbols for i386/x86_64 cpu features Arnout Vandecappelle
2012-06-12  6:05   ` Arnout Vandecappelle
2012-06-13 22:38     ` Samuel Martin
2012-06-10 11:46 ` [Buildroot] [PATCH v3 2/6] target: add symbols for PowerPC " Samuel Martin
2012-06-12  6:15   ` Arnout Vandecappelle
2012-06-12  9:48     ` Gustavo Zacarias
2012-06-13 22:44       ` Samuel Martin
2012-06-10 11:46 ` [Buildroot] [PATCH v3 3/6] libevas: refactor *_CONF_OPT assignment with cpu-feature options Samuel Martin
2012-06-10 11:46 ` [Buildroot] [PATCH v3 4/6] sdl_gfx: " Samuel Martin
2012-06-10 11:46 ` [Buildroot] [PATCH v3 5/6] sdl_sound: " Samuel Martin
2012-06-10 11:46 ` [Buildroot] [PATCH v3 6/6] opencv: bump to version 2.4.1 Samuel Martin
2012-06-10 14:41   ` Samuel Martin
2012-06-10 13:04 ` [Buildroot] [PATCH 1/1] omap-u-boot-utils: fix visibility in menuconfig Thomas Petazzoni
2012-06-10 20:14 ` Peter Korsgaard

find likely ancestor, descendant, or conflicting patches for this message:
( dfblob:25ff750 dfblob:49c01e5 )
 OR (
bs:"[Buildroot] [PATCH v3 1/6] target: add symbols for i386/x86_64 cpu features" )
	(help)

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=1339328813-6269-4-git-send-email-s.martin49@gmail.com \
    --to=s.martin49@gmail.com \
    --cc=buildroot@busybox.net \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link

Be sure your reply has a Subject: header at the top and a blank line before the message body.

This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox