[Buildroot] [PATCH 1/7] toolchain-wrapper: pass MIPS optimizations to TOOLCHAIN_WRAPPER_OPTS

[Buildroot] [PATCH 1/7] toolchain-wrapper: pass MIPS optimizations to TOOLCHAIN_WRAPPER_OPTS

[Vicente Olivert Riera]

Signed-off-by: Vicente Olivert Riera <Vincent.Riera@imgtec.com>
---
 toolchain/toolchain-wrapper.mk | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/toolchain/toolchain-wrapper.mk b/toolchain/toolchain-wrapper.mk
index af39071..6e480e6 100644
--- a/toolchain/toolchain-wrapper.mk
+++ b/toolchain/toolchain-wrapper.mk
@@ -12,9 +12,14 @@ endif
 TOOLCHAIN_WRAPPER_ARGS = $($(PKG)_TOOLCHAIN_WRAPPER_ARGS)
 TOOLCHAIN_WRAPPER_ARGS += -DBR_SYSROOT='"$(STAGING_SUBDIR)"'
 
+# MIPS optimization flags
+TOOLCHAIN_WRAPPER_MIPS_OPTS =
+
 # We create a list like '"-mfoo", "-mbar", "-mbarfoo"' so that each flag is a
 # separate argument when used in execv() by the toolchain wrapper.
 TOOLCHAIN_WRAPPER_OPTS = \
+	$(foreach f,$(call qstrip,$(TOOLCHAIN_WRAPPER_MIPS_OPTS)),"$(f)"$(comma))
+TOOLCHAIN_WRAPPER_OPTS += \
 	$(foreach f,$(call qstrip,$(BR2_TARGET_OPTIMIZATION)),"$(f)"$(comma))
 TOOLCHAIN_WRAPPER_ARGS += -DBR_ADDITIONAL_CFLAGS='$(TOOLCHAIN_WRAPPER_OPTS)'
 
-- 
2.10.0

[Buildroot] [PATCH 2/7] MIPS: add support for MSA

[Vicente Olivert Riera]

Signed-off-by: Vicente Olivert Riera <Vincent.Riera@imgtec.com>
---
 arch/Config.in.mips            | 17 +++++++++++++++++
 toolchain/toolchain-wrapper.mk |  3 +++
 2 files changed, 20 insertions(+)

diff --git a/arch/Config.in.mips b/arch/Config.in.mips
index f7bfa21..fb9053c 100644
--- a/arch/Config.in.mips
+++ b/arch/Config.in.mips
@@ -16,6 +16,14 @@ config BR2_MIPS_CPU_MIPS64R5
 config BR2_MIPS_CPU_MIPS64R6
 	bool
 
+# mips cpu features
+config BR2_MIPS_CPU_HAS_MSA
+	bool
+
+# for some cores, MSA support is optional
+config BR2_MIPS_CPU_MAYBE_HAS_MSA
+	bool
+
 choice
 	prompt "Target Architecture Variant"
 	depends on BR2_mips || BR2_mipsel || BR2_mips64 || BR2_mips64el
@@ -113,6 +121,15 @@ config BR2_MIPS_SOFT_FLOAT
 	  floating point functions, then everything will need to be
 	  compiled with soft floating point support (-msoft-float).
 
+config BR2_MIPS_ENABLE_MSA
+	bool "Enable MIPS SIMD Architecture (MSA) support"
+	depends on BR2_MIPS_CPU_MAYBE_HAS_MSA && !BR2_SOFT_FLOAT
+	select BR2_MIPS_CPU_HAS_MSA
+	help
+	  For some CPU cores, the MSA extension is optional.
+	  Select this option if you are certain your particular
+	  implementation has MSA support and you want to use it.
+
 config BR2_ARCH
 	default "mips"		if BR2_mips
 	default "mipsel"	if BR2_mipsel
diff --git a/toolchain/toolchain-wrapper.mk b/toolchain/toolchain-wrapper.mk
index 6e480e6..f9a1899 100644
--- a/toolchain/toolchain-wrapper.mk
+++ b/toolchain/toolchain-wrapper.mk
@@ -14,6 +14,9 @@ TOOLCHAIN_WRAPPER_ARGS += -DBR_SYSROOT='"$(STAGING_SUBDIR)"'
 
 # MIPS optimization flags
 TOOLCHAIN_WRAPPER_MIPS_OPTS =
+ifeq ($(BR2_MIPS_CPU_HAS_MSA),y)
+TOOLCHAIN_WRAPPER_MIPS_OPTS += -mmsa
+endif
 
 # We create a list like '"-mfoo", "-mbar", "-mbarfoo"' so that each flag is a
 # separate argument when used in execv() by the toolchain wrapper.
-- 
2.10.0

[Buildroot] [PATCH 3/7] MIPS: add optional MSA support for M5100 core

[Vicente Olivert Riera]

Signed-off-by: Vicente Olivert Riera <Vincent.Riera@imgtec.com>
---
 arch/Config.in.mips | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/Config.in.mips b/arch/Config.in.mips
index fb9053c..b7bb48c 100644
--- a/arch/Config.in.mips
+++ b/arch/Config.in.mips
@@ -59,6 +59,7 @@ config BR2_mips_m5100
 	bool "M5100"
 	depends on !BR2_ARCH_IS_64
 	select BR2_MIPS_CPU_MIPS32R5
+	select BR2_MIPS_CPU_MAYBE_HAS_MSA
 config BR2_mips_m5101
 	bool "M5101"
 	depends on !BR2_ARCH_IS_64
-- 
2.10.0

[Buildroot] [PATCH 4/7] MIPS: add optional MSA support for M5101 core

[Vicente Olivert Riera]

Signed-off-by: Vicente Olivert Riera <Vincent.Riera@imgtec.com>
---
 arch/Config.in.mips | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/Config.in.mips b/arch/Config.in.mips
index b7bb48c..4122365 100644
--- a/arch/Config.in.mips
+++ b/arch/Config.in.mips
@@ -64,6 +64,7 @@ config BR2_mips_m5101
 	bool "M5101"
 	depends on !BR2_ARCH_IS_64
 	select BR2_MIPS_CPU_MIPS32R5
+	select BR2_MIPS_CPU_MAYBE_HAS_MSA
 config BR2_mips_p5600
 	bool "P5600"
 	depends on !BR2_ARCH_IS_64
-- 
2.10.0

[Buildroot] [PATCH 5/7] MIPS: add optional MSA support for P5600 core

[Vicente Olivert Riera]

Signed-off-by: Vicente Olivert Riera <Vincent.Riera@imgtec.com>
---
 arch/Config.in.mips | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/Config.in.mips b/arch/Config.in.mips
index 4122365..4b41412 100644
--- a/arch/Config.in.mips
+++ b/arch/Config.in.mips
@@ -69,6 +69,7 @@ config BR2_mips_p5600
 	bool "P5600"
 	depends on !BR2_ARCH_IS_64
 	select BR2_MIPS_CPU_MIPS32R5
+	select BR2_MIPS_CPU_MAYBE_HAS_MSA
 config BR2_mips_64
 	bool "Generic MIPS64"
 	depends on BR2_ARCH_IS_64
-- 
2.10.0

[Buildroot] [PATCH 6/7] MIPS: add optional MSA support for I6400 core

[Vicente Olivert Riera]

Signed-off-by: Vicente Olivert Riera <Vincent.Riera@imgtec.com>
---
 arch/Config.in.mips | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/Config.in.mips b/arch/Config.in.mips
index 4b41412..4c92c09 100644
--- a/arch/Config.in.mips
+++ b/arch/Config.in.mips
@@ -90,6 +90,7 @@ config BR2_mips_i6400
 	bool "I6400"
 	depends on BR2_ARCH_IS_64
 	select BR2_MIPS_CPU_MIPS64R6
+	select BR2_MIPS_CPU_MAYBE_HAS_MSA
 config BR2_mips_p6600
 	bool "P6600"
 	depends on BR2_ARCH_IS_64
-- 
2.10.0

[Buildroot] [PATCH 7/7] MIPS: add optional MSA support for P6600 core

[Vicente Olivert Riera]

Signed-off-by: Vicente Olivert Riera <Vincent.Riera@imgtec.com>
---
 arch/Config.in.mips | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/Config.in.mips b/arch/Config.in.mips
index 4c92c09..51f46df 100644
--- a/arch/Config.in.mips
+++ b/arch/Config.in.mips
@@ -95,6 +95,7 @@ config BR2_mips_p6600
 	bool "P6600"
 	depends on BR2_ARCH_IS_64
 	select BR2_MIPS_CPU_MIPS64R6
+	select BR2_MIPS_CPU_MAYBE_HAS_MSA
 endchoice
 
 
-- 
2.10.0

[Buildroot] [PATCH 1/7] toolchain-wrapper: pass MIPS optimizations to TOOLCHAIN_WRAPPER_OPTS

[Arnout Vandecappelle]

 Hi Vincent,

On 16-10-16 19:05, Vicente Olivert Riera wrote:
> Signed-off-by: Vicente Olivert Riera <Vincent.Riera@imgtec.com>
> ---
>  toolchain/toolchain-wrapper.mk | 5 +++++
>  1 file changed, 5 insertions(+)
> 
> diff --git a/toolchain/toolchain-wrapper.mk b/toolchain/toolchain-wrapper.mk
> index af39071..6e480e6 100644
> --- a/toolchain/toolchain-wrapper.mk
> +++ b/toolchain/toolchain-wrapper.mk
> @@ -12,9 +12,14 @@ endif
>  TOOLCHAIN_WRAPPER_ARGS = $($(PKG)_TOOLCHAIN_WRAPPER_ARGS)
>  TOOLCHAIN_WRAPPER_ARGS += -DBR_SYSROOT='"$(STAGING_SUBDIR)"'
>  
> +# MIPS optimization flags
> +TOOLCHAIN_WRAPPER_MIPS_OPTS =

 This is not exactly what I meant, so I've sent a quick patch that does do what
I meant. Wait a little for Thomas to provide feedback on it, and then you can
include it in your series. For now I've marked the series as Superseded and
Changes Requested.

 Regards,
 Arnout

> +
>  # We create a list like '"-mfoo", "-mbar", "-mbarfoo"' so that each flag is a
>  # separate argument when used in execv() by the toolchain wrapper.
>  TOOLCHAIN_WRAPPER_OPTS = \
> +	$(foreach f,$(call qstrip,$(TOOLCHAIN_WRAPPER_MIPS_OPTS)),"$(f)"$(comma))
> +TOOLCHAIN_WRAPPER_OPTS += \
>  	$(foreach f,$(call qstrip,$(BR2_TARGET_OPTIMIZATION)),"$(f)"$(comma))
>  TOOLCHAIN_WRAPPER_ARGS += -DBR_ADDITIONAL_CFLAGS='$(TOOLCHAIN_WRAPPER_OPTS)'
>  
> 

-- 
Arnout Vandecappelle                          arnout at mind be
Senior Embedded Software Architect            +32-16-286500
Essensium/Mind                                http://www.mind.be
G.Geenslaan 9, 3001 Leuven, Belgium           BE 872 984 063 RPR Leuven
LinkedIn profile: http://www.linkedin.com/in/arnoutvandecappelle
GPG fingerprint:  7493 020B C7E3 8618 8DEC 222C 82EB F404 F9AC 0DDF

[Buildroot] [PATCH 1/7] toolchain-wrapper: pass MIPS optimizations to TOOLCHAIN_WRAPPER_OPTS

[Thomas Petazzoni]

Hello,

On Tue, 18 Oct 2016 20:59:08 +0200, Arnout Vandecappelle wrote:

>  This is not exactly what I meant, so I've sent a quick patch that does do what
> I meant. Wait a little for Thomas to provide feedback on it, and then you can
> include it in your series. For now I've marked the series as Superseded and
> Changes Requested.

Only patches 1/7 and 2/7 were marked as Changes Requested or
Superseded, but patches 3/7 to 7/7 were still in patchwork. So I've
also marked them as Changes Requested, as they need to be resent with
the rest.

Vicente: for the next iteration, you can merge patches 3/7 to 7/7 in a
single patch, like:

  mips: indicate which MIPS cores have MSA support

Thanks,

Thomas
-- 
Thomas Petazzoni, CTO, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com