* [Buildroot] [PATCH 1/6] arch/arm: add cortex-m7 core
2018-02-25 20:18 [Buildroot] [PATCH 0/6] arch/ar: add cortex-m7, and cortex-M FPUs Yann E. MORIN
@ 2018-02-25 20:18 ` Yann E. MORIN
2018-05-20 16:51 ` Thomas Petazzoni
2018-02-25 20:18 ` [Buildroot] [PATCH 2/6] arch/arm: introduce generic FPU internal option Yann E. MORIN
` (5 subsequent siblings)
6 siblings, 1 reply; 10+ messages in thread
From: Yann E. MORIN @ 2018-02-25 20:18 UTC (permalink / raw)
To: buildroot
Nothing fancy, just a plain Cortex-M, armv7-M core...
Signed-off-by: "Yann E. MORIN" <yann.morin.1998@free.fr>
---
arch/Config.in.arm | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/Config.in.arm b/arch/Config.in.arm
index b05e83e33c..67f8a16737 100644
--- a/arch/Config.in.arm
+++ b/arch/Config.in.arm
@@ -241,6 +241,11 @@ config BR2_cortex_m4
bool "cortex-M4"
select BR2_ARM_CPU_HAS_THUMB2
select BR2_ARM_CPU_ARMV7M
+config BR2_cortex_m7
+ bool "cortex-M7"
+ select BR2_ARM_CPU_HAS_THUMB2
+ select BR2_ARM_CPU_ARMV7M
+ select BR2_ARCH_NEEDS_GCC_AT_LEAST_5
endif # !BR2_ARCH_IS_64
comment "armv8 cores"
@@ -716,6 +721,7 @@ config BR2_GCC_TARGET_CPU
# armv7m
default "cortex-m3" if BR2_cortex_m3
default "cortex-m4" if BR2_cortex_m4
+ default "cortex-m7" if BR2_cortex_m7
# armv8a
default "cortex-a32" if BR2_cortex_a32
default "cortex-a35" if BR2_cortex_a35
--
2.14.1
^ permalink raw reply related [flat|nested] 10+ messages in thread* [Buildroot] [PATCH 1/6] arch/arm: add cortex-m7 core
2018-02-25 20:18 ` [Buildroot] [PATCH 1/6] arch/arm: add cortex-m7 core Yann E. MORIN
@ 2018-05-20 16:51 ` Thomas Petazzoni
0 siblings, 0 replies; 10+ messages in thread
From: Thomas Petazzoni @ 2018-05-20 16:51 UTC (permalink / raw)
To: buildroot
Hello,
On Sun, 25 Feb 2018 21:18:13 +0100, Yann E. MORIN wrote:
> Nothing fancy, just a plain Cortex-M, armv7-M core...
>
> Signed-off-by: "Yann E. MORIN" <yann.morin.1998@free.fr>
> ---
> arch/Config.in.arm | 6 ++++++
> 1 file changed, 6 insertions(+)
Applied to next, thanks.
Thomas
--
Thomas Petazzoni, CTO, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
https://bootlin.com
^ permalink raw reply [flat|nested] 10+ messages in thread
* [Buildroot] [PATCH 2/6] arch/arm: introduce generic FPU internal option
2018-02-25 20:18 [Buildroot] [PATCH 0/6] arch/ar: add cortex-m7, and cortex-M FPUs Yann E. MORIN
2018-02-25 20:18 ` [Buildroot] [PATCH 1/6] arch/arm: add cortex-m7 core Yann E. MORIN
@ 2018-02-25 20:18 ` Yann E. MORIN
2018-02-25 20:18 ` [Buildroot] [PATCH 3/6] arch/arm: add option for FPv4 FPU Yann E. MORIN
` (4 subsequent siblings)
6 siblings, 0 replies; 10+ messages in thread
From: Yann E. MORIN @ 2018-02-25 20:18 UTC (permalink / raw)
To: buildroot
Currently, we consider that any VFP FPU is a superset of VFPv2, and thus
we use VFPv2 as a way to detect that a VFP is used.
However, for Cortex-M cores, the optional FPU is not a superset of
VFPv2; it is even not a VFP [0].
As a consequence, we can no longer consider VFPv2 as a indication that
an FPU is present.
So, we introduce two new internal options, BR2_ARM_CPU_MAYBE_HAS_FPU and
BR2_ARM_CPU_HAS_FPU, which we use to consider the presence of an FPU.
[0] https://en.wikipedia.org/wiki/ARM_Cortex-M#Cortex-M4
Signed-off-by: "Yann E. MORIN" <yann.morin.1998@free.fr>
---
arch/Config.in.arm | 17 +++++++++++++----
1 file changed, 13 insertions(+), 4 deletions(-)
diff --git a/arch/Config.in.arm b/arch/Config.in.arm
index 67f8a16737..89db5fad08 100644
--- a/arch/Config.in.arm
+++ b/arch/Config.in.arm
@@ -6,12 +6,21 @@ config BR2_ARM_CPU_HAS_NEON
config BR2_ARM_CPU_MAYBE_HAS_NEON
bool
+# For some cores, the FPU is optional
+config BR2_ARM_CPU_MAYBE_HAS_FPU
+ bool
+
+config BR2_ARM_CPU_HAS_FPU
+ bool
+
# for some cores, VFPv2 is optional
config BR2_ARM_CPU_MAYBE_HAS_VFPV2
bool
+ select BR2_ARM_CPU_MAYBE_HAS_FPU
config BR2_ARM_CPU_HAS_VFPV2
bool
+ select BR2_ARM_CPU_HAS_FPU
# for some cores, VFPv3 is optional
config BR2_ARM_CPU_MAYBE_HAS_VFPV3
@@ -450,7 +459,7 @@ config BR2_ARM_ENABLE_NEON
config BR2_ARM_ENABLE_VFP
bool "Enable VFP extension support"
- depends on BR2_ARM_CPU_MAYBE_HAS_VFPV2
+ depends on BR2_ARM_CPU_MAYBE_HAS_FPU
select BR2_ARM_CPU_HAS_VFPV4 if BR2_ARM_CPU_MAYBE_HAS_VFPV4
select BR2_ARM_CPU_HAS_VFPV3 if BR2_ARM_CPU_MAYBE_HAS_VFPV3
select BR2_ARM_CPU_HAS_VFPV2 if BR2_ARM_CPU_MAYBE_HAS_VFPV2
@@ -462,7 +471,7 @@ config BR2_ARM_ENABLE_VFP
choice
prompt "Target ABI"
depends on BR2_arm || BR2_armeb
- default BR2_ARM_EABIHF if BR2_ARM_CPU_HAS_VFPV2
+ default BR2_ARM_EABIHF if BR2_ARM_CPU_HAS_FPU
default BR2_ARM_EABI
help
Application Binary Interface to use. The Application Binary
@@ -496,7 +505,7 @@ config BR2_ARM_EABI
config BR2_ARM_EABIHF
bool "EABIhf"
- depends on BR2_ARM_CPU_HAS_VFPV2
+ depends on BR2_ARM_CPU_HAS_FPU
help
The EABIhf is an extension of EABI which supports the 'hard'
floating point model. This model uses the floating point
@@ -520,7 +529,7 @@ choice
default BR2_ARM_FPU_VFPV4D16 if BR2_ARM_CPU_HAS_VFPV4
default BR2_ARM_FPU_VFPV3D16 if BR2_ARM_CPU_HAS_VFPV3
default BR2_ARM_FPU_VFPV2 if BR2_ARM_CPU_HAS_VFPV2
- default BR2_ARM_SOFT_FLOAT if !BR2_ARM_CPU_HAS_VFPV2
+ default BR2_ARM_SOFT_FLOAT if !BR2_ARM_CPU_HAS_FPU
config BR2_ARM_SOFT_FLOAT
bool "Soft float"
--
2.14.1
^ permalink raw reply related [flat|nested] 10+ messages in thread* [Buildroot] [PATCH 3/6] arch/arm: add option for FPv4 FPU
2018-02-25 20:18 [Buildroot] [PATCH 0/6] arch/ar: add cortex-m7, and cortex-M FPUs Yann E. MORIN
2018-02-25 20:18 ` [Buildroot] [PATCH 1/6] arch/arm: add cortex-m7 core Yann E. MORIN
2018-02-25 20:18 ` [Buildroot] [PATCH 2/6] arch/arm: introduce generic FPU internal option Yann E. MORIN
@ 2018-02-25 20:18 ` Yann E. MORIN
2018-02-25 20:18 ` [Buildroot] [PATCH 4/6] arch/arm: add options for FPv5 FPU Yann E. MORIN
` (3 subsequent siblings)
6 siblings, 0 replies; 10+ messages in thread
From: Yann E. MORIN @ 2018-02-25 20:18 UTC (permalink / raw)
To: buildroot
The FPv4-SP FPU is a single-precision FPU with 16 double registers [0]
[1]. It is only available for cortex-m4 cores, and is known to gcc as
fpv4-sp-d16 (note that there is no leading 'v') since gcc-4.5 [2].
[0] https://en.wikipedia.org/wiki/ARM_Cortex-M#Cortex-M4
[1] https://developer.arm.com/docs/ddi0439/latest/floating-point-unit
[2] https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=639cb7b789a54bf78d6ae5e2644450f5eb1837a6
Signed-off-by: "Yann E. MORIN" <yann.morin.1998@free.fr>
---
arch/Config.in.arm | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/arch/Config.in.arm b/arch/Config.in.arm
index 89db5fad08..b063ee33fd 100644
--- a/arch/Config.in.arm
+++ b/arch/Config.in.arm
@@ -40,6 +40,15 @@ config BR2_ARM_CPU_HAS_VFPV4
bool
select BR2_ARM_CPU_HAS_VFPV3
+# FPv4 is always optional
+config BR2_ARM_CPU_MAYBE_HAS_FPV4
+ bool
+ select BR2_ARM_CPU_MAYBE_HAS_FPU
+
+config BR2_ARM_CPU_HAS_FPV4
+ bool
+ select BR2_ARM_CPU_HAS_FPU
+
config BR2_ARM_CPU_HAS_FP_ARMV8
bool
select BR2_ARM_CPU_HAS_VFPV4
@@ -460,6 +469,7 @@ config BR2_ARM_ENABLE_NEON
config BR2_ARM_ENABLE_VFP
bool "Enable VFP extension support"
depends on BR2_ARM_CPU_MAYBE_HAS_FPU
+ select BR2_ARM_CPU_HAS_FPV4 if BR2_ARM_CPU_MAYBE_HAS_FPV4
select BR2_ARM_CPU_HAS_VFPV4 if BR2_ARM_CPU_MAYBE_HAS_VFPV4
select BR2_ARM_CPU_HAS_VFPV3 if BR2_ARM_CPU_MAYBE_HAS_VFPV3
select BR2_ARM_CPU_HAS_VFPV2 if BR2_ARM_CPU_MAYBE_HAS_VFPV2
@@ -526,6 +536,7 @@ endchoice
choice
prompt "Floating point strategy"
default BR2_ARM_FPU_FP_ARMV8 if BR2_ARM_CPU_HAS_FP_ARMV8
+ default BR2_ARM_FPU_FPV4D16 if BR2_ARM_CPU_HAS_FPV4
default BR2_ARM_FPU_VFPV4D16 if BR2_ARM_CPU_HAS_VFPV4
default BR2_ARM_FPU_VFPV3D16 if BR2_ARM_CPU_HAS_VFPV3
default BR2_ARM_FPU_VFPV2 if BR2_ARM_CPU_HAS_VFPV2
@@ -636,6 +647,14 @@ config BR2_ARM_FPU_NEON_VFPV4
example on Cortex-A5 and Cortex-A7, support for VFPv4 and
NEON is optional.
+config BR2_ARM_FPU_FPV4D16
+ bool "FPv4-D16"
+ depends on BR2_ARM_CPU_HAS_FPV4
+ help
+ This option allows to use the FPv4-SP (single precision)
+ floating point unit, as available in some ARMv7m processors
+ (Cortex-M4).
+
config BR2_ARM_FPU_FP_ARMV8
bool "FP-ARMv8"
depends on BR2_ARM_CPU_HAS_FP_ARMV8
@@ -769,6 +788,7 @@ config BR2_GCC_TARGET_FPU
default "vfpv4-d16" if BR2_ARM_FPU_VFPV4D16
default "neon" if BR2_ARM_FPU_NEON
default "neon-vfpv4" if BR2_ARM_FPU_NEON_VFPV4
+ default "fpv4-sp-d16" if BR2_ARM_FPU_FPV4D16
default "fp-armv8" if BR2_ARM_FPU_FP_ARMV8
default "neon-fp-armv8" if BR2_ARM_FPU_NEON_FP_ARMV8
--
2.14.1
^ permalink raw reply related [flat|nested] 10+ messages in thread* [Buildroot] [PATCH 4/6] arch/arm: add options for FPv5 FPU
2018-02-25 20:18 [Buildroot] [PATCH 0/6] arch/ar: add cortex-m7, and cortex-M FPUs Yann E. MORIN
` (2 preceding siblings ...)
2018-02-25 20:18 ` [Buildroot] [PATCH 3/6] arch/arm: add option for FPv4 FPU Yann E. MORIN
@ 2018-02-25 20:18 ` Yann E. MORIN
2018-02-25 20:18 ` [Buildroot] [PATCH 5/6] arch/arm: cortex-m4 may have an FPv4 FPU Yann E. MORIN
` (2 subsequent siblings)
6 siblings, 0 replies; 10+ messages in thread
From: Yann E. MORIN @ 2018-02-25 20:18 UTC (permalink / raw)
To: buildroot
Contrary to its older brother, the FPv5 comes in two flavours; single-
and double-precision [0] [1]. the two variants are only available for
cortex-m7 cores, and the two variants are known to gcc as fpv5-sp-d16
and fpv5-d16, respectively, since gcc-5 [2].
[0] https://en.wikipedia.org/wiki/ARM_Cortex-M#Cortex-M7
[1] https://developer.arm.com/docs/ddi0489/latest/floating-point-unit
[2] https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=a076f99fa702deac764f6e0441b9435ad999f521
Signed-off-by: "Yann E. MORIN" <yann.morin.1998@free.fr>
---
arch/Config.in.arm | 37 +++++++++++++++++++++++++++++++++++++
1 file changed, 37 insertions(+)
diff --git a/arch/Config.in.arm b/arch/Config.in.arm
index b063ee33fd..8fd11cc157 100644
--- a/arch/Config.in.arm
+++ b/arch/Config.in.arm
@@ -49,6 +49,15 @@ config BR2_ARM_CPU_HAS_FPV4
bool
select BR2_ARM_CPU_HAS_FPU
+# FPv5 is always optional
+config BR2_ARM_CPU_MAYBE_HAS_FPV5
+ bool
+ select BR2_ARM_CPU_MAYBE_HAS_FPV4
+
+config BR2_ARM_CPU_HAS_FPV5
+ bool
+ select BR2_ARM_CPU_HAS_FPV4
+
config BR2_ARM_CPU_HAS_FP_ARMV8
bool
select BR2_ARM_CPU_HAS_VFPV4
@@ -469,6 +478,7 @@ config BR2_ARM_ENABLE_NEON
config BR2_ARM_ENABLE_VFP
bool "Enable VFP extension support"
depends on BR2_ARM_CPU_MAYBE_HAS_FPU
+ select BR2_ARM_CPU_HAS_FPV5 if BR2_ARM_CPU_MAYBE_HAS_FPV5
select BR2_ARM_CPU_HAS_FPV4 if BR2_ARM_CPU_MAYBE_HAS_FPV4
select BR2_ARM_CPU_HAS_VFPV4 if BR2_ARM_CPU_MAYBE_HAS_VFPV4
select BR2_ARM_CPU_HAS_VFPV3 if BR2_ARM_CPU_MAYBE_HAS_VFPV3
@@ -536,6 +546,7 @@ endchoice
choice
prompt "Floating point strategy"
default BR2_ARM_FPU_FP_ARMV8 if BR2_ARM_CPU_HAS_FP_ARMV8
+ default BR2_ARM_FPU_FPV5D16 if BR2_ARM_CPU_HAS_FPV5
default BR2_ARM_FPU_FPV4D16 if BR2_ARM_CPU_HAS_FPV4
default BR2_ARM_FPU_VFPV4D16 if BR2_ARM_CPU_HAS_VFPV4
default BR2_ARM_FPU_VFPV3D16 if BR2_ARM_CPU_HAS_VFPV3
@@ -655,6 +666,30 @@ config BR2_ARM_FPU_FPV4D16
floating point unit, as available in some ARMv7m processors
(Cortex-M4).
+config BR2_ARM_FPU_FPV5D16
+ bool "FPv5-D16"
+ depends on BR2_ARM_CPU_HAS_FPV5
+ select BR2_ARCH_NEEDS_GCC_AT_LEAST_5
+ help
+ This option allows to use the FPv5-SP (single precision)
+ floating point unit, as available in some ARMv7m processors
+ (Cortex-M7).
+
+ Note that if you want binary code that works on the earlier
+ Cortex-M4, you should instead select FPv4-D16.
+
+config BR2_ARM_FPU_FPV5DPD16
+ bool "FPv5-DP-D16"
+ depends on BR2_ARM_CPU_HAS_FPV5
+ select BR2_ARCH_NEEDS_GCC_AT_LEAST_5
+ help
+ This option allows to use the FPv5-DP (double precision)
+ floating point unit, as available in some ARMv7m processors
+ (Cortex-M7).
+
+ Note that if you want binary code that works on the earlier
+ Cortex-M4, you should instead select FPv4-D16.
+
config BR2_ARM_FPU_FP_ARMV8
bool "FP-ARMv8"
depends on BR2_ARM_CPU_HAS_FP_ARMV8
@@ -789,6 +824,8 @@ config BR2_GCC_TARGET_FPU
default "neon" if BR2_ARM_FPU_NEON
default "neon-vfpv4" if BR2_ARM_FPU_NEON_VFPV4
default "fpv4-sp-d16" if BR2_ARM_FPU_FPV4D16
+ default "fpv5-sp-d16" if BR2_ARM_FPU_FPV5D16
+ default "fpv5-d16" if BR2_ARM_FPU_FPV5DPD16
default "fp-armv8" if BR2_ARM_FPU_FP_ARMV8
default "neon-fp-armv8" if BR2_ARM_FPU_NEON_FP_ARMV8
--
2.14.1
^ permalink raw reply related [flat|nested] 10+ messages in thread* [Buildroot] [PATCH 5/6] arch/arm: cortex-m4 may have an FPv4 FPU
2018-02-25 20:18 [Buildroot] [PATCH 0/6] arch/ar: add cortex-m7, and cortex-M FPUs Yann E. MORIN
` (3 preceding siblings ...)
2018-02-25 20:18 ` [Buildroot] [PATCH 4/6] arch/arm: add options for FPv5 FPU Yann E. MORIN
@ 2018-02-25 20:18 ` Yann E. MORIN
2018-02-25 20:18 ` [Buildroot] [PATCH 6/6] arch/arm: cortex-m7 may have a FPv5 FPU Yann E. MORIN
2018-05-20 17:22 ` [Buildroot] [PATCH 0/6] arch/ar: add cortex-m7, and cortex-M FPUs Thomas Petazzoni
6 siblings, 0 replies; 10+ messages in thread
From: Yann E. MORIN @ 2018-02-25 20:18 UTC (permalink / raw)
To: buildroot
Signed-off-by: "Yann E. MORIN" <yann.morin.1998@free.fr>
---
arch/Config.in.arm | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/Config.in.arm b/arch/Config.in.arm
index 8fd11cc157..7c0fcacc36 100644
--- a/arch/Config.in.arm
+++ b/arch/Config.in.arm
@@ -267,6 +267,7 @@ config BR2_cortex_m3
config BR2_cortex_m4
bool "cortex-M4"
select BR2_ARM_CPU_HAS_THUMB2
+ select BR2_ARM_CPU_MAYBE_HAS_FPV4
select BR2_ARM_CPU_ARMV7M
config BR2_cortex_m7
bool "cortex-M7"
--
2.14.1
^ permalink raw reply related [flat|nested] 10+ messages in thread* [Buildroot] [PATCH 6/6] arch/arm: cortex-m7 may have a FPv5 FPU
2018-02-25 20:18 [Buildroot] [PATCH 0/6] arch/ar: add cortex-m7, and cortex-M FPUs Yann E. MORIN
` (4 preceding siblings ...)
2018-02-25 20:18 ` [Buildroot] [PATCH 5/6] arch/arm: cortex-m4 may have an FPv4 FPU Yann E. MORIN
@ 2018-02-25 20:18 ` Yann E. MORIN
2018-05-20 17:22 ` [Buildroot] [PATCH 0/6] arch/ar: add cortex-m7, and cortex-M FPUs Thomas Petazzoni
6 siblings, 0 replies; 10+ messages in thread
From: Yann E. MORIN @ 2018-02-25 20:18 UTC (permalink / raw)
To: buildroot
Signed-off-by: "Yann E. MORIN" <yann.morin.1998@free.fr>
---
arch/Config.in.arm | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/Config.in.arm b/arch/Config.in.arm
index 7c0fcacc36..640ad93f8b 100644
--- a/arch/Config.in.arm
+++ b/arch/Config.in.arm
@@ -272,6 +272,7 @@ config BR2_cortex_m4
config BR2_cortex_m7
bool "cortex-M7"
select BR2_ARM_CPU_HAS_THUMB2
+ select BR2_ARM_CPU_MAYBE_HAS_FPV5
select BR2_ARM_CPU_ARMV7M
select BR2_ARCH_NEEDS_GCC_AT_LEAST_5
endif # !BR2_ARCH_IS_64
--
2.14.1
^ permalink raw reply related [flat|nested] 10+ messages in thread* [Buildroot] [PATCH 0/6] arch/ar: add cortex-m7, and cortex-M FPUs
2018-02-25 20:18 [Buildroot] [PATCH 0/6] arch/ar: add cortex-m7, and cortex-M FPUs Yann E. MORIN
` (5 preceding siblings ...)
2018-02-25 20:18 ` [Buildroot] [PATCH 6/6] arch/arm: cortex-m7 may have a FPv5 FPU Yann E. MORIN
@ 2018-05-20 17:22 ` Thomas Petazzoni
2018-05-20 17:27 ` Yann E. MORIN
6 siblings, 1 reply; 10+ messages in thread
From: Thomas Petazzoni @ 2018-05-20 17:22 UTC (permalink / raw)
To: buildroot
Hello,
On Sun, 25 Feb 2018 21:18:14 +0100, Yann E. MORIN wrote:
> Yann E. MORIN (6):
> arch/arm: add cortex-m7 core
> arch/arm: introduce generic FPU internal option
> arch/arm: add option for FPv4 FPU
> arch/arm: add options for FPv5 FPU
> arch/arm: cortex-m4 may have an FPv4 FPU
> arch/arm: cortex-m7 may have a FPv5 FPU
Entire series applied to next.
As discussed on IRC, I initially screwed up and applied PATCH 1/6 on
the master branch, so I reverted it, and applied the whole thing on the
next branch.
Thanks!
Thomas
--
Thomas Petazzoni, CTO, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
https://bootlin.com
^ permalink raw reply [flat|nested] 10+ messages in thread* [Buildroot] [PATCH 0/6] arch/ar: add cortex-m7, and cortex-M FPUs
2018-05-20 17:22 ` [Buildroot] [PATCH 0/6] arch/ar: add cortex-m7, and cortex-M FPUs Thomas Petazzoni
@ 2018-05-20 17:27 ` Yann E. MORIN
0 siblings, 0 replies; 10+ messages in thread
From: Yann E. MORIN @ 2018-05-20 17:27 UTC (permalink / raw)
To: buildroot
Thomas, All,
On 2018-05-20 19:22 +0200, Thomas Petazzoni spake thusly:
> On Sun, 25 Feb 2018 21:18:14 +0100, Yann E. MORIN wrote:
> > Yann E. MORIN (6):
> > arch/arm: add cortex-m7 core
> > arch/arm: introduce generic FPU internal option
> > arch/arm: add option for FPv4 FPU
> > arch/arm: add options for FPv5 FPU
> > arch/arm: cortex-m4 may have an FPv4 FPU
> > arch/arm: cortex-m7 may have a FPv5 FPU
>
> Entire series applied to next.
Thank you! ;-)
> As discussed on IRC, I initially screwed up and applied PATCH 1/6 on
> the master branch, so I reverted it, and applied the whole thing on the
> next branch.
Fortunately, a highly-sedulous vigilante was quick to notice the issue
and prompt the revert! ;-]
Thanks! ;-)
Regards,
Yann E. MORIN.
--
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| +33 662 376 056 | Software Designer | \ / CAMPAIGN | ___ |
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^ permalink raw reply [flat|nested] 10+ messages in thread