From: "Yann E. MORIN" <yann.morin.1998@free.fr>
To: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
Cc: Niklas Cassel <niklas.cassel@wdc.com>,
Damien Le Moal <damien.lemoal@wdc.com>,
Mark Corbin <mark@dibsco.co.uk>,
Jonathan Ben Avraham <yba@tkos.co.il>,
buildroot@buildroot.org,
Giulio Benetti <giulio.benetti@benettiengineering.com>,
Romain Naour <romain.naour@gmail.com>,
Thomas De Schampheleire <thomas.de_schampheleire@nokia.com>
Subject: Re: [Buildroot] [PATCH v2 4/4] arch: rework MMU option handling and move to "Target architecture" menu
Date: Wed, 27 Jul 2022 11:43:17 +0200 [thread overview]
Message-ID: <20220727094317.GF1085273@scaer> (raw)
In-Reply-To: <20220726163951.2111731-4-thomas.petazzoni@bootlin.com>
Thomas, All,
On 2022-07-26 18:39 +0200, Thomas Petazzoni via buildroot spake thusly:
> The MMU option is currently located in the "Toolchain" menu, but it
> doesn't make sense as it's really architecture related. In addition,
> the selection of MMU has an impact on the choice of binary format
> available, which is visible in the architecture menu.
>
> Therefore, this commit moves the MMU option into the architecture
> menu.
I slightly expanded on that after your reply.
[--SNIP--]
> This commit might raise a concern in terms of backward compatibility
> with existing configurations. The only configurations that will be
> broken by this change are RISC-V noMMU (which was very recently
> introduced) and Xtensa noMMU (which we can probably agree is not such
> a widely popular configuration).
Indeed. People in this game know what to do and look for.
Applied to master, thanks.
Regards,
Yann E. MORIN.
> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
> ---
> Changes since v1:
> - Make BR2_RISCV_USE_MMU and BR2_XTENSA_USE_MMU default y to behave
> like BR2_USE_MMU used to
> - Update the defconfigs that had "# BR2_USE_MMU is not set" to use the
> new option.
> ---
> arch/Config.in | 47 +++++++++++------------
> arch/Config.in.arm | 10 ++---
> arch/Config.in.m68k | 2 +-
> arch/Config.in.riscv | 12 +++++-
> arch/Config.in.xtensa | 12 +++++-
> configs/canaan_kd233_defconfig | 2 +-
> configs/qemu_riscv64_nommu_virt_defconfig | 4 +-
> configs/qemu_xtensa_lx60_nommu_defconfig | 4 +-
> configs/sipeed_maix_bit_defconfig | 2 +-
> configs/sipeed_maix_bit_sdcard_defconfig | 2 +-
> configs/sipeed_maix_dock_defconfig | 2 +-
> configs/sipeed_maix_dock_sdcard_defconfig | 2 +-
> configs/sipeed_maix_go_defconfig | 2 +-
> configs/sipeed_maix_go_sdcard_defconfig | 2 +-
> configs/sipeed_maixduino_defconfig | 2 +-
> configs/sipeed_maixduino_sdcard_defconfig | 2 +-
> toolchain/Config.in | 7 ----
> 17 files changed, 59 insertions(+), 57 deletions(-)
>
> diff --git a/arch/Config.in b/arch/Config.in
> index 095036f1aa..1d38c7a065 100644
> --- a/arch/Config.in
> +++ b/arch/Config.in
> @@ -9,10 +9,7 @@ config BR2_KERNEL_64_USERLAND_32
> config BR2_SOFT_FLOAT
> bool
>
> -config BR2_ARCH_HAS_MMU_MANDATORY
> - bool
> -
> -config BR2_ARCH_HAS_MMU_OPTIONAL
> +config BR2_USE_MMU
> bool
>
> choice
> @@ -23,7 +20,7 @@ choice
>
> config BR2_arcle
> bool "ARC (little endian)"
> - select BR2_ARCH_HAS_MMU_MANDATORY
> + select BR2_USE_MMU
> help
> Synopsys' DesignWare ARC Processor Cores are a family of
> 32-bit CPUs that can be used from deeply embedded to high
> @@ -31,7 +28,7 @@ config BR2_arcle
>
> config BR2_arceb
> bool "ARC (big endian)"
> - select BR2_ARCH_HAS_MMU_MANDATORY
> + select BR2_USE_MMU
> help
> Synopsys' DesignWare ARC Processor Cores are a family of
> 32-bit CPUs that can be used from deeply embedded to high
> @@ -49,7 +46,7 @@ config BR2_arm
>
> config BR2_armeb
> bool "ARM (big endian)"
> - select BR2_ARCH_HAS_MMU_MANDATORY
> + select BR2_USE_MMU
> help
> ARM is a 32-bit reduced instruction set computer (RISC)
> instruction set architecture (ISA) developed by ARM Holdings.
> @@ -76,7 +73,7 @@ config BR2_aarch64_be
> config BR2_csky
> bool "csky"
> select BR2_ARCH_HAS_NO_TOOLCHAIN_BUILDROOT
> - select BR2_ARCH_HAS_MMU_MANDATORY
> + select BR2_USE_MMU
> select BR2_ARCH_NEEDS_GCC_AT_LEAST_9
> help
> csky is processor IP from china.
> @@ -85,7 +82,7 @@ config BR2_csky
>
> config BR2_i386
> bool "i386"
> - select BR2_ARCH_HAS_MMU_MANDATORY
> + select BR2_USE_MMU
> help
> Intel i386 architecture compatible microprocessor
> http://en.wikipedia.org/wiki/I386
> @@ -99,7 +96,7 @@ config BR2_m68k
>
> config BR2_microblazeel
> bool "Microblaze AXI (little endian)"
> - select BR2_ARCH_HAS_MMU_MANDATORY
> + select BR2_USE_MMU
> help
> Soft processor core designed for Xilinx FPGAs from Xilinx. AXI
> bus based architecture (little endian)
> @@ -108,7 +105,7 @@ config BR2_microblazeel
>
> config BR2_microblazebe
> bool "Microblaze non-AXI (big endian)"
> - select BR2_ARCH_HAS_MMU_MANDATORY
> + select BR2_USE_MMU
> help
> Soft processor core designed for Xilinx FPGAs from Xilinx. PLB
> bus based architecture (non-AXI, big endian)
> @@ -117,7 +114,7 @@ config BR2_microblazebe
>
> config BR2_mips
> bool "MIPS (big endian)"
> - select BR2_ARCH_HAS_MMU_MANDATORY
> + select BR2_USE_MMU
> help
> MIPS is a RISC microprocessor from MIPS Technologies. Big
> endian.
> @@ -126,7 +123,7 @@ config BR2_mips
>
> config BR2_mipsel
> bool "MIPS (little endian)"
> - select BR2_ARCH_HAS_MMU_MANDATORY
> + select BR2_USE_MMU
> help
> MIPS is a RISC microprocessor from MIPS Technologies. Little
> endian.
> @@ -136,7 +133,7 @@ config BR2_mipsel
> config BR2_mips64
> bool "MIPS64 (big endian)"
> select BR2_ARCH_IS_64
> - select BR2_ARCH_HAS_MMU_MANDATORY
> + select BR2_USE_MMU
> help
> MIPS is a RISC microprocessor from MIPS Technologies. Big
> endian.
> @@ -146,7 +143,7 @@ config BR2_mips64
> config BR2_mips64el
> bool "MIPS64 (little endian)"
> select BR2_ARCH_IS_64
> - select BR2_ARCH_HAS_MMU_MANDATORY
> + select BR2_USE_MMU
> help
> MIPS is a RISC microprocessor from MIPS Technologies. Little
> endian.
> @@ -155,7 +152,7 @@ config BR2_mips64el
>
> config BR2_nios2
> bool "Nios II"
> - select BR2_ARCH_HAS_MMU_MANDATORY
> + select BR2_USE_MMU
> help
> Nios II is a soft core processor from Altera Corporation.
> http://www.altera.com/
> @@ -163,14 +160,14 @@ config BR2_nios2
>
> config BR2_or1k
> bool "OpenRISC"
> - select BR2_ARCH_HAS_MMU_MANDATORY
> + select BR2_USE_MMU
> help
> OpenRISC is a free and open processor for embedded system.
> http://openrisc.io
>
> config BR2_powerpc
> bool "PowerPC"
> - select BR2_ARCH_HAS_MMU_MANDATORY
> + select BR2_USE_MMU
> help
> PowerPC is a RISC architecture created by Apple-IBM-Motorola
> alliance. Big endian.
> @@ -180,7 +177,7 @@ config BR2_powerpc
> config BR2_powerpc64
> bool "PowerPC64 (big endian)"
> select BR2_ARCH_IS_64
> - select BR2_ARCH_HAS_MMU_MANDATORY
> + select BR2_USE_MMU
> help
> PowerPC is a RISC architecture created by Apple-IBM-Motorola
> alliance. Big endian.
> @@ -190,7 +187,7 @@ config BR2_powerpc64
> config BR2_powerpc64le
> bool "PowerPC64 (little endian)"
> select BR2_ARCH_IS_64
> - select BR2_ARCH_HAS_MMU_MANDATORY
> + select BR2_USE_MMU
> help
> PowerPC is a RISC architecture created by Apple-IBM-Motorola
> alliance. Little endian.
> @@ -210,7 +207,7 @@ config BR2_riscv
> config BR2_s390x
> bool "s390x"
> select BR2_ARCH_IS_64
> - select BR2_ARCH_HAS_MMU_MANDATORY
> + select BR2_USE_MMU
> help
> s390x is a big-endian architecture made by IBM.
> http://www.ibm.com/
> @@ -218,7 +215,7 @@ config BR2_s390x
>
> config BR2_sh
> bool "SuperH"
> - select BR2_ARCH_HAS_MMU_MANDATORY
> + select BR2_USE_MMU
> help
> SuperH (or SH) is a 32-bit reduced instruction set computer
> (RISC) instruction set architecture (ISA) developed by
> @@ -228,7 +225,7 @@ config BR2_sh
>
> config BR2_sparc
> bool "SPARC"
> - select BR2_ARCH_HAS_MMU_MANDATORY
> + select BR2_USE_MMU
> help
> SPARC (from Scalable Processor Architecture) is a RISC
> instruction set architecture (ISA) developed by Sun
> @@ -239,7 +236,7 @@ config BR2_sparc
> config BR2_sparc64
> bool "SPARC64"
> select BR2_ARCH_IS_64
> - select BR2_ARCH_HAS_MMU_MANDATORY
> + select BR2_USE_MMU
> help
> SPARC (from Scalable Processor Architecture) is a RISC
> instruction set architecture (ISA) developed by Sun
> @@ -250,7 +247,7 @@ config BR2_sparc64
> config BR2_x86_64
> bool "x86_64"
> select BR2_ARCH_IS_64
> - select BR2_ARCH_HAS_MMU_MANDATORY
> + select BR2_USE_MMU
> help
> x86-64 is an extension of the x86 instruction set (Intel i386
> architecture compatible microprocessor).
> diff --git a/arch/Config.in.arm b/arch/Config.in.arm
> index eb71d70430..15f96c4239 100644
> --- a/arch/Config.in.arm
> +++ b/arch/Config.in.arm
> @@ -73,26 +73,26 @@ config BR2_ARM_CPU_HAS_THUMB2
>
> config BR2_ARM_CPU_ARMV4
> bool
> - select BR2_ARCH_HAS_MMU_MANDATORY
> + select BR2_USE_MMU
>
> config BR2_ARM_CPU_ARMV5
> bool
> - select BR2_ARCH_HAS_MMU_MANDATORY
> + select BR2_USE_MMU
>
> config BR2_ARM_CPU_ARMV6
> bool
> - select BR2_ARCH_HAS_MMU_MANDATORY
> + select BR2_USE_MMU
>
> config BR2_ARM_CPU_ARMV7A
> bool
> - select BR2_ARCH_HAS_MMU_MANDATORY
> + select BR2_USE_MMU
>
> config BR2_ARM_CPU_ARMV7M
> bool
>
> config BR2_ARM_CPU_ARMV8A
> bool
> - select BR2_ARCH_HAS_MMU_MANDATORY
> + select BR2_USE_MMU
>
> choice
> prompt "Target Architecture Variant"
> diff --git a/arch/Config.in.m68k b/arch/Config.in.m68k
> index 1f7d944621..9fd22aaf1e 100644
> --- a/arch/Config.in.m68k
> +++ b/arch/Config.in.m68k
> @@ -26,7 +26,7 @@ choice
> config BR2_m68k_68040
> bool "68040"
> select BR2_m68k_m68k
> - select BR2_ARCH_HAS_MMU_MANDATORY
> + select BR2_USE_MMU
>
> config BR2_m68k_cf5208
> bool "5208"
> diff --git a/arch/Config.in.riscv b/arch/Config.in.riscv
> index 30bdcaa80b..b5e84389e0 100644
> --- a/arch/Config.in.riscv
> +++ b/arch/Config.in.riscv
> @@ -71,15 +71,23 @@ choice
>
> config BR2_RISCV_32
> bool "32-bit"
> - select BR2_ARCH_HAS_MMU_MANDATORY
> + select BR2_USE_MMU
>
> config BR2_RISCV_64
> bool "64-bit"
> select BR2_ARCH_IS_64
> - select BR2_ARCH_HAS_MMU_OPTIONAL
>
> endchoice
>
> +config BR2_RISCV_USE_MMU
> + bool "MMU support"
> + default y
> + depends on BR2_RISCV_64
> + select BR2_USE_MMU
> + help
> + Enable this option if your RISC-V core has a MMU (Memory
> + Management Unit).
> +
> choice
> prompt "Target ABI"
> default BR2_RISCV_ABI_ILP32D if !BR2_ARCH_IS_64 && BR2_RISCV_ISA_RVD
> diff --git a/arch/Config.in.xtensa b/arch/Config.in.xtensa
> index 45ad2dc487..f9d5adb4c9 100644
> --- a/arch/Config.in.xtensa
> +++ b/arch/Config.in.xtensa
> @@ -5,11 +5,10 @@ choice
>
> config BR2_XTENSA_CUSTOM
> bool "Custom Xtensa processor configuration"
> - select BR2_ARCH_HAS_MMU_OPTIONAL
>
> config BR2_xtensa_fsf
> bool "fsf - Default configuration"
> - select BR2_ARCH_HAS_MMU_MANDATORY
> + select BR2_USE_MMU
>
> endchoice
>
> @@ -41,6 +40,15 @@ config BR2_XTENSA_BIG_ENDIAN
>
> endchoice
>
> +config BR2_XTENSA_USE_MMU
> + bool "MMU support"
> + default y
> + depends on BR2_XTENSA_CUSTOM
> + select BR2_USE_MMU
> + help
> + Enable this option if your Xtensa core has a MMU (Memory
> + Management Unit).
> +
> config BR2_ENDIAN
> default "LITTLE" if BR2_XTENSA_LITTLE_ENDIAN
> default "BIG" if BR2_xtensa_fsf || BR2_XTENSA_BIG_ENDIAN
> diff --git a/configs/canaan_kd233_defconfig b/configs/canaan_kd233_defconfig
> index 85b7b14fbd..278fb883bf 100644
> --- a/configs/canaan_kd233_defconfig
> +++ b/configs/canaan_kd233_defconfig
> @@ -7,13 +7,13 @@ BR2_RISCV_ISA_CUSTOM_RVA=y
> BR2_RISCV_ISA_CUSTOM_RVF=y
> BR2_RISCV_ISA_CUSTOM_RVD=y
> BR2_RISCV_ISA_CUSTOM_RVC=y
> +# BR2_RISCV_USE_MMU is not set
> BR2_RISCV_ABI_LP64D=y
>
> # Patches
> BR2_GLOBAL_PATCH_DIR="board/riscv/nommu/patches"
>
> # Binary format
> -# BR2_USE_MMU is not set
> BR2_BINFMT_FLAT=y
> BR2_BINFMT_FLAT_ONE=y
> # BR2_TARGET_ENABLE_ROOT_LOGIN is not set
> diff --git a/configs/qemu_riscv64_nommu_virt_defconfig b/configs/qemu_riscv64_nommu_virt_defconfig
> index 33fad50a3c..691cf31748 100644
> --- a/configs/qemu_riscv64_nommu_virt_defconfig
> +++ b/configs/qemu_riscv64_nommu_virt_defconfig
> @@ -1,13 +1,11 @@
> # Architecture
> BR2_riscv=y
> BR2_RISCV_64=y
> +# BR2_RISCV_USE_MMU is not set
>
> # Patches
> BR2_GLOBAL_PATCH_DIR="board/riscv/nommu/patches"
>
> -# Toolchain
> -# BR2_USE_MMU is not set
> -
> # Busybox with hush
> BR2_PACKAGE_BUSYBOX_CONFIG="package/busybox/busybox-minimal.config"
>
> diff --git a/configs/qemu_xtensa_lx60_nommu_defconfig b/configs/qemu_xtensa_lx60_nommu_defconfig
> index f107b7e73b..4be1b66edc 100644
> --- a/configs/qemu_xtensa_lx60_nommu_defconfig
> +++ b/configs/qemu_xtensa_lx60_nommu_defconfig
> @@ -2,9 +2,7 @@
> BR2_xtensa=y
> BR2_XTENSA_CUSTOM=y
> BR2_XTENSA_OVERLAY_FILE="https://github.com/jcmvbkbc/xtensa-toolchain-build/raw/95291b7c39e6f790d0b2f062c945a630290f2c81/overlays/xtensa_dc233c.tar.gz"
> -
> -# Toolchain
> -# BR2_USE_MMU is not set
> +# BR2_XTENSA_USE_MMU is not set
>
> # Use minimal busybox with hush and networking tools
> BR2_PACKAGE_BUSYBOX_CONFIG="package/busybox/busybox-minimal.config"
> diff --git a/configs/sipeed_maix_bit_defconfig b/configs/sipeed_maix_bit_defconfig
> index dbc5af4e74..b31bc1309b 100644
> --- a/configs/sipeed_maix_bit_defconfig
> +++ b/configs/sipeed_maix_bit_defconfig
> @@ -7,13 +7,13 @@ BR2_RISCV_ISA_CUSTOM_RVA=y
> BR2_RISCV_ISA_CUSTOM_RVF=y
> BR2_RISCV_ISA_CUSTOM_RVD=y
> BR2_RISCV_ISA_CUSTOM_RVC=y
> +# BR2_RISCV_USE_MMU is not set
> BR2_RISCV_ABI_LP64D=y
>
> # Patches
> BR2_GLOBAL_PATCH_DIR="board/riscv/nommu/patches"
>
> # Binary format
> -# BR2_USE_MMU is not set
> BR2_BINFMT_FLAT=y
> BR2_BINFMT_FLAT_ONE=y
> # BR2_TARGET_ENABLE_ROOT_LOGIN is not set
> diff --git a/configs/sipeed_maix_bit_sdcard_defconfig b/configs/sipeed_maix_bit_sdcard_defconfig
> index 9f1c3a305f..4ad3b2e1db 100644
> --- a/configs/sipeed_maix_bit_sdcard_defconfig
> +++ b/configs/sipeed_maix_bit_sdcard_defconfig
> @@ -7,13 +7,13 @@ BR2_RISCV_ISA_CUSTOM_RVA=y
> BR2_RISCV_ISA_CUSTOM_RVF=y
> BR2_RISCV_ISA_CUSTOM_RVD=y
> BR2_RISCV_ISA_CUSTOM_RVC=y
> +# BR2_RISCV_USE_MMU is not set
> BR2_RISCV_ABI_LP64D=y
>
> # Patches
> BR2_GLOBAL_PATCH_DIR="board/riscv/nommu/patches"
>
> # System
> -# BR2_USE_MMU is not set
> BR2_BINFMT_FLAT=y
> BR2_BINFMT_FLAT_ONE=y
> # BR2_TARGET_ENABLE_ROOT_LOGIN is not set
> diff --git a/configs/sipeed_maix_dock_defconfig b/configs/sipeed_maix_dock_defconfig
> index 0f30e8d38f..d071e5d380 100644
> --- a/configs/sipeed_maix_dock_defconfig
> +++ b/configs/sipeed_maix_dock_defconfig
> @@ -7,13 +7,13 @@ BR2_RISCV_ISA_CUSTOM_RVA=y
> BR2_RISCV_ISA_CUSTOM_RVF=y
> BR2_RISCV_ISA_CUSTOM_RVD=y
> BR2_RISCV_ISA_CUSTOM_RVC=y
> +# BR2_RISCV_USE_MMU is not set
> BR2_RISCV_ABI_LP64D=y
>
> # Patches
> BR2_GLOBAL_PATCH_DIR="board/riscv/nommu/patches"
>
> # Binary format
> -# BR2_USE_MMU is not set
> BR2_BINFMT_FLAT=y
> BR2_BINFMT_FLAT_ONE=y
> # BR2_TARGET_ENABLE_ROOT_LOGIN is not set
> diff --git a/configs/sipeed_maix_dock_sdcard_defconfig b/configs/sipeed_maix_dock_sdcard_defconfig
> index fdbca11590..de79ff950b 100644
> --- a/configs/sipeed_maix_dock_sdcard_defconfig
> +++ b/configs/sipeed_maix_dock_sdcard_defconfig
> @@ -7,13 +7,13 @@ BR2_RISCV_ISA_CUSTOM_RVA=y
> BR2_RISCV_ISA_CUSTOM_RVF=y
> BR2_RISCV_ISA_CUSTOM_RVD=y
> BR2_RISCV_ISA_CUSTOM_RVC=y
> +# BR2_RISCV_USE_MMU is not set
> BR2_RISCV_ABI_LP64D=y
>
> # Patches
> BR2_GLOBAL_PATCH_DIR="board/riscv/nommu/patches"
>
> # System
> -# BR2_USE_MMU is not set
> BR2_BINFMT_FLAT=y
> BR2_BINFMT_FLAT_ONE=y
> # BR2_TARGET_ENABLE_ROOT_LOGIN is not set
> diff --git a/configs/sipeed_maix_go_defconfig b/configs/sipeed_maix_go_defconfig
> index 2054e49ae2..3055379db4 100644
> --- a/configs/sipeed_maix_go_defconfig
> +++ b/configs/sipeed_maix_go_defconfig
> @@ -7,13 +7,13 @@ BR2_RISCV_ISA_CUSTOM_RVA=y
> BR2_RISCV_ISA_CUSTOM_RVF=y
> BR2_RISCV_ISA_CUSTOM_RVD=y
> BR2_RISCV_ISA_CUSTOM_RVC=y
> +# BR2_RISCV_USE_MMU is not set
> BR2_RISCV_ABI_LP64D=y
>
> # Patches
> BR2_GLOBAL_PATCH_DIR="board/riscv/nommu/patches"
>
> # Binary format
> -# BR2_USE_MMU is not set
> BR2_BINFMT_FLAT=y
> BR2_BINFMT_FLAT_ONE=y
> # BR2_TARGET_ENABLE_ROOT_LOGIN is not set
> diff --git a/configs/sipeed_maix_go_sdcard_defconfig b/configs/sipeed_maix_go_sdcard_defconfig
> index a16943608c..7338b0c09d 100644
> --- a/configs/sipeed_maix_go_sdcard_defconfig
> +++ b/configs/sipeed_maix_go_sdcard_defconfig
> @@ -7,13 +7,13 @@ BR2_RISCV_ISA_CUSTOM_RVA=y
> BR2_RISCV_ISA_CUSTOM_RVF=y
> BR2_RISCV_ISA_CUSTOM_RVD=y
> BR2_RISCV_ISA_CUSTOM_RVC=y
> +# BR2_RISCV_USE_MMU is not set
> BR2_RISCV_ABI_LP64D=y
>
> # Patches
> BR2_GLOBAL_PATCH_DIR="board/riscv/nommu/patches"
>
> # System
> -# BR2_USE_MMU is not set
> BR2_BINFMT_FLAT=y
> BR2_BINFMT_FLAT_ONE=y
> # BR2_TARGET_ENABLE_ROOT_LOGIN is not set
> diff --git a/configs/sipeed_maixduino_defconfig b/configs/sipeed_maixduino_defconfig
> index a581ecbea5..50c59bd4ad 100644
> --- a/configs/sipeed_maixduino_defconfig
> +++ b/configs/sipeed_maixduino_defconfig
> @@ -7,13 +7,13 @@ BR2_RISCV_ISA_CUSTOM_RVA=y
> BR2_RISCV_ISA_CUSTOM_RVF=y
> BR2_RISCV_ISA_CUSTOM_RVD=y
> BR2_RISCV_ISA_CUSTOM_RVC=y
> +# BR2_RISCV_USE_MMU is not set
> BR2_RISCV_ABI_LP64D=y
>
> # Patches
> BR2_GLOBAL_PATCH_DIR="board/riscv/nommu/patches"
>
> # Binary format
> -# BR2_USE_MMU is not set
> BR2_BINFMT_FLAT=y
> BR2_BINFMT_FLAT_ONE=y
> # BR2_TARGET_ENABLE_ROOT_LOGIN is not set
> diff --git a/configs/sipeed_maixduino_sdcard_defconfig b/configs/sipeed_maixduino_sdcard_defconfig
> index 7e627e5d15..b4f1994239 100644
> --- a/configs/sipeed_maixduino_sdcard_defconfig
> +++ b/configs/sipeed_maixduino_sdcard_defconfig
> @@ -7,13 +7,13 @@ BR2_RISCV_ISA_CUSTOM_RVA=y
> BR2_RISCV_ISA_CUSTOM_RVF=y
> BR2_RISCV_ISA_CUSTOM_RVD=y
> BR2_RISCV_ISA_CUSTOM_RVC=y
> +# BR2_RISCV_USE_MMU is not set
> BR2_RISCV_ABI_LP64D=y
>
> # Patches
> BR2_GLOBAL_PATCH_DIR="board/riscv/nommu/patches"
>
> # System
> -# BR2_USE_MMU is not set
> BR2_BINFMT_FLAT=y
> BR2_BINFMT_FLAT_ONE=y
> # BR2_TARGET_ENABLE_ROOT_LOGIN is not set
> diff --git a/toolchain/Config.in b/toolchain/Config.in
> index e6fabbfc74..5f79c07df0 100644
> --- a/toolchain/Config.in
> +++ b/toolchain/Config.in
> @@ -315,13 +315,6 @@ config BR2_TOOLCHAIN_EXTRA_LIBS
> config BR2_TOOLCHAIN_HAS_FULL_GETTEXT
> bool
>
> -config BR2_USE_MMU
> - bool "Enable MMU support" if BR2_ARCH_HAS_MMU_OPTIONAL
> - default y if BR2_ARCH_HAS_MMU_OPTIONAL || BR2_ARCH_HAS_MMU_MANDATORY
> - help
> - If your target has a MMU, you should say Y here. If you
> - are unsure, just say Y.
> -
> config BR2_TARGET_OPTIMIZATION
> string "Target Optimizations"
> default ""
> --
> 2.37.1
>
> _______________________________________________
> buildroot mailing list
> buildroot@buildroot.org
> https://lists.buildroot.org/mailman/listinfo/buildroot
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next prev parent reply other threads:[~2022-07-27 9:43 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-07-26 16:39 [Buildroot] [PATCH v2 1/4] arch/Config.in.riscv: lp64f ABI is only supported if MMU is enabled Thomas Petazzoni via buildroot
2022-07-26 16:39 ` [Buildroot] [PATCH v2 2/4] package/Makefile.in: add detection for the lack of C library Thomas Petazzoni via buildroot
2022-07-27 7:58 ` Yann E. MORIN
2022-07-27 8:24 ` Thomas Petazzoni via buildroot
2022-08-29 20:15 ` Peter Korsgaard
2022-07-26 16:39 ` [Buildroot] [PATCH v2 3/4] arch/Config.in: move the binary format selection further down Thomas Petazzoni via buildroot
2022-07-27 7:58 ` Yann E. MORIN
2022-07-26 16:39 ` [Buildroot] [PATCH v2 4/4] arch: rework MMU option handling and move to "Target architecture" menu Thomas Petazzoni via buildroot
2022-07-27 7:03 ` Damien Le Moal via buildroot
2022-07-27 8:30 ` Yann E. MORIN
2022-07-27 9:22 ` Thomas Petazzoni via buildroot
2022-07-27 9:35 ` Yann E. MORIN
2022-07-27 9:43 ` Yann E. MORIN [this message]
2022-07-27 9:55 ` Thomas Petazzoni via buildroot
2022-07-27 7:57 ` [Buildroot] [PATCH v2 1/4] arch/Config.in.riscv: lp64f ABI is only supported if MMU is enabled Yann E. MORIN
2022-08-29 20:13 ` Peter Korsgaard
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