[Buildroot] [PATCH 1/2] package/llvm: Support for RISC-V on the LLVM package

[Buildroot] [PATCH 1/2] package/llvm: Support for RISC-V on the LLVM package

[Abel Bernabeu]

[-- Attachment #1.1: Type: text/plain, Size: 2565 bytes --]

From 254bc67341f9180a1068551a5beeeaab0be06301 Mon Sep 17 00:00:00 2001
From: Abel Bernabeu <abel@x-silicon.com>
Date: Mon, 4 Jul 2022 00:32:47 +0200
Subject: [PATCH 1/2] package/llvm: Support for RISC-V on the LLVM package

The initial support for the LLVM package did not include RISC-V, and
needed to be added.

There is a new configuration parameter added
(BR2_PACKAGE_LLVM_TARGETS_TO_BUILD) for dealing with the fact that
the LLVM target and the architecture have different naming for RISC-V.
While the target for RISC-V is "RISCV" irrespective of the ISA being
32 or 64 bits, the architecture does contain the number of bits
leading to "riscv32" and "riscv64".

For previously supported architectures the naming for target and
architecture matched and thus this parameter had not been needed, but
it is now needed for RISC-V.
---
 package/llvm/Config.in | 10 ++++++++++
 package/llvm/llvm.mk   |  2 +-
 2 files changed, 11 insertions(+), 1 deletion(-)

diff --git a/package/llvm/Config.in b/package/llvm/Config.in
index c1887e36dd..5f2864b802 100644
--- a/package/llvm/Config.in
+++ b/package/llvm/Config.in
@@ -4,12 +4,22 @@ config BR2_PACKAGE_LLVM_ARCH_SUPPORTS
        default y if BR2_x86_64
        default y if BR2_aarch64
        default y if BR2_arm || BR2_armeb
+       default y if BR2_riscv

 config BR2_PACKAGE_LLVM_TARGET_ARCH
        string
        default "AArch64" if BR2_aarch64
        default "ARM" if BR2_arm || BR2_armeb
        default "X86" if BR2_i386 || BR2_x86_64
+       default "riscv32" if BR2_riscv && !BR2_ARCH_IS_64
+        default "riscv64" if BR2_riscv && BR2_ARCH_IS_64
+
+config BR2_PACKAGE_LLVM_TARGETS_TO_BUILD
+       string
+       default "AArch64" if BR2_aarch64
+       default "ARM" if BR2_arm || BR2_armeb
+       default "X86" if BR2_i386 || BR2_x86_64
+       default "RISCV" if BR2_riscv

 config BR2_PACKAGE_LLVM
        bool "llvm"
diff --git a/package/llvm/llvm.mk b/package/llvm/llvm.mk
index 4670773ca3..dbf1f7b813 100644
--- a/package/llvm/llvm.mk
+++ b/package/llvm/llvm.mk
@@ -42,7 +42,7 @@ HOST_LLVM_CONF_OPTS +=
-DCMAKE_INSTALL_RPATH="$(HOST_DIR)/lib"
 LLVM_TARGET_ARCH = $(call qstrip,$(BR2_PACKAGE_LLVM_TARGET_ARCH))

 # Build backend for target architecture. This include backends like AMDGPU.
-LLVM_TARGETS_TO_BUILD = $(LLVM_TARGET_ARCH)
+LLVM_TARGETS_TO_BUILD = $(BR2_PACKAGE_LLVM_TARGETS_TO_BUILD)
 HOST_LLVM_CONF_OPTS += -DLLVM_TARGETS_TO_BUILD="$(subst
$(space),;,$(LLVM_TARGETS_TO_BUILD))"
 LLVM_CONF_OPTS += -DLLVM_TARGETS_TO_BUILD="$(subst
$(space),;,$(LLVM_TARGETS_TO_BUILD))"

-- 
2.25.1

[-- Attachment #1.2: Type: text/html, Size: 3226 bytes --]

[-- Attachment #2: Type: text/plain, Size: 150 bytes --]

_______________________________________________
buildroot mailing list
buildroot@buildroot.org
https://lists.buildroot.org/mailman/listinfo/buildroot

[Buildroot] [PATCH 1/2] package/llvm: Support for RISC-V on the LLVM package

[Abel Bernabeu]

The initial support for the LLVM package did not include RISC-V, and
needed to be added.

There is a new configuration parameter added
(BR2_PACKAGE_LLVM_TARGETS_TO_BUILD) for dealing with the fact that
the LLVM target and the architecture have different naming for RISC-V.
While the target for RISC-V is "RISCV" irrespective of the ISA being
32 or 64 bits, the architecture does contain the number of bits
leading to "riscv32" and "riscv64".

For previously supported architectures the naming for target and
architecture matched and thus this parameter had not been needed, but
it is now needed for RISC-V.

Signed-off-by: Abel Bernabeu <abel@x-silicon.com>
---
 package/llvm/Config.in | 10 ++++++++++
 package/llvm/llvm.mk   |  2 +-
 2 files changed, 11 insertions(+), 1 deletion(-)

diff --git a/package/llvm/Config.in b/package/llvm/Config.in
index c1887e36dd..5f2864b802 100644
--- a/package/llvm/Config.in
+++ b/package/llvm/Config.in
@@ -4,12 +4,22 @@ config BR2_PACKAGE_LLVM_ARCH_SUPPORTS
 	default y if BR2_x86_64
 	default y if BR2_aarch64
 	default y if BR2_arm || BR2_armeb
+	default y if BR2_riscv
 
 config BR2_PACKAGE_LLVM_TARGET_ARCH
 	string
 	default "AArch64" if BR2_aarch64
 	default "ARM" if BR2_arm || BR2_armeb
 	default "X86" if BR2_i386 || BR2_x86_64
+	default "riscv32" if BR2_riscv && !BR2_ARCH_IS_64
+        default "riscv64" if BR2_riscv && BR2_ARCH_IS_64
+
+config BR2_PACKAGE_LLVM_TARGETS_TO_BUILD
+	string
+	default "AArch64" if BR2_aarch64
+	default "ARM" if BR2_arm || BR2_armeb
+	default "X86" if BR2_i386 || BR2_x86_64
+	default "RISCV" if BR2_riscv
 
 config BR2_PACKAGE_LLVM
 	bool "llvm"
diff --git a/package/llvm/llvm.mk b/package/llvm/llvm.mk
index 4670773ca3..dbf1f7b813 100644
--- a/package/llvm/llvm.mk
+++ b/package/llvm/llvm.mk
@@ -42,7 +42,7 @@ HOST_LLVM_CONF_OPTS += -DCMAKE_INSTALL_RPATH="$(HOST_DIR)/lib"
 LLVM_TARGET_ARCH = $(call qstrip,$(BR2_PACKAGE_LLVM_TARGET_ARCH))
 
 # Build backend for target architecture. This include backends like AMDGPU.
-LLVM_TARGETS_TO_BUILD = $(LLVM_TARGET_ARCH)
+LLVM_TARGETS_TO_BUILD = $(BR2_PACKAGE_LLVM_TARGETS_TO_BUILD)
 HOST_LLVM_CONF_OPTS += -DLLVM_TARGETS_TO_BUILD="$(subst $(space),;,$(LLVM_TARGETS_TO_BUILD))"
 LLVM_CONF_OPTS += -DLLVM_TARGETS_TO_BUILD="$(subst $(space),;,$(LLVM_TARGETS_TO_BUILD))"
 
-- 
2.34.1

_______________________________________________
buildroot mailing list
buildroot@buildroot.org
https://lists.buildroot.org/mailman/listinfo/buildroot

Re: [Buildroot] [PATCH 1/2] package/llvm: Support for RISC-V on the LLVM package

[Romain Naour]

Hello Abel,

Le 04/07/2022 à 10:55, Abel Bernabeu a écrit :
> The initial support for the LLVM package did not include RISC-V, and
> needed to be added.

Indeed, at the time LLVM package was added to Buildroot there was no RISC-V
support yet.

> 
> There is a new configuration parameter added
> (BR2_PACKAGE_LLVM_TARGETS_TO_BUILD) for dealing with the fact that
> the LLVM target and the architecture have different naming for RISC-V.
> While the target for RISC-V is "RISCV" irrespective of the ISA being
> 32 or 64 bits, the architecture does contain the number of bits
> leading to "riscv32" and "riscv64".
> 
> For previously supported architectures the naming for target and
> architecture matched and thus this parameter had not been needed, but
> it is now needed for RISC-V.
> 
> Signed-off-by: Abel Bernabeu <abel@x-silicon.com>
> ---
>  package/llvm/Config.in | 10 ++++++++++
>  package/llvm/llvm.mk   |  2 +-
>  2 files changed, 11 insertions(+), 1 deletion(-)
> 
> diff --git a/package/llvm/Config.in b/package/llvm/Config.in
> index c1887e36dd..5f2864b802 100644
> --- a/package/llvm/Config.in
> +++ b/package/llvm/Config.in
> @@ -4,12 +4,22 @@ config BR2_PACKAGE_LLVM_ARCH_SUPPORTS
>  	default y if BR2_x86_64
>  	default y if BR2_aarch64
>  	default y if BR2_arm || BR2_armeb
> +	default y if BR2_riscv
>  
>  config BR2_PACKAGE_LLVM_TARGET_ARCH
>  	string
>  	default "AArch64" if BR2_aarch64
>  	default "ARM" if BR2_arm || BR2_armeb
>  	default "X86" if BR2_i386 || BR2_x86_64
> +	default "riscv32" if BR2_riscv && !BR2_ARCH_IS_64
> +        default "riscv64" if BR2_riscv && BR2_ARCH_IS_64

Indentation issue, please use one tab.

> +
> +config BR2_PACKAGE_LLVM_TARGETS_TO_BUILD
> +	string
> +	default "AArch64" if BR2_aarch64
> +	default "ARM" if BR2_arm || BR2_armeb
> +	default "X86" if BR2_i386 || BR2_x86_64
> +	default "RISCV" if BR2_riscv

Having to duplicate BR2_PACKAGE_LLVM_TARGET_ARCH for the sake of one
architecture is a pity.

Maybe we can try to use $(subst ...) to replace riscv32|64 by RISCV but it's not
really a clean solution either....

Reviewed-by: Romain Naour <romain.naour@smile.fr>

Best regards,
Romain

>  
>  config BR2_PACKAGE_LLVM
>  	bool "llvm"
> diff --git a/package/llvm/llvm.mk b/package/llvm/llvm.mk
> index 4670773ca3..dbf1f7b813 100644
> --- a/package/llvm/llvm.mk
> +++ b/package/llvm/llvm.mk
> @@ -42,7 +42,7 @@ HOST_LLVM_CONF_OPTS += -DCMAKE_INSTALL_RPATH="$(HOST_DIR)/lib"
>  LLVM_TARGET_ARCH = $(call qstrip,$(BR2_PACKAGE_LLVM_TARGET_ARCH))
>  
>  # Build backend for target architecture. This include backends like AMDGPU.
> -LLVM_TARGETS_TO_BUILD = $(LLVM_TARGET_ARCH)
> +LLVM_TARGETS_TO_BUILD = $(BR2_PACKAGE_LLVM_TARGETS_TO_BUILD)
>  HOST_LLVM_CONF_OPTS += -DLLVM_TARGETS_TO_BUILD="$(subst $(space),;,$(LLVM_TARGETS_TO_BUILD))"
>  LLVM_CONF_OPTS += -DLLVM_TARGETS_TO_BUILD="$(subst $(space),;,$(LLVM_TARGETS_TO_BUILD))"
>  

_______________________________________________
buildroot mailing list
buildroot@buildroot.org
https://lists.buildroot.org/mailman/listinfo/buildroot

[Buildroot] [PATCH 1/2] package/llvm: Support for RISC-V on the LLVM package

[Abel Bernabeu]

The initial support for the LLVM package did not include RISC-V, and
needed to be added.

There is a new configuration parameter added
(BR2_PACKAGE_LLVM_TARGETS_TO_BUILD) for dealing with the fact that
the LLVM target and the architecture have different naming for RISC-V.
While the target for RISC-V is "RISCV" irrespective of the ISA being
32 or 64 bits, the architecture does contain the number of bits
leading to "riscv32" and "riscv64".

For previously supported architectures the naming for target and
architecture matched and thus this parameter had not been needed, but
it is now needed for RISC-V.

Signed-off-by: Abel Bernabeu <abel@x-silicon.com>
---
 package/llvm/Config.in | 10 ++++++++++
 package/llvm/llvm.mk   |  2 +-
 2 files changed, 11 insertions(+), 1 deletion(-)

diff --git a/package/llvm/Config.in b/package/llvm/Config.in
index c1887e36dd..61197fc588 100644
--- a/package/llvm/Config.in
+++ b/package/llvm/Config.in
@@ -4,12 +4,22 @@ config BR2_PACKAGE_LLVM_ARCH_SUPPORTS
 	default y if BR2_x86_64
 	default y if BR2_aarch64
 	default y if BR2_arm || BR2_armeb
+	default y if BR2_riscv
 
 config BR2_PACKAGE_LLVM_TARGET_ARCH
 	string
 	default "AArch64" if BR2_aarch64
 	default "ARM" if BR2_arm || BR2_armeb
 	default "X86" if BR2_i386 || BR2_x86_64
+	default "riscv32" if BR2_riscv && !BR2_ARCH_IS_64
+	default "riscv64" if BR2_riscv && BR2_ARCH_IS_64
+
+config BR2_PACKAGE_LLVM_TARGETS_TO_BUILD
+	string
+	default "AArch64" if BR2_aarch64
+	default "ARM" if BR2_arm || BR2_armeb
+	default "X86" if BR2_i386 || BR2_x86_64
+	default "RISCV" if BR2_riscv
 
 config BR2_PACKAGE_LLVM
 	bool "llvm"
diff --git a/package/llvm/llvm.mk b/package/llvm/llvm.mk
index 4670773ca3..dbf1f7b813 100644
--- a/package/llvm/llvm.mk
+++ b/package/llvm/llvm.mk
@@ -42,7 +42,7 @@ HOST_LLVM_CONF_OPTS += -DCMAKE_INSTALL_RPATH="$(HOST_DIR)/lib"
 LLVM_TARGET_ARCH = $(call qstrip,$(BR2_PACKAGE_LLVM_TARGET_ARCH))
 
 # Build backend for target architecture. This include backends like AMDGPU.
-LLVM_TARGETS_TO_BUILD = $(LLVM_TARGET_ARCH)
+LLVM_TARGETS_TO_BUILD = $(BR2_PACKAGE_LLVM_TARGETS_TO_BUILD)
 HOST_LLVM_CONF_OPTS += -DLLVM_TARGETS_TO_BUILD="$(subst $(space),;,$(LLVM_TARGETS_TO_BUILD))"
 LLVM_CONF_OPTS += -DLLVM_TARGETS_TO_BUILD="$(subst $(space),;,$(LLVM_TARGETS_TO_BUILD))"
 
-- 
2.34.1

_______________________________________________
buildroot mailing list
buildroot@buildroot.org
https://lists.buildroot.org/mailman/listinfo/buildroot

[Buildroot] [PATCH 2/2] arch/riscv: Added support for RISC-V vector extension on the architecture menu.

[Abel Bernabeu]

This new setting will allow to test new toolchains already available
that support the vector extension (more patches coming soon).

Signed-off-by: Abel Bernabeu <abel@x-silicon.com>
---
 arch/Config.in.riscv | 7 +++++++
 arch/arch.mk.riscv   | 4 ++++
 2 files changed, 11 insertions(+)

diff --git a/arch/Config.in.riscv b/arch/Config.in.riscv
index 288ed833eb..e4dc936cf8 100644
--- a/arch/Config.in.riscv
+++ b/arch/Config.in.riscv
@@ -18,6 +18,9 @@ config BR2_RISCV_ISA_RVD
 config BR2_RISCV_ISA_RVC
 	bool
 
+config BR2_RISCV_ISA_RVV
+	bool
+
 choice
 	prompt "Target Architecture Variant"
 	default BR2_riscv_g
@@ -63,6 +66,10 @@ config BR2_RISCV_ISA_CUSTOM_RVD
 config BR2_RISCV_ISA_CUSTOM_RVC
 	bool "Compressed Instructions (C)"
 	select BR2_RISCV_ISA_RVC
+
+config BR2_RISCV_ISA_CUSTOM_RVV
+	bool "Vector Instructions (V)"
+	select BR2_RISCV_ISA_RVV
 endif
 
 choice
diff --git a/arch/arch.mk.riscv b/arch/arch.mk.riscv
index f3bf2b3467..07a94aa6a4 100644
--- a/arch/arch.mk.riscv
+++ b/arch/arch.mk.riscv
@@ -26,5 +26,9 @@ endif
 ifeq ($(BR2_RISCV_ISA_RVC),y)
 GCC_TARGET_ARCH := $(GCC_TARGET_ARCH)c
 endif
+ifeq ($(BR2_RISCV_ISA_RVV),y)
+GCC_TARGET_ARCH := $(GCC_TARGET_ARCH)v
+endif
+
 
 endif
-- 
2.34.1

_______________________________________________
buildroot mailing list
buildroot@buildroot.org
https://lists.buildroot.org/mailman/listinfo/buildroot

Re: [Buildroot] [PATCH 2/2] arch/riscv: Added support for RISC-V vector extension on the architecture menu.

[Romain Naour]

Hello Abel,

Le 23/07/2022 à 23:54, Abel Bernabeu a écrit :
> This new setting will allow to test new toolchains already available
> that support the vector extension (more patches coming soon).

It seems that is the same series as v1:

http://patchwork.ozlabs.org/project/buildroot/list/?series=307848&state=*

See 22.5.5. "Patch revision changelog" section for help.

https://nightly.buildroot.org/manual.html#submitting-patches

> 
> Signed-off-by: Abel Bernabeu <abel@x-silicon.com>
> ---
>  arch/Config.in.riscv | 7 +++++++
>  arch/arch.mk.riscv   | 4 ++++
>  2 files changed, 11 insertions(+)
> 
> diff --git a/arch/Config.in.riscv b/arch/Config.in.riscv
> index 288ed833eb..e4dc936cf8 100644
> --- a/arch/Config.in.riscv
> +++ b/arch/Config.in.riscv
> @@ -18,6 +18,9 @@ config BR2_RISCV_ISA_RVD
>  config BR2_RISCV_ISA_RVC
>  	bool
>  
> +config BR2_RISCV_ISA_RVV
> +	bool
> +
>  choice
>  	prompt "Target Architecture Variant"
>  	default BR2_riscv_g
> @@ -63,6 +66,10 @@ config BR2_RISCV_ISA_CUSTOM_RVD
>  config BR2_RISCV_ISA_CUSTOM_RVC
>  	bool "Compressed Instructions (C)"
>  	select BR2_RISCV_ISA_RVC
> +
> +config BR2_RISCV_ISA_CUSTOM_RVV

This option must depends on gcc-12.

Best regards,
Romain

> +	bool "Vector Instructions (V)"
> +	select BR2_RISCV_ISA_RVV
>  endif
>  
>  choice
> diff --git a/arch/arch.mk.riscv b/arch/arch.mk.riscv
> index f3bf2b3467..07a94aa6a4 100644
> --- a/arch/arch.mk.riscv
> +++ b/arch/arch.mk.riscv
> @@ -26,5 +26,9 @@ endif
>  ifeq ($(BR2_RISCV_ISA_RVC),y)
>  GCC_TARGET_ARCH := $(GCC_TARGET_ARCH)c
>  endif
> +ifeq ($(BR2_RISCV_ISA_RVV),y)
> +GCC_TARGET_ARCH := $(GCC_TARGET_ARCH)v
> +endif
> +
>  
>  endif

_______________________________________________
buildroot mailing list
buildroot@buildroot.org
https://lists.buildroot.org/mailman/listinfo/buildroot

Re: [Buildroot] [PATCH 2/2] arch/riscv: Added support for RISC-V vector extension on the architecture menu.

[Arnout Vandecappelle]

On 24/07/2022 10:08, Romain Naour wrote:
> Hello Abel,
> 
> Le 23/07/2022 à 23:54, Abel Bernabeu a écrit :
>> This new setting will allow to test new toolchains already available
>> that support the vector extension (more patches coming soon).
> 
> It seems that is the same series as v1:
> 
> http://patchwork.ozlabs.org/project/buildroot/list/?series=307848&state=*
> 
> See 22.5.5. "Patch revision changelog" section for help.
> 
> https://nightly.buildroot.org/manual.html#submitting-patches
> 
>>
>> Signed-off-by: Abel Bernabeu <abel@x-silicon.com>
>> ---
>>   arch/Config.in.riscv | 7 +++++++
>>   arch/arch.mk.riscv   | 4 ++++
>>   2 files changed, 11 insertions(+)
>>
>> diff --git a/arch/Config.in.riscv b/arch/Config.in.riscv
>> index 288ed833eb..e4dc936cf8 100644
>> --- a/arch/Config.in.riscv
>> +++ b/arch/Config.in.riscv
>> @@ -18,6 +18,9 @@ config BR2_RISCV_ISA_RVD
>>   config BR2_RISCV_ISA_RVC
>>   	bool
>>   
>> +config BR2_RISCV_ISA_RVV
>> +	bool
>> +
>>   choice
>>   	prompt "Target Architecture Variant"
>>   	default BR2_riscv_g
>> @@ -63,6 +66,10 @@ config BR2_RISCV_ISA_CUSTOM_RVD
>>   config BR2_RISCV_ISA_CUSTOM_RVC
>>   	bool "Compressed Instructions (C)"
>>   	select BR2_RISCV_ISA_RVC
>> +
>> +config BR2_RISCV_ISA_CUSTOM_RVV
> 
> This option must depends on gcc-12.

  No, it's the other way round: it should force GCC 12, by selecting 
BR2_ARCH_NEEDS_GCC_AT_LEAST_12.

  Regards,
  Arnout

> 
> Best regards,
> Romain
> 
>> +	bool "Vector Instructions (V)"
>> +	select BR2_RISCV_ISA_RVV
>>   endif
>>   
>>   choice
>> diff --git a/arch/arch.mk.riscv b/arch/arch.mk.riscv
>> index f3bf2b3467..07a94aa6a4 100644
>> --- a/arch/arch.mk.riscv
>> +++ b/arch/arch.mk.riscv
>> @@ -26,5 +26,9 @@ endif
>>   ifeq ($(BR2_RISCV_ISA_RVC),y)
>>   GCC_TARGET_ARCH := $(GCC_TARGET_ARCH)c
>>   endif
>> +ifeq ($(BR2_RISCV_ISA_RVV),y)
>> +GCC_TARGET_ARCH := $(GCC_TARGET_ARCH)v
>> +endif
>> +
>>   
>>   endif
> 
> _______________________________________________
> buildroot mailing list
> buildroot@buildroot.org
> https://lists.buildroot.org/mailman/listinfo/buildroot
_______________________________________________
buildroot mailing list
buildroot@buildroot.org
https://lists.buildroot.org/mailman/listinfo/buildroot

Re: [Buildroot] [PATCH 2/2] arch/riscv: Added support for RISC-V vector extension on the architecture menu.

[Romain Naour]

Le 24/07/2022 à 11:25, Arnout Vandecappelle a écrit :
> 
> 
> On 24/07/2022 10:08, Romain Naour wrote:
>> Hello Abel,
>>
>> Le 23/07/2022 à 23:54, Abel Bernabeu a écrit :
>>> This new setting will allow to test new toolchains already available
>>> that support the vector extension (more patches coming soon).
>>
>> It seems that is the same series as v1:
>>
>> http://patchwork.ozlabs.org/project/buildroot/list/?series=307848&state=*
>>
>> See 22.5.5. "Patch revision changelog" section for help.
>>
>> https://nightly.buildroot.org/manual.html#submitting-patches
>>
>>>
>>> Signed-off-by: Abel Bernabeu <abel@x-silicon.com>
>>> ---
>>>   arch/Config.in.riscv | 7 +++++++
>>>   arch/arch.mk.riscv   | 4 ++++
>>>   2 files changed, 11 insertions(+)
>>>
>>> diff --git a/arch/Config.in.riscv b/arch/Config.in.riscv
>>> index 288ed833eb..e4dc936cf8 100644
>>> --- a/arch/Config.in.riscv
>>> +++ b/arch/Config.in.riscv
>>> @@ -18,6 +18,9 @@ config BR2_RISCV_ISA_RVD
>>>   config BR2_RISCV_ISA_RVC
>>>       bool
>>>   +config BR2_RISCV_ISA_RVV
>>> +    bool
>>> +
>>>   choice
>>>       prompt "Target Architecture Variant"
>>>       default BR2_riscv_g
>>> @@ -63,6 +66,10 @@ config BR2_RISCV_ISA_CUSTOM_RVD
>>>   config BR2_RISCV_ISA_CUSTOM_RVC
>>>       bool "Compressed Instructions (C)"
>>>       select BR2_RISCV_ISA_RVC
>>> +
>>> +config BR2_RISCV_ISA_CUSTOM_RVV
>>
>> This option must depends on gcc-12.
> 
>  No, it's the other way round: it should force GCC 12, by selecting
> BR2_ARCH_NEEDS_GCC_AT_LEAST_12.

Indeed, Thomas commented on this yesterday [1]

[1] http://lists.busybox.net/pipermail/buildroot/2022-July/646698.html

Best regards,
Romain


> 
>  Regards,
>  Arnout
> 
>>
>> Best regards,
>> Romain
>>
>>> +    bool "Vector Instructions (V)"
>>> +    select BR2_RISCV_ISA_RVV
>>>   endif
>>>     choice
>>> diff --git a/arch/arch.mk.riscv b/arch/arch.mk.riscv
>>> index f3bf2b3467..07a94aa6a4 100644
>>> --- a/arch/arch.mk.riscv
>>> +++ b/arch/arch.mk.riscv
>>> @@ -26,5 +26,9 @@ endif
>>>   ifeq ($(BR2_RISCV_ISA_RVC),y)
>>>   GCC_TARGET_ARCH := $(GCC_TARGET_ARCH)c
>>>   endif
>>> +ifeq ($(BR2_RISCV_ISA_RVV),y)
>>> +GCC_TARGET_ARCH := $(GCC_TARGET_ARCH)v
>>> +endif
>>> +
>>>     endif
>>
>> _______________________________________________
>> buildroot mailing list
>> buildroot@buildroot.org
>> https://lists.buildroot.org/mailman/listinfo/buildroot

_______________________________________________
buildroot mailing list
buildroot@buildroot.org
https://lists.buildroot.org/mailman/listinfo/buildroot

Re: [Buildroot] [PATCH 2/2] arch/riscv: Added support for RISC-V vector extension on the architecture menu.

[Abel Bernabeu]

[-- Attachment #1.1: Type: text/plain, Size: 2801 bytes --]

Thanks, will do as suggested (forcing GCC 12 or newer when using the
option).

On Sun, Jul 24, 2022, 11:52 AM Romain Naour <romain.naour@smile.fr> wrote:

> Le 24/07/2022 à 11:25, Arnout Vandecappelle a écrit :
> >
> >
> > On 24/07/2022 10:08, Romain Naour wrote:
> >> Hello Abel,
> >>
> >> Le 23/07/2022 à 23:54, Abel Bernabeu a écrit :
> >>> This new setting will allow to test new toolchains already available
> >>> that support the vector extension (more patches coming soon).
> >>
> >> It seems that is the same series as v1:
> >>
> >>
> http://patchwork.ozlabs.org/project/buildroot/list/?series=307848&state=*
> >>
> >> See 22.5.5. "Patch revision changelog" section for help.
> >>
> >> https://nightly.buildroot.org/manual.html#submitting-patches
> >>
> >>>
> >>> Signed-off-by: Abel Bernabeu <abel@x-silicon.com>
> >>> ---
> >>>   arch/Config.in.riscv | 7 +++++++
> >>>   arch/arch.mk.riscv   | 4 ++++
> >>>   2 files changed, 11 insertions(+)
> >>>
> >>> diff --git a/arch/Config.in.riscv b/arch/Config.in.riscv
> >>> index 288ed833eb..e4dc936cf8 100644
> >>> --- a/arch/Config.in.riscv
> >>> +++ b/arch/Config.in.riscv
> >>> @@ -18,6 +18,9 @@ config BR2_RISCV_ISA_RVD
> >>>   config BR2_RISCV_ISA_RVC
> >>>       bool
> >>>   +config BR2_RISCV_ISA_RVV
> >>> +    bool
> >>> +
> >>>   choice
> >>>       prompt "Target Architecture Variant"
> >>>       default BR2_riscv_g
> >>> @@ -63,6 +66,10 @@ config BR2_RISCV_ISA_CUSTOM_RVD
> >>>   config BR2_RISCV_ISA_CUSTOM_RVC
> >>>       bool "Compressed Instructions (C)"
> >>>       select BR2_RISCV_ISA_RVC
> >>> +
> >>> +config BR2_RISCV_ISA_CUSTOM_RVV
> >>
> >> This option must depends on gcc-12.
> >
> >  No, it's the other way round: it should force GCC 12, by selecting
> > BR2_ARCH_NEEDS_GCC_AT_LEAST_12.
>
> Indeed, Thomas commented on this yesterday [1]
>
> [1] http://lists.busybox.net/pipermail/buildroot/2022-July/646698.html
>
> Best regards,
> Romain
>
>
> >
> >  Regards,
> >  Arnout
> >
> >>
> >> Best regards,
> >> Romain
> >>
> >>> +    bool "Vector Instructions (V)"
> >>> +    select BR2_RISCV_ISA_RVV
> >>>   endif
> >>>     choice
> >>> diff --git a/arch/arch.mk.riscv b/arch/arch.mk.riscv
> >>> index f3bf2b3467..07a94aa6a4 100644
> >>> --- a/arch/arch.mk.riscv
> >>> +++ b/arch/arch.mk.riscv
> >>> @@ -26,5 +26,9 @@ endif
> >>>   ifeq ($(BR2_RISCV_ISA_RVC),y)
> >>>   GCC_TARGET_ARCH := $(GCC_TARGET_ARCH)c
> >>>   endif
> >>> +ifeq ($(BR2_RISCV_ISA_RVV),y)
> >>> +GCC_TARGET_ARCH := $(GCC_TARGET_ARCH)v
> >>> +endif
> >>> +
> >>>     endif
> >>
> >> _______________________________________________
> >> buildroot mailing list
> >> buildroot@buildroot.org
> >> https://lists.buildroot.org/mailman/listinfo/buildroot
>
>

[-- Attachment #1.2: Type: text/html, Size: 4569 bytes --]

[-- Attachment #2: Type: text/plain, Size: 150 bytes --]

_______________________________________________
buildroot mailing list
buildroot@buildroot.org
https://lists.buildroot.org/mailman/listinfo/buildroot

Re: [Buildroot] [PATCH 1/2] package/llvm: Support for RISC-V on the LLVM package

[Thomas Petazzoni via buildroot]

On Sat, 23 Jul 2022 23:54:47 +0200
Abel Bernabeu <abel@x-silicon.com> wrote:

> The initial support for the LLVM package did not include RISC-V, and
> needed to be added.
> 
> There is a new configuration parameter added
> (BR2_PACKAGE_LLVM_TARGETS_TO_BUILD) for dealing with the fact that
> the LLVM target and the architecture have different naming for RISC-V.
> While the target for RISC-V is "RISCV" irrespective of the ISA being
> 32 or 64 bits, the architecture does contain the number of bits
> leading to "riscv32" and "riscv64".
> 
> For previously supported architectures the naming for target and
> architecture matched and thus this parameter had not been needed, but
> it is now needed for RISC-V.
> 
> Signed-off-by: Abel Bernabeu <abel@x-silicon.com>
> ---
>  package/llvm/Config.in | 10 ++++++++++
>  package/llvm/llvm.mk   |  2 +-
>  2 files changed, 11 insertions(+), 1 deletion(-)

I have simplified the RISCV quirk by moving it to the llvm.mk file:

# Build backend for target architecture. This include backends like
# AMDGPU. We need to special case RISCV.
ifneq ($(filter riscv%,$(LLVM_TARGET_ARCH)),)
LLVM_TARGETS_TO_BUILD = RISCV
else
LLVM_TARGETS_TO_BUILD = $(LLVM_TARGET_ARCH)
endif

Applied with this change, thanks!

Thomas
-- 
Thomas Petazzoni, CTO, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
_______________________________________________
buildroot mailing list
buildroot@buildroot.org
https://lists.buildroot.org/mailman/listinfo/buildroot

Re: [Buildroot] [PATCH 1/2] package/llvm: Support for RISC-V on the LLVM package

[Abel Bernabeu]

[-- Attachment #1.1: Type: text/plain, Size: 1524 bytes --]

Thanks Thomas!

On Tue, Aug 2, 2022 at 12:09 AM Thomas Petazzoni <
thomas.petazzoni@bootlin.com> wrote:

> On Sat, 23 Jul 2022 23:54:47 +0200
> Abel Bernabeu <abel@x-silicon.com> wrote:
>
> > The initial support for the LLVM package did not include RISC-V, and
> > needed to be added.
> >
> > There is a new configuration parameter added
> > (BR2_PACKAGE_LLVM_TARGETS_TO_BUILD) for dealing with the fact that
> > the LLVM target and the architecture have different naming for RISC-V.
> > While the target for RISC-V is "RISCV" irrespective of the ISA being
> > 32 or 64 bits, the architecture does contain the number of bits
> > leading to "riscv32" and "riscv64".
> >
> > For previously supported architectures the naming for target and
> > architecture matched and thus this parameter had not been needed, but
> > it is now needed for RISC-V.
> >
> > Signed-off-by: Abel Bernabeu <abel@x-silicon.com>
> > ---
> >  package/llvm/Config.in | 10 ++++++++++
> >  package/llvm/llvm.mk   |  2 +-
> >  2 files changed, 11 insertions(+), 1 deletion(-)
>
> I have simplified the RISCV quirk by moving it to the llvm.mk file:
>
> # Build backend for target architecture. This include backends like
> # AMDGPU. We need to special case RISCV.
> ifneq ($(filter riscv%,$(LLVM_TARGET_ARCH)),)
> LLVM_TARGETS_TO_BUILD = RISCV
> else
> LLVM_TARGETS_TO_BUILD = $(LLVM_TARGET_ARCH)
> endif
>
> Applied with this change, thanks!
>
> Thomas
> --
> Thomas Petazzoni, CTO, Bootlin
> Embedded Linux and Kernel engineering
> https://bootlin.com
>

[-- Attachment #1.2: Type: text/html, Size: 2346 bytes --]

[-- Attachment #2: Type: text/plain, Size: 150 bytes --]

_______________________________________________
buildroot mailing list
buildroot@buildroot.org
https://lists.buildroot.org/mailman/listinfo/buildroot