[Buildroot] [PATCH] arch/config: Enable RISC-V Toolchain with Vector Extension

[Buildroot] [PATCH] arch/config: Enable RISC-V Toolchain with Vector Extension

[Tianrui Wei via buildroot]

This commits adds support for building a RISC-V toolchain with the
vector extension.

Signed-off-by: Tianrui Wei <tianrui@tianruiwei.com>
---
 arch/Config.in.riscv | 8 ++++++++
 arch/arch.mk.riscv   | 3 +++
 2 files changed, 11 insertions(+)

diff --git a/arch/Config.in.riscv b/arch/Config.in.riscv
index b5e84389e0..c5b6c48ed3 100644
--- a/arch/Config.in.riscv
+++ b/arch/Config.in.riscv
@@ -18,6 +18,9 @@ config BR2_RISCV_ISA_RVD
 config BR2_RISCV_ISA_RVC
 	bool
 
+config BR2_RISCV_ISA_RVV
+	bool
+
 choice
 	prompt "Target Architecture Variant"
 	default BR2_riscv_g
@@ -63,6 +66,11 @@ config BR2_RISCV_ISA_CUSTOM_RVD
 config BR2_RISCV_ISA_CUSTOM_RVC
 	bool "Compressed Instructions (C)"
 	select BR2_RISCV_ISA_RVC
+
+config BR2_RISCV_ISA_CUSTOM_RVV
+	bool "Vector Instructions (V)"
+	select BR2_RISCV_ISA_RVV
+
 endif
 
 choice
diff --git a/arch/arch.mk.riscv b/arch/arch.mk.riscv
index 8d2236147c..ee5c434b97 100644
--- a/arch/arch.mk.riscv
+++ b/arch/arch.mk.riscv
@@ -26,6 +26,9 @@ endif
 ifeq ($(BR2_RISCV_ISA_RVC),y)
 GCC_TARGET_ARCH := $(GCC_TARGET_ARCH)c
 endif
+ifeq ($(BR2_RISCV_ISA_RVV),y)
+GCC_TARGET_ARCH := $(GCC_TARGET_ARCH)v
+endif
 
 # Starting from gcc 12.x, csr and fence instructions have been
 # separated from the base I instruction set, and special -march
-- 
2.41.0

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Re: [Buildroot] [PATCH] arch/config: Enable RISC-V Toolchain with Vector Extension

[Thomas Petazzoni via buildroot]

Hello Tianrui,

On Fri,  9 Jun 2023 17:46:42 +0000
Tianrui Wei via buildroot <buildroot@buildroot.org> wrote:

> This commits adds support for building a RISC-V toolchain with the
> vector extension.
> 
> Signed-off-by: Tianrui Wei <tianrui@tianruiwei.com>
> ---
>  arch/Config.in.riscv | 8 ++++++++
>  arch/arch.mk.riscv   | 3 +++
>  2 files changed, 11 insertions(+)

I've applied to master, after adding a "select
BR2_ARCH_NEEDS_GCC_AT_LEAST_12" which was missing, to ensure that only
gcc >= 12.x can be selected when vector extension is enabled, since
support for this was only added in gcc 12.x.

Best regards,

Thomas
-- 
Thomas Petazzoni, CTO, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
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