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From: Pavel Machek <pavel@denx.de>
To: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
Cc: cip-dev@lists.cip-project.org,
	Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>,
	Biju Das <biju.das.jz@bp.renesas.com>,
	Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>,
	tomm.merciai@gmail.com
Subject: Re: [PATCH 6.1.y-cip 19/43] pinctrl: renesas: rzg2l: Add support for RZ/V2H SoC
Date: Tue, 1 Apr 2025 12:34:11 +0200	[thread overview]
Message-ID: <Z+vBI87WfQCmFafK@duo.ucw.cz> (raw)
In-Reply-To: <20250331104514.79090-20-tommaso.merciai.xr@bp.renesas.com>

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Hi!

> commit 9bd95ac86e700ab8b1a6c225685e0e5afe426b4e upstream.
> 
> Add pinctrl driver support for RZ/V2H(P) SoC.
> 
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> Link: https://lore.kernel.org/r/20240530173857.164073-16-prabhakar.mahadev-lad.rj@bp.renesas.com
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
> Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
> ---
>  drivers/pinctrl/renesas/pinctrl-rzg2l.c | 374 +++++++++++++++++++++++-
>  1 file changed, 371 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> index d42ce90af83ac..8c29c8d3c5743 100644
> --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> @@ -1041,14 +1086,104 @@ static int rzg2l_bias_param_to_hw(enum pin_config_param param)
>  	return -EINVAL;
>  }
>  
> +static int rzv2h_hw_to_bias_param(unsigned int bias)
> +{
> +	switch (bias) {
> +	case 0:
> +	case 1:
> +		return PIN_CONFIG_BIAS_DISABLE;
> +	case 2:
> +		return PIN_CONFIG_BIAS_PULL_DOWN;
> +	case 3:
> +		return PIN_CONFIG_BIAS_PULL_UP;
> +	default:
> +		break;
> +	}
> +
> +	return -EINVAL;
> +}
> +
> +static int rzv2h_bias_param_to_hw(enum pin_config_param param)
> +{
> +	switch (param) {
> +	case PIN_CONFIG_BIAS_DISABLE:
> +		return 0;
> +	case PIN_CONFIG_BIAS_PULL_DOWN:
> +		return 2;
> +	case PIN_CONFIG_BIAS_PULL_UP:
> +		return 3;
> +	default:
> +		break;
> +	}
> +
> +	return -EINVAL;
> +}

Again, direct return might be better here.

> +static u8 rzv2h_pin_to_oen_bit(struct rzg2l_pinctrl *pctrl, u32 offset)
> +{
> +	static const char * const pin_names[] = { "ET0_TXC_TXCLK", "ET1_TXC_TXCLK",
> +						  "XSPI0_RESET0N", "XSPI0_CS0N",
> +						  "XSPI0_CKN", "XSPI0_CKP" };
> +	const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset];
> +	unsigned int i;
> +
> +	for (i = 0; i < ARRAY_SIZE(pin_names); i++) {
> +		if (!strcmp(pin_desc->name, pin_names[i]))
> +			return i;
> +	}
> +
> +	/* Should not happen. */
> +	return 0;
> +}

Should we have WARN() here?

>  static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev,
>  				     unsigned int _pin,
>  				     unsigned long *config)
>  {
>  	struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
> -	enum pin_config_param param = pinconf_to_config_param(*config);
>  	const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg;
>  	const struct pinctrl_pin_desc *pin = &pctrl->desc.pins[_pin];
> +	u32 param = pinconf_to_config_param(*config);
>  	u64 *pin_data = pin->drv_data;
>  	unsigned int arg = 0;
>  	u32 off;

I wonder what is going on here. param changed types, but I don't see
corresponding change to pinconf_to_config_param() prototype.

Best regards,
								Pavel
-- 
DENX Software Engineering GmbH,        Managing Director: Erika Unter
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany

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  reply	other threads:[~2025-04-01 10:34 UTC|newest]

Thread overview: 50+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-03-31 10:44 [PATCH 6.1.y-cip 00/43] Add RZ/G3E pinctrl support Tommaso Merciai
2025-03-31 10:44 ` [PATCH 6.1.y-cip 01/43] dt-bindings: pinctrl: renesas: Add alpha-numerical port support for RZ/V2H Tommaso Merciai
2025-03-31 10:44 ` [PATCH 6.1.y-cip 02/43] dt-bindings: pinctrl: renesas,rzg2l-pinctrl: Allow 'input' and 'output-enable' properties Tommaso Merciai
2025-03-31 10:44 ` [PATCH 6.1.y-cip 03/43] dt-bindings: pinctrl: renesas,rzg2l-pinctrl: Remove the check from the object Tommaso Merciai
2025-03-31 10:44 ` [PATCH 6.1.y-cip 04/43] dt-bindings: pinctrl: renesas: Document RZ/V2H(P) SoC Tommaso Merciai
2025-03-31 10:44 ` [PATCH 6.1.y-cip 05/43] dt-bindings: pinctrl: renesas,rzg2l-pinctrl: Allow schmitt and open drain properties Tommaso Merciai
2025-03-31 10:44 ` [PATCH 6.1.y-cip 06/43] dt-bindings: pinctrl: renesas: Document RZ/G3E SoC Tommaso Merciai
2025-03-31 10:44 ` [PATCH 6.1.y-cip 07/43] pinctrl: renesas: rzg2l: Allow more bits for pin configuration Tommaso Merciai
2025-03-31 10:44 ` [PATCH 6.1.y-cip 08/43] pinctrl: renesas: rzg2l: Drop struct rzg2l_variable_pin_cfg Tommaso Merciai
2025-03-31 10:44 ` [PATCH 6.1.y-cip 09/43] pinctrl: renesas: rzg2l: Enable variable configuration for all Tommaso Merciai
2025-03-31 10:44 ` [PATCH 6.1.y-cip 10/43] pinctrl: renesas: rzg2l: Validate power registers for SD and ETH Tommaso Merciai
2025-03-31 10:44 ` [PATCH 6.1.y-cip 11/43] pinctrl: renesas: rzg2l: Add function pointer for PFC register locking Tommaso Merciai
2025-03-31 10:44 ` [PATCH 6.1.y-cip 12/43] pinctrl: renesas: rzg2l: Add function pointer for PMC register write Tommaso Merciai
2025-03-31 10:44 ` [PATCH 6.1.y-cip 13/43] pinctrl: renesas: rzg2l: Add function pointers for OEN register access Tommaso Merciai
2025-03-31 10:44 ` [PATCH 6.1.y-cip 14/43] pinctrl: renesas: rzg2l: Add support to configure slew-rate Tommaso Merciai
2025-03-31 10:44 ` [PATCH 6.1.y-cip 15/43] pinctrl: renesas: rzg2l: Add support for pull-up/down Tommaso Merciai
2025-04-01 10:30   ` Pavel Machek
2025-03-31 10:44 ` [PATCH 6.1.y-cip 16/43] pinctrl: renesas: rzg2l: Pass pincontrol device to pinconf_generic_parse_dt_config() Tommaso Merciai
2025-03-31 10:44 ` [PATCH 6.1.y-cip 17/43] pinctrl: renesas: rzg2l: Add support for custom parameters Tommaso Merciai
2025-03-31 10:44 ` [PATCH 6.1.y-cip 18/43] pinctrl: renesas: rzg2l: Acquire lock in rzg2l_pinctrl_pm_setup_pfc() Tommaso Merciai
2025-03-31 10:44 ` [PATCH 6.1.y-cip 19/43] pinctrl: renesas: rzg2l: Add support for RZ/V2H SoC Tommaso Merciai
2025-04-01 10:34   ` Pavel Machek [this message]
2025-03-31 10:44 ` [PATCH 6.1.y-cip 20/43] pinctrl: renesas: rzg2l: Update PIN_CFG_MASK() macro to be 32-bit wide Tommaso Merciai
2025-03-31 10:44 ` [PATCH 6.1.y-cip 21/43] pinctrl: renesas: rzg2l: Adjust bit masks for PIN_CFG_VARIABLE to use BIT(62) Tommaso Merciai
2025-03-31 10:44 ` [PATCH 6.1.y-cip 22/43] pinctrl: renesas: rzg2l: Move RZG2L_SINGLE_PIN definition to top of the file Tommaso Merciai
2025-03-31 10:44 ` [PATCH 6.1.y-cip 23/43] pinctrl: renesas: rzg2l: Reorganize variable configuration macro Tommaso Merciai
2025-03-31 10:44 ` [PATCH 6.1.y-cip 24/43] pinctrl: renesas: rzg2l: Clarify OEN read/write support Tommaso Merciai
2025-04-01 10:38   ` Pavel Machek
     [not found]   ` <18322B8E923A9106.2063@lists.cip-project.org>
2025-04-01 10:45     ` [cip-dev] " Pavel Machek
2025-03-31 10:44 ` [PATCH 6.1.y-cip 25/43] pinctrl: renesas: rzg2l: Clean up and refactor OEN read/write functions Tommaso Merciai
2025-03-31 10:44 ` [PATCH 6.1.y-cip 26/43] pinctrl: renesas: rzg2l: Support output enable on RZ/G2L Tommaso Merciai
2025-03-31 10:44 ` [PATCH 6.1.y-cip 27/43] pinctrl: renesas: rzg2l: Return -EINVAL if the pin doesn't support PIN_CFG_OEN Tommaso Merciai
2025-03-31 10:44 ` [PATCH 6.1.y-cip 28/43] pinctrl: renesas: rzg2l: Use dev_err_probe() Tommaso Merciai
2025-03-31 10:45 ` [PATCH 6.1.y-cip 29/43] mm/util: Introduce kmemdup_array() Tommaso Merciai
2025-03-31 10:45 ` [PATCH 6.1.y-cip 30/43] pinctrl: renesas: Switch to use kmemdup_array() Tommaso Merciai
2025-03-31 10:45 ` [PATCH 6.1.y-cip 31/43] pinctrl: renesas: rzg2l: Replace of_node_to_fwnode() with more suitable API Tommaso Merciai
2025-03-31 10:45 ` [PATCH 6.1.y-cip 32/43] pinctrl: renesas: rzg2l: Introduce single macro for digital noise filter configuration Tommaso Merciai
2025-03-31 10:45 ` [PATCH 6.1.y-cip 33/43] pinctrl: renesas: rzg2l: Move pinconf_to_config_argument() call outside of switch cases Tommaso Merciai
2025-03-31 10:45 ` [PATCH 6.1.y-cip 34/43] pinctrl: renesas: rzg2l: Remove RZG2L_TINT_IRQ_START_INDEX Tommaso Merciai
2025-03-31 10:45 ` [PATCH 6.1.y-cip 35/43] pinctrl: renesas: rzg2l: Fix missing return in rzg2l_pinctrl_register() Tommaso Merciai
2025-03-31 10:45 ` [PATCH 6.1.y-cip 36/43] pinctrl: renesas: rzg2l: Add support for enabling/disabling open-drain outputs Tommaso Merciai
2025-03-31 10:45 ` [PATCH 6.1.y-cip 37/43] pinctrl: renesas: rzg2l: Add support for configuring schmitt-trigger Tommaso Merciai
2025-03-31 10:45 ` [PATCH 6.1.y-cip 38/43] pinctrl: renesas: rzg2l: Use gpiochip_populate_parent_fwspec_twocell helper Tommaso Merciai
2025-03-31 10:45 ` [PATCH 6.1.y-cip 39/43] pinctrl: renesas: rzg2l: Update r9a09g057_variable_pin_cfg table Tommaso Merciai
2025-03-31 10:45 ` [PATCH 6.1.y-cip 40/43] pinctrl: renesas: rzg2l: Add support for RZ/G3E SoC Tommaso Merciai
2025-03-31 10:45 ` [PATCH 6.1.y-cip 41/43] pinctrl: renesas: rzg2l: Fix PFC_MASK for RZ/V2H and RZ/G3E Tommaso Merciai
2025-03-31 10:45 ` [PATCH 6.1.y-cip 42/43] arm64: dts: renesas: r9a09g047: Add pincontrol node Tommaso Merciai
2025-03-31 10:45 ` [PATCH 6.1.y-cip 43/43] arm64: dts: renesas: r9a09g047e57-smarc: Add SCIF pincontrol Tommaso Merciai
2025-04-01 10:46 ` [PATCH 6.1.y-cip 00/43] Add RZ/G3E pinctrl support Pavel Machek
2025-04-02  8:00 ` Pavel Machek

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