* [PATCH v6.1.y-cip 1/3] clk: renesas: r9a08g045: Add DMA clocks and resets
2025-04-28 5:00 [PATCH v6.1.y-cip 0/3] RZ/G3S: Backport DMA Claudiu
@ 2025-04-28 5:00 ` Claudiu
2025-04-28 5:00 ` [PATCH v6.1.y-cip 2/3] dt-bindings: dma: rz-dmac: Document RZ/G3S SoC Claudiu
` (3 subsequent siblings)
4 siblings, 0 replies; 7+ messages in thread
From: Claudiu @ 2025-04-28 5:00 UTC (permalink / raw)
To: nobuhiro1.iwamatsu, pavel; +Cc: claudiu.beznea, cip-dev
From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
commit 6f5c16b74b8d2eacc98f4e0d1611a129aa6506bd upstream.
Add the missing DMA clock and resets.
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20240711123405.2966302-2-claudiu.beznea.uj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
---
drivers/clk/renesas/r9a08g045-cpg.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/clk/renesas/r9a08g045-cpg.c b/drivers/clk/renesas/r9a08g045-cpg.c
index 55e7d42dc472..b22bc5e972a4 100644
--- a/drivers/clk/renesas/r9a08g045-cpg.c
+++ b/drivers/clk/renesas/r9a08g045-cpg.c
@@ -193,6 +193,7 @@ static const struct rzg2l_mod_clk r9a08g045_mod_clks[] = {
DEF_MOD("ia55_pclk", R9A08G045_IA55_PCLK, R9A08G045_CLK_P2, 0x518, 0),
DEF_MOD("ia55_clk", R9A08G045_IA55_CLK, R9A08G045_CLK_P1, 0x518, 1),
DEF_MOD("dmac_aclk", R9A08G045_DMAC_ACLK, R9A08G045_CLK_P3, 0x52c, 0),
+ DEF_MOD("dmac_pclk", R9A08G045_DMAC_PCLK, CLK_P3_DIV2, 0x52c, 1),
DEF_MOD("wdt0_pclk", R9A08G045_WDT0_PCLK, R9A08G045_CLK_P0, 0x548, 0),
DEF_MOD("wdt0_clk", R9A08G045_WDT0_CLK, R9A08G045_OSCCLK, 0x548, 1),
DEF_MOD("sdhi0_imclk", R9A08G045_SDHI0_IMCLK, CLK_SD0_DIV4, 0x554, 0),
@@ -222,6 +223,8 @@ static const struct rzg2l_reset r9a08g045_resets[] = {
DEF_RST(R9A08G045_GIC600_GICRESET_N, 0x814, 0),
DEF_RST(R9A08G045_GIC600_DBG_GICRESET_N, 0x814, 1),
DEF_RST(R9A08G045_IA55_RESETN, 0x818, 0),
+ DEF_RST(R9A08G045_DMAC_ARESETN, 0x82c, 0),
+ DEF_RST(R9A08G045_DMAC_RST_ASYNC, 0x82c, 1),
DEF_RST(R9A08G045_WDT0_PRESETN, 0x848, 0),
DEF_RST(R9A08G045_SDHI0_IXRST, 0x854, 0),
DEF_RST(R9A08G045_SDHI1_IXRST, 0x854, 1),
--
2.43.0
^ permalink raw reply related [flat|nested] 7+ messages in thread* [PATCH v6.1.y-cip 2/3] dt-bindings: dma: rz-dmac: Document RZ/G3S SoC
2025-04-28 5:00 [PATCH v6.1.y-cip 0/3] RZ/G3S: Backport DMA Claudiu
2025-04-28 5:00 ` [PATCH v6.1.y-cip 1/3] clk: renesas: r9a08g045: Add DMA clocks and resets Claudiu
@ 2025-04-28 5:00 ` Claudiu
2025-04-28 5:00 ` [PATCH v6.1.y-cip 3/3] arm64: dts: renesas: r9a08g045: Add DMAC node Claudiu
` (2 subsequent siblings)
4 siblings, 0 replies; 7+ messages in thread
From: Claudiu @ 2025-04-28 5:00 UTC (permalink / raw)
To: nobuhiro1.iwamatsu, pavel; +Cc: claudiu.beznea, cip-dev
From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
commit 7492b2f89cf6d83e2a68400c43be25bd8d4cff4b upstream.
Document the Renesas RZ/G3S DMAC block. This is identical to the one found
on the RZ/G2L SoC.
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20240711123405.2966302-3-claudiu.beznea.uj@bp.renesas.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
---
Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml b/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml
index 7e472f3d6087..6e7b4b6af0b0 100644
--- a/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml
+++ b/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml
@@ -19,6 +19,7 @@ properties:
- renesas,r9a07g043-dmac # RZ/G2UL
- renesas,r9a07g044-dmac # RZ/G2{L,LC}
- renesas,r9a07g054-dmac # RZ/V2L
+ - renesas,r9a08g045-dmac # RZ/G3S
- const: renesas,rz-dmac
reg:
--
2.43.0
^ permalink raw reply related [flat|nested] 7+ messages in thread* [PATCH v6.1.y-cip 3/3] arm64: dts: renesas: r9a08g045: Add DMAC node
2025-04-28 5:00 [PATCH v6.1.y-cip 0/3] RZ/G3S: Backport DMA Claudiu
2025-04-28 5:00 ` [PATCH v6.1.y-cip 1/3] clk: renesas: r9a08g045: Add DMA clocks and resets Claudiu
2025-04-28 5:00 ` [PATCH v6.1.y-cip 2/3] dt-bindings: dma: rz-dmac: Document RZ/G3S SoC Claudiu
@ 2025-04-28 5:00 ` Claudiu
2025-04-28 7:01 ` [cip-dev] [PATCH v6.1.y-cip 0/3] RZ/G3S: Backport DMA Pavel Machek
2025-04-29 9:53 ` Pavel Machek
4 siblings, 0 replies; 7+ messages in thread
From: Claudiu @ 2025-04-28 5:00 UTC (permalink / raw)
To: nobuhiro1.iwamatsu, pavel; +Cc: claudiu.beznea, cip-dev
From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
commit 054a83a1548ce30eeebcf95c86951d3ef56e6f7d upstream.
Add DMAC node.
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20240711123405.2966302-4-claudiu.beznea.uj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
---
arch/arm64/boot/dts/renesas/r9a08g045.dtsi | 38 ++++++++++++++++++++++
1 file changed, 38 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi
index 3401c1200a1c..3803605d7db0 100644
--- a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi
@@ -208,6 +208,44 @@ irqc: interrupt-controller@11050000 {
resets = <&cpg R9A08G045_IA55_RESETN>;
};
+ dmac: dma-controller@11820000 {
+ compatible = "renesas,r9a08g045-dmac",
+ "renesas,rz-dmac";
+ reg = <0 0x11820000 0 0x10000>,
+ <0 0x11830000 0 0x10000>;
+ interrupts = <GIC_SPI 111 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 112 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 113 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 114 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 115 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 116 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 117 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 118 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 119 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 120 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 121 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 122 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 123 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 124 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 125 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 126 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 127 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "error",
+ "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12", "ch13", "ch14", "ch15";
+ clocks = <&cpg CPG_MOD R9A08G045_DMAC_ACLK>,
+ <&cpg CPG_MOD R9A08G045_DMAC_PCLK>;
+ clock-names = "main", "register";
+ power-domains = <&cpg>;
+ resets = <&cpg R9A08G045_DMAC_ARESETN>,
+ <&cpg R9A08G045_DMAC_RST_ASYNC>;
+ reset-names = "arst", "rst_async";
+ #dma-cells = <1>;
+ dma-channels = <16>;
+ };
+
sdhi0: mmc@11c00000 {
compatible = "renesas,sdhi-r9a08g045", "renesas,rcar-gen3-sdhi";
reg = <0x0 0x11c00000 0 0x10000>;
--
2.43.0
^ permalink raw reply related [flat|nested] 7+ messages in thread* Re: [cip-dev] [PATCH v6.1.y-cip 0/3] RZ/G3S: Backport DMA
2025-04-28 5:00 [PATCH v6.1.y-cip 0/3] RZ/G3S: Backport DMA Claudiu
` (2 preceding siblings ...)
2025-04-28 5:00 ` [PATCH v6.1.y-cip 3/3] arm64: dts: renesas: r9a08g045: Add DMAC node Claudiu
@ 2025-04-28 7:01 ` Pavel Machek
2025-04-29 9:53 ` Pavel Machek
4 siblings, 0 replies; 7+ messages in thread
From: Pavel Machek @ 2025-04-28 7:01 UTC (permalink / raw)
To: claudiu beznea; +Cc: nobuhiro1.iwamatsu, cip-dev
[-- Attachment #1: Type: text/plain, Size: 440 bytes --]
Hi!
> Series backports the Renesas RZ/G3S DMA support to v5.10.y CIP.
Thank you. Same as 5.10 -- series looks okay to me, and I can apply it
if there are no other comments and it passes testing.
Best regards,
Pavel
--
DENX Software Engineering GmbH, Managing Director: Erika Unter
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 195 bytes --]
^ permalink raw reply [flat|nested] 7+ messages in thread* Re: [cip-dev] [PATCH v6.1.y-cip 0/3] RZ/G3S: Backport DMA
2025-04-28 5:00 [PATCH v6.1.y-cip 0/3] RZ/G3S: Backport DMA Claudiu
` (3 preceding siblings ...)
2025-04-28 7:01 ` [cip-dev] [PATCH v6.1.y-cip 0/3] RZ/G3S: Backport DMA Pavel Machek
@ 2025-04-29 9:53 ` Pavel Machek
2025-04-29 12:24 ` Claudiu Beznea
4 siblings, 1 reply; 7+ messages in thread
From: Pavel Machek @ 2025-04-29 9:53 UTC (permalink / raw)
To: claudiu beznea; +Cc: nobuhiro1.iwamatsu, cip-dev
[-- Attachment #1: Type: text/plain, Size: 388 bytes --]
Hi!
> Series backports the Renesas RZ/G3S DMA support to v5.10.y CIP.
Applied. I had to fix up 3/ patch as the dts changed and it no longer
applied. It was trivial enough, so I believe I got it right.
Best regards,
Pavel
--
DENX Software Engineering GmbH, Managing Director: Erika Unter
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 195 bytes --]
^ permalink raw reply [flat|nested] 7+ messages in thread* Re: [cip-dev] [PATCH v6.1.y-cip 0/3] RZ/G3S: Backport DMA
2025-04-29 9:53 ` Pavel Machek
@ 2025-04-29 12:24 ` Claudiu Beznea
0 siblings, 0 replies; 7+ messages in thread
From: Claudiu Beznea @ 2025-04-29 12:24 UTC (permalink / raw)
To: Pavel Machek; +Cc: nobuhiro1.iwamatsu, cip-dev
Hi, Pavel,
On 29.04.2025 12:53, Pavel Machek wrote:
> Hi!
>
>> Series backports the Renesas RZ/G3S DMA support to v5.10.y CIP.
>
> Applied. I had to fix up 3/ patch as the dts changed and it no longer
> applied. It was trivial enough, so I believe I got it right.
I checked it. All good. Thank you for taking care of it!
Claudiu
>
> Best regards,
> Pavel
^ permalink raw reply [flat|nested] 7+ messages in thread