[PATCH 6.1.y-cip 1/1] arm64: dts: renesas: rzg3s-smarc-som: Set bypass for Versa3 PLL2

[PATCH 6.1.y-cip 1/1] arm64: dts: renesas: rzg3s-smarc-som: Set bypass for Versa3 PLL2

[Claudiu]

From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>

commit 6dcbb6f070cccabc6a13d640a5a84de581fdd761 upstream.

The default settings for the Versa3 device on the Renesas RZ/G3S SMARC
SoM board have PLL2 disabled. PLL2 was later enabled together with audio
support, as it is required to support both 44.1 kHz and 48 kHz audio.

With PLL2 enabled, it was observed that Linux occasionally either hangs
during boot (the last log message being related to the I2C probe) or
randomly crashes. This was mainly reproducible on cold boots. During
debugging, it was also noticed that the Unicode replacement character (�)
sometimes appears on the serial console. Further investigation traced this
to the configuration applied through the Versa3 register at offset 0x1c,
which controls PLL enablement.

The appearance of the Unicode replacement character suggested an issue
with the SoC reference clock. The RZ/G3S reference clock is provided by
the Versa3 clock generator (REF output).

After checking with the Renesas Versa3 hardware team, it was found that
this is related to the PLL2 lock bit being set through the
renesas,settings DT property.

The PLL lock bit must be set to avoid unstable clock output from the PLL.
However, due to the Versa3 hardware design, when a PLL lock bit is set,
all outputs (including the REF clock) are temporarily disabled until the
configured PLLs become stable.

As an alternative, the bypass bit can be used. This does not interrupt the
PLL2 output or any other Versa3 outputs, but it may result in temporary
instability on PLL2 output while the configuration is applied. Since PLL2
feeds only the audio path and audio is not used during early boot, this is
acceptable and does not affect system boot.

Drop the PLL2 lock bit and set the bypass bit instead.

This has been tested with more than 1000 cold boots.

Fixes: a94253232b04 ("arm64: dts: renesas: rzg3s-smarc-som: Add versa3 clock generator node")
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20260302135703.162601-1-claudiu.beznea.uj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
---
 arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi
index b11f2e49748b..990adea09799 100644
--- a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi
@@ -164,7 +164,7 @@ versa3: clock-generator@68 {
 				       <100000000>;
 		renesas,settings = [
 		  80 00 11 19 4c 42 dc 2f 06 7d 20 1a 5f 1e f2 27
-		  00 40 00 00 00 00 00 00 06 0c 19 02 3f f0 90 86
+		  00 40 00 00 00 00 00 00 06 0c 19 02 3b f0 90 86
 		  a0 80 30 30 9c
 		];
 	};
-- 
2.43.0

RE: [PATCH 6.1.y-cip 1/1] arm64: dts: renesas: rzg3s-smarc-som: Set bypass for Versa3 PLL2

[nobuhiro.iwamatsu.x90]

Hi all,

> -----Original Message-----
> From: Claudiu <claudiu.beznea@tuxon.dev>
> Sent: Friday, April 3, 2026 1:10 AM
> To: iwamatsu nobuhiro(岩松 信洋 □ＤＩＴＣ○ＣＰＴ) <nobuhiro.iwamatsu.x90@mail.toshiba>; pavel@nabladev.com
> Cc: cip-dev@lists.cip-project.org
> Subject: [PATCH 6.1.y-cip 1/1] arm64: dts: renesas: rzg3s-smarc-som: Set bypass for Versa3 PLL2
> 
> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
> 
> commit 6dcbb6f070cccabc6a13d640a5a84de581fdd761 upstream.
> 
> The default settings for the Versa3 device on the Renesas RZ/G3S SMARC SoM board have PLL2 disabled. PLL2 was later
> enabled together with audio support, as it is required to support both 44.1 kHz and 48 kHz audio.
> 
> With PLL2 enabled, it was observed that Linux occasionally either hangs during boot (the last log message being related
> to the I2C probe) or randomly crashes. This was mainly reproducible on cold boots. During debugging, it was also noticed
> that the Unicode replacement character ( ) sometimes appears on the serial console. Further investigation traced this to
> the configuration applied through the Versa3 register at offset 0x1c, which controls PLL enablement.
> 
> The appearance of the Unicode replacement character suggested an issue with the SoC reference clock. The RZ/G3S
> reference clock is provided by the Versa3 clock generator (REF output).
> 
> After checking with the Renesas Versa3 hardware team, it was found that this is related to the PLL2 lock bit being set
> through the renesas,settings DT property.
> 
> The PLL lock bit must be set to avoid unstable clock output from the PLL.
> However, due to the Versa3 hardware design, when a PLL lock bit is set, all outputs (including the REF clock) are
> temporarily disabled until the configured PLLs become stable.
> 
> As an alternative, the bypass bit can be used. This does not interrupt the
> PLL2 output or any other Versa3 outputs, but it may result in temporary instability on PLL2 output while the configuration
> is applied. Since PLL2 feeds only the audio path and audio is not used during early boot, this is acceptable and does not
> affect system boot.
> 
> Drop the PLL2 lock bit and set the bypass bit instead.
> 
> This has been tested with more than 1000 cold boots.
> 
> Fixes: a94253232b04 ("arm64: dts: renesas: rzg3s-smarc-som: Add versa3 clock generator node")
> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> Link: https://patch.msgid.link/20260302135703.162601-1-claudiu.beznea.uj@bp.renesas.com
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>

I reviewed each version, looks good to me.
If tests are OK and there is no comment, I can apply.
  https://gitlab.com/cip-project/cip-kernel/linux-cip/-/pipelines/2433101088
  https://gitlab.com/cip-project/cip-kernel/linux-cip/-/pipelines/2433102394
  https://gitlab.com/cip-project/cip-kernel/linux-cip/-/pipelines/2433103164

Reviewed-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.x90@mail.toshiba>

> ---
>  arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi
> b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi
> index b11f2e49748b..990adea09799 100644
> --- a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi
> +++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi
> @@ -164,7 +164,7 @@ versa3: clock-generator@68 {
>  				       <100000000>;
>  		renesas,settings = [
>  		  80 00 11 19 4c 42 dc 2f 06 7d 20 1a 5f 1e f2 27
> -		  00 40 00 00 00 00 00 00 06 0c 19 02 3f f0 90 86
> +		  00 40 00 00 00 00 00 00 06 0c 19 02 3b f0 90 86
>  		  a0 80 30 30 9c
>  		];
>  	};
> --
> 2.43.0

Best regards,
  Nobuhiro

Re: [cip-dev] [PATCH 6.1.y-cip 1/1] arm64: dts: renesas: rzg3s-smarc-som: Set bypass for Versa3 PLL2

[Pavel Machek]

[-- Attachment #1: Type: text/plain, Size: 3009 bytes --]

Hi!

> > commit 6dcbb6f070cccabc6a13d640a5a84de581fdd761 upstream.
> > 
> > The default settings for the Versa3 device on the Renesas RZ/G3S SMARC SoM board have PLL2 disabled. PLL2 was later
> > enabled together with audio support, as it is required to support both 44.1 kHz and 48 kHz audio.
> > 
> > With PLL2 enabled, it was observed that Linux occasionally either hangs during boot (the last log message being related
> > to the I2C probe) or randomly crashes. This was mainly reproducible on cold boots. During debugging, it was also noticed
> > that the Unicode replacement character ( ) sometimes appears on the serial console. Further investigation traced this to
> > the configuration applied through the Versa3 register at offset 0x1c, which controls PLL enablement.
> > 
> > The appearance of the Unicode replacement character suggested an issue with the SoC reference clock. The RZ/G3S
> > reference clock is provided by the Versa3 clock generator (REF output).
> > 
> > After checking with the Renesas Versa3 hardware team, it was found that this is related to the PLL2 lock bit being set
> > through the renesas,settings DT property.
> > 
> > The PLL lock bit must be set to avoid unstable clock output from the PLL.
> > However, due to the Versa3 hardware design, when a PLL lock bit is set, all outputs (including the REF clock) are
> > temporarily disabled until the configured PLLs become stable.
> > 
> > As an alternative, the bypass bit can be used. This does not interrupt the
> > PLL2 output or any other Versa3 outputs, but it may result in temporary instability on PLL2 output while the configuration
> > is applied. Since PLL2 feeds only the audio path and audio is not used during early boot, this is acceptable and does not
> > affect system boot.
> > 
> > Drop the PLL2 lock bit and set the bypass bit instead.
> > 
> > This has been tested with more than 1000 cold boots.
> > 
> > Fixes: a94253232b04 ("arm64: dts: renesas: rzg3s-smarc-som: Add versa3 clock generator node")
> > Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
> > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> > Link: https://patch.msgid.link/20260302135703.162601-1-claudiu.beznea.uj@bp.renesas.com
> > Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
> > Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
> 
> I reviewed each version, looks good to me.
> If tests are OK and there is no comment, I can apply.
>   https://gitlab.com/cip-project/cip-kernel/linux-cip/-/pipelines/2433101088
>   https://gitlab.com/cip-project/cip-kernel/linux-cip/-/pipelines/2433102394
>   https://gitlab.com/cip-project/cip-kernel/linux-cip/-/pipelines/2433103164
> 
> Reviewed-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.x90@mail.toshiba>

Looks good to me, 5.10, 6.1 and 6.12 versions:

Reviewed-by: Pavel Machek <pavel@nabladev.com>

Best regards,
                                                                Pavel

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RE: [cip-dev] [PATCH 6.1.y-cip 1/1] arm64: dts: renesas: rzg3s-smarc-som: Set bypass for Versa3 PLL2

[nobuhiro.iwamatsu.x90]

Hi Pavel,

> -----Original Message-----
> From: cip-dev@lists.cip-project.org <cip-dev@lists.cip-project.org> On Behalf Of Pavel Machek via lists.cip-project.org
> Sent: Tuesday, April 7, 2026 8:36 PM
> To: iwamatsu nobuhiro(岩松 信洋 □ＤＩＴＣ○ＣＰＴ) <nobuhiro.iwamatsu.x90@mail.toshiba>
> Cc: claudiu.beznea@tuxon.dev; pavel@nabladev.com; cip-dev@lists.cip-project.org
> Subject: Re: [cip-dev] [PATCH 6.1.y-cip 1/1] arm64: dts: renesas: rzg3s-smarc-som: Set bypass for Versa3 PLL2
> 
> Hi!
> 
> > > commit 6dcbb6f070cccabc6a13d640a5a84de581fdd761 upstream.
> > >
> > > The default settings for the Versa3 device on the Renesas RZ/G3S
> > > SMARC SoM board have PLL2 disabled. PLL2 was later enabled together with audio support, as it is required to
> support both 44.1 kHz and 48 kHz audio.
> > >
> > > With PLL2 enabled, it was observed that Linux occasionally either
> > > hangs during boot (the last log message being related to the I2C
> > > probe) or randomly crashes. This was mainly reproducible on cold
> > > boots. During debugging, it was also noticed that the Unicode replacement character ( ) sometimes appears on the
> serial console. Further investigation traced this to the configuration applied through the Versa3 register at offset 0x1c,
> which controls PLL enablement.
> > >
> > > The appearance of the Unicode replacement character suggested an
> > > issue with the SoC reference clock. The RZ/G3S reference clock is provided by the Versa3 clock generator (REF
> output).
> > >
> > > After checking with the Renesas Versa3 hardware team, it was found
> > > that this is related to the PLL2 lock bit being set through the renesas,settings DT property.
> > >
> > > The PLL lock bit must be set to avoid unstable clock output from the PLL.
> > > However, due to the Versa3 hardware design, when a PLL lock bit is
> > > set, all outputs (including the REF clock) are temporarily disabled until the configured PLLs become stable.
> > >
> > > As an alternative, the bypass bit can be used. This does not
> > > interrupt the
> > > PLL2 output or any other Versa3 outputs, but it may result in
> > > temporary instability on PLL2 output while the configuration is
> > > applied. Since PLL2 feeds only the audio path and audio is not used during early boot, this is acceptable and does not
> affect system boot.
> > >
> > > Drop the PLL2 lock bit and set the bypass bit instead.
> > >
> > > This has been tested with more than 1000 cold boots.
> > >
> > > Fixes: a94253232b04 ("arm64: dts: renesas: rzg3s-smarc-som: Add
> > > versa3 clock generator node")
> > > Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
> > > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> > > Link:
> > > https://patch.msgid.link/20260302135703.162601-1-claudiu.beznea.uj@b
> > > p.renesas.com
> > > Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
> > > Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
> >
> > I reviewed each version, looks good to me.
> > If tests are OK and there is no comment, I can apply.
> >   https://gitlab.com/cip-project/cip-kernel/linux-cip/-/pipelines/2433101088
> >   https://gitlab.com/cip-project/cip-kernel/linux-cip/-/pipelines/2433102394
> >
> > https://gitlab.com/cip-project/cip-kernel/linux-cip/-/pipelines/243310
> > 3164
> >
> > Reviewed-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.x90@mail.toshiba>
> 
> Looks good to me, 5.10, 6.1 and 6.12 versions:
> 
> Reviewed-by: Pavel Machek <pavel@nabladev.com>

Thanks, applied.
> 
> Best regards,
>                                                                 Pavel

Best regards,
  Nobuhiro