* [PATCH 6.1.y-cip 1/8] spi: dt-bindings: Document the RZ/V2H(P) RSPI
2026-04-15 13:19 [PATCH 6.1.y-cip 0/8] Add RSPI support for RZ/V2H and RZ/V2N Ovidiu Panait
@ 2026-04-15 13:19 ` Ovidiu Panait
2026-04-15 13:19 ` [PATCH 6.1.y-cip 2/8] spi: Add driver for the RZ/V2H(P) RSPI IP Ovidiu Panait
` (7 subsequent siblings)
8 siblings, 0 replies; 11+ messages in thread
From: Ovidiu Panait @ 2026-04-15 13:19 UTC (permalink / raw)
To: cip-dev, pavel, nobuhiro.iwamatsu.x90
From: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
commit 44b91d61c505863b8ae90b7094aee5ca0dce808f upstream.
Add dt-bindings for the RSPI IP found inside the Renesas RZ/V2H(P)
SoC.
Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20250704162036.468765-2-fabrizio.castro.jz@renesas.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Ovidiu Panait <ovidiu.panait.rb@renesas.com>
---
.../bindings/spi/renesas,rzv2h-rspi.yaml | 96 +++++++++++++++++++
1 file changed, 96 insertions(+)
create mode 100644 Documentation/devicetree/bindings/spi/renesas,rzv2h-rspi.yaml
diff --git a/Documentation/devicetree/bindings/spi/renesas,rzv2h-rspi.yaml b/Documentation/devicetree/bindings/spi/renesas,rzv2h-rspi.yaml
new file mode 100644
index 000000000000..ab27fefc3c3a
--- /dev/null
+++ b/Documentation/devicetree/bindings/spi/renesas,rzv2h-rspi.yaml
@@ -0,0 +1,96 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/spi/renesas,rzv2h-rspi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas RZ/V2H(P) Renesas Serial Peripheral Interface (RSPI)
+
+maintainers:
+ - Fabrizio Castro <fabrizio.castro.jz@renesas.com>
+
+allOf:
+ - $ref: spi-controller.yaml#
+
+properties:
+ compatible:
+ const: renesas,r9a09g057-rspi # RZ/V2H(P)
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ items:
+ - description: Idle Interrupt
+ - description: Error Interrupt
+ - description: Communication End Interrupt
+ - description: Receive Buffer Full Interrupt
+ - description: Transmit Buffer Empty Interrupt
+
+ interrupt-names:
+ items:
+ - const: idle
+ - const: error
+ - const: end
+ - const: rx
+ - const: tx
+
+ clocks:
+ maxItems: 3
+
+ clock-names:
+ items:
+ - const: pclk
+ - const: pclk_sfr
+ - const: tclk
+
+ resets:
+ maxItems: 2
+
+ reset-names:
+ items:
+ - const: presetn
+ - const: tresetn
+
+ power-domains:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - interrupt-names
+ - clocks
+ - clock-names
+ - resets
+ - reset-names
+ - power-domains
+ - '#address-cells'
+ - '#size-cells'
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/renesas-cpg-mssr.h>
+ spi@12800800 {
+ compatible = "renesas,r9a09g057-rspi";
+
+ reg = <0x12800800 0x400>;
+ interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 113 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 504 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 505 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "idle", "error", "end", "rx", "tx";
+ clocks = <&cpg CPG_MOD 0x5a>,
+ <&cpg CPG_MOD 0x5b>,
+ <&cpg CPG_MOD 0x5c>;
+ clock-names = "pclk", "pclk_sfr", "tclk";
+ resets = <&cpg 0x7f>, <&cpg 0x80>;
+ reset-names = "presetn", "tresetn";
+ power-domains = <&cpg>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
--
2.34.1
^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH 6.1.y-cip 2/8] spi: Add driver for the RZ/V2H(P) RSPI IP
2026-04-15 13:19 [PATCH 6.1.y-cip 0/8] Add RSPI support for RZ/V2H and RZ/V2N Ovidiu Panait
2026-04-15 13:19 ` [PATCH 6.1.y-cip 1/8] spi: dt-bindings: Document the RZ/V2H(P) RSPI Ovidiu Panait
@ 2026-04-15 13:19 ` Ovidiu Panait
2026-04-16 20:51 ` [cip-dev] " Pavel Machek
2026-04-15 13:19 ` [PATCH 6.1.y-cip 3/8] arm64: defconfig: Enable the RZ/V2H(P) RSPI driver Ovidiu Panait
` (6 subsequent siblings)
8 siblings, 1 reply; 11+ messages in thread
From: Ovidiu Panait @ 2026-04-15 13:19 UTC (permalink / raw)
To: cip-dev, pavel, nobuhiro.iwamatsu.x90
From: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
commit 8b61c8919dff080d83415523cd68f2fef03ccfc7 upstream.
The Renesas RZ/V2H(P) RSPI IP supports 4-wire and 3-wire
serial communications in both host role and target role.
It can use a DMA, but the I/O can also be driven by the
processor.
RX-only, TX-only, and RX-TX operations are available in
DMA mode, while in processor I/O mode it only RX-TX
operations are supported.
Add a driver to support 4-wire serial communications as
host role in processor I/O mode.
Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
Link: https://patch.msgid.link/20250704162036.468765-3-fabrizio.castro.jz@renesas.com
Signed-off-by: Mark Brown <broonie@kernel.org>
[OP:
- Fixed minor context differences and adjusted rzv2h_rspi_remove()
function signature to return int.
- Squashed upstream commit 218917659df1 ("spi: rzv2h-rspi: do not set
SPI_TRANS_FAIL_IO"), as SPI_TRANS_FAIL_IO flag does not exist in
6.1.y-cip.]
Signed-off-by: Ovidiu Panait <ovidiu.panait.rb@renesas.com>
---
drivers/spi/Kconfig | 8 +
drivers/spi/Makefile | 1 +
drivers/spi/spi-rzv2h-rspi.c | 465 +++++++++++++++++++++++++++++++++++
3 files changed, 474 insertions(+)
create mode 100644 drivers/spi/spi-rzv2h-rspi.c
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 834fc0b8e27e..346f32f2b0c5 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -792,6 +792,14 @@ config SPI_RSPI
help
SPI driver for Renesas RSPI and QSPI blocks.
+config SPI_RZV2H_RSPI
+ tristate "Renesas RZ/V2H RSPI controller"
+ depends on ARCH_RENESAS || COMPILE_TEST
+ help
+ RSPI driver for the Renesas RZ/V2H Serial Peripheral Interface (RSPI).
+ RSPI supports both SPI host and SPI target roles. This option only
+ enables the SPI host role.
+
config SPI_QCOM_QSPI
tristate "QTI QSPI controller"
depends on ARCH_QCOM
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 4b34e855c841..b1082e6e1af6 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -110,6 +110,7 @@ obj-$(CONFIG_SPI_RB4XX) += spi-rb4xx.o
obj-$(CONFIG_MACH_REALTEK_RTL) += spi-realtek-rtl.o
obj-$(CONFIG_SPI_RPCIF) += spi-rpc-if.o
obj-$(CONFIG_SPI_RSPI) += spi-rspi.o
+obj-$(CONFIG_SPI_RZV2H_RSPI) += spi-rzv2h-rspi.o
obj-$(CONFIG_SPI_S3C24XX) += spi-s3c24xx-hw.o
spi-s3c24xx-hw-y := spi-s3c24xx.o
obj-$(CONFIG_SPI_S3C64XX) += spi-s3c64xx.o
diff --git a/drivers/spi/spi-rzv2h-rspi.c b/drivers/spi/spi-rzv2h-rspi.c
new file mode 100644
index 000000000000..cf4272f99378
--- /dev/null
+++ b/drivers/spi/spi-rzv2h-rspi.c
@@ -0,0 +1,465 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Renesas RZ/V2H Renesas Serial Peripheral Interface (RSPI)
+ *
+ * Copyright (C) 2025 Renesas Electronics Corporation
+ */
+
+#include <linux/bitfield.h>
+#include <linux/bitops.h>
+#include <linux/bits.h>
+#include <linux/clk.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/limits.h>
+#include <linux/log2.h>
+#include <linux/math.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/property.h>
+#include <linux/reset.h>
+#include <linux/spi/spi.h>
+#include <linux/wait.h>
+
+/* Registers */
+#define RSPI_SPDR 0x00
+#define RSPI_SPCR 0x08
+#define RSPI_SSLP 0x10
+#define RSPI_SPBR 0x11
+#define RSPI_SPSCR 0x13
+#define RSPI_SPCMD 0x14
+#define RSPI_SPDCR2 0x44
+#define RSPI_SPSR 0x52
+#define RSPI_SPSRC 0x6a
+#define RSPI_SPFCR 0x6c
+
+/* Register SPCR */
+#define RSPI_SPCR_MSTR BIT(30)
+#define RSPI_SPCR_SPRIE BIT(17)
+#define RSPI_SPCR_SCKASE BIT(12)
+#define RSPI_SPCR_SPE BIT(0)
+
+/* Register SPBR */
+#define RSPI_SPBR_SPR_MIN 0
+#define RSPI_SPBR_SPR_MAX 255
+
+/* Register SPCMD */
+#define RSPI_SPCMD_SSLA GENMASK(25, 24)
+#define RSPI_SPCMD_SPB GENMASK(20, 16)
+#define RSPI_SPCMD_LSBF BIT(12)
+#define RSPI_SPCMD_SSLKP BIT(7)
+#define RSPI_SPCMD_BRDV GENMASK(3, 2)
+#define RSPI_SPCMD_CPOL BIT(1)
+#define RSPI_SPCMD_CPHA BIT(0)
+
+#define RSPI_SPCMD_BRDV_MIN 0
+#define RSPI_SPCMD_BRDV_MAX 3
+
+/* Register SPDCR2 */
+#define RSPI_SPDCR2_TTRG GENMASK(11, 8)
+#define RSPI_SPDCR2_RTRG GENMASK(3, 0)
+#define RSPI_FIFO_SIZE 16
+
+/* Register SPSR */
+#define RSPI_SPSR_SPRF BIT(15)
+
+/* Register RSPI_SPSRC */
+#define RSPI_SPSRC_CLEAR 0xfd80
+
+#define RSPI_RESET_NUM 2
+#define RSPI_CLK_NUM 3
+
+struct rzv2h_rspi_priv {
+ struct reset_control_bulk_data resets[RSPI_RESET_NUM];
+ struct spi_controller *controller;
+ void __iomem *base;
+ struct clk *tclk;
+ wait_queue_head_t wait;
+ unsigned int bytes_per_word;
+ u32 freq;
+ u16 status;
+};
+
+#define RZV2H_RSPI_TX(func, type) \
+static inline void rzv2h_rspi_tx_##type(struct rzv2h_rspi_priv *rspi, \
+ const void *txbuf, \
+ unsigned int index) { \
+ type buf = 0; \
+ \
+ if (txbuf) \
+ buf = ((type *)txbuf)[index]; \
+ \
+ func(buf, rspi->base + RSPI_SPDR); \
+}
+
+#define RZV2H_RSPI_RX(func, type) \
+static inline void rzv2h_rspi_rx_##type(struct rzv2h_rspi_priv *rspi, \
+ void *rxbuf, \
+ unsigned int index) { \
+ type buf = func(rspi->base + RSPI_SPDR); \
+ \
+ if (rxbuf) \
+ ((type *)rxbuf)[index] = buf; \
+}
+
+RZV2H_RSPI_TX(writel, u32)
+RZV2H_RSPI_TX(writew, u16)
+RZV2H_RSPI_TX(writeb, u8)
+RZV2H_RSPI_RX(readl, u32)
+RZV2H_RSPI_RX(readw, u16)
+RZV2H_RSPI_RX(readl, u8)
+
+static void rzv2h_rspi_reg_rmw(const struct rzv2h_rspi_priv *rspi,
+ int reg_offs, u32 bit_mask, u32 value)
+{
+ u32 tmp;
+
+ value <<= __ffs(bit_mask);
+ tmp = (readl(rspi->base + reg_offs) & ~bit_mask) | value;
+ writel(tmp, rspi->base + reg_offs);
+}
+
+static inline void rzv2h_rspi_spe_disable(const struct rzv2h_rspi_priv *rspi)
+{
+ rzv2h_rspi_reg_rmw(rspi, RSPI_SPCR, RSPI_SPCR_SPE, 0);
+}
+
+static inline void rzv2h_rspi_spe_enable(const struct rzv2h_rspi_priv *rspi)
+{
+ rzv2h_rspi_reg_rmw(rspi, RSPI_SPCR, RSPI_SPCR_SPE, 1);
+}
+
+static inline void rzv2h_rspi_clear_fifos(const struct rzv2h_rspi_priv *rspi)
+{
+ writeb(1, rspi->base + RSPI_SPFCR);
+}
+
+static inline void rzv2h_rspi_clear_all_irqs(struct rzv2h_rspi_priv *rspi)
+{
+ writew(RSPI_SPSRC_CLEAR, rspi->base + RSPI_SPSRC);
+ rspi->status = 0;
+}
+
+static irqreturn_t rzv2h_rx_irq_handler(int irq, void *data)
+{
+ struct rzv2h_rspi_priv *rspi = data;
+
+ rspi->status = readw(rspi->base + RSPI_SPSR);
+ wake_up(&rspi->wait);
+
+ return IRQ_HANDLED;
+}
+
+static inline int rzv2h_rspi_wait_for_interrupt(struct rzv2h_rspi_priv *rspi,
+ u32 wait_mask)
+{
+ return wait_event_timeout(rspi->wait, (rspi->status & wait_mask),
+ HZ) == 0 ? -ETIMEDOUT : 0;
+}
+
+static void rzv2h_rspi_send(struct rzv2h_rspi_priv *rspi, const void *txbuf,
+ unsigned int index)
+{
+ switch (rspi->bytes_per_word) {
+ case 4:
+ rzv2h_rspi_tx_u32(rspi, txbuf, index);
+ break;
+ case 2:
+ rzv2h_rspi_tx_u16(rspi, txbuf, index);
+ break;
+ default:
+ rzv2h_rspi_tx_u8(rspi, txbuf, index);
+ }
+}
+
+static int rzv2h_rspi_receive(struct rzv2h_rspi_priv *rspi, void *rxbuf,
+ unsigned int index)
+{
+ int ret;
+
+ ret = rzv2h_rspi_wait_for_interrupt(rspi, RSPI_SPSR_SPRF);
+ if (ret)
+ return ret;
+
+ switch (rspi->bytes_per_word) {
+ case 4:
+ rzv2h_rspi_rx_u32(rspi, rxbuf, index);
+ break;
+ case 2:
+ rzv2h_rspi_rx_u16(rspi, rxbuf, index);
+ break;
+ default:
+ rzv2h_rspi_rx_u8(rspi, rxbuf, index);
+ }
+
+ return 0;
+}
+
+static int rzv2h_rspi_transfer_one(struct spi_controller *controller,
+ struct spi_device *spi,
+ struct spi_transfer *transfer)
+{
+ struct rzv2h_rspi_priv *rspi = spi_controller_get_devdata(controller);
+ unsigned int words_to_transfer, i;
+ int ret = 0;
+
+ transfer->effective_speed_hz = rspi->freq;
+ words_to_transfer = transfer->len / rspi->bytes_per_word;
+
+ for (i = 0; i < words_to_transfer; i++) {
+ rzv2h_rspi_clear_all_irqs(rspi);
+
+ rzv2h_rspi_send(rspi, transfer->tx_buf, i);
+
+ ret = rzv2h_rspi_receive(rspi, transfer->rx_buf, i);
+ if (ret)
+ break;
+ }
+
+ rzv2h_rspi_clear_all_irqs(rspi);
+
+ spi_finalize_current_transfer(controller);
+
+ return ret;
+}
+
+static inline u32 rzv2h_rspi_calc_bitrate(unsigned long tclk_rate, u8 spr,
+ u8 brdv)
+{
+ return DIV_ROUND_UP(tclk_rate, (2 * (spr + 1) * (1 << brdv)));
+}
+
+static u32 rzv2h_rspi_setup_clock(struct rzv2h_rspi_priv *rspi, u32 hz)
+{
+ unsigned long tclk_rate;
+ int spr;
+ u8 brdv;
+
+ /*
+ * From the manual:
+ * Bit rate = f(RSPI_n_TCLK)/(2*(n+1)*2^(N))
+ *
+ * Where:
+ * * RSPI_n_TCLK is fixed to 200MHz on V2H
+ * * n = SPR - is RSPI_SPBR.SPR (from 0 to 255)
+ * * N = BRDV - is RSPI_SPCMD.BRDV (from 0 to 3)
+ */
+ tclk_rate = clk_get_rate(rspi->tclk);
+ for (brdv = RSPI_SPCMD_BRDV_MIN; brdv <= RSPI_SPCMD_BRDV_MAX; brdv++) {
+ spr = DIV_ROUND_UP(tclk_rate, hz * (1 << (brdv + 1)));
+ spr--;
+ if (spr >= RSPI_SPBR_SPR_MIN && spr <= RSPI_SPBR_SPR_MAX)
+ goto clock_found;
+ }
+
+ return 0;
+
+clock_found:
+ rzv2h_rspi_reg_rmw(rspi, RSPI_SPCMD, RSPI_SPCMD_BRDV, brdv);
+ writeb(spr, rspi->base + RSPI_SPBR);
+
+ return rzv2h_rspi_calc_bitrate(tclk_rate, spr, brdv);
+}
+
+static int rzv2h_rspi_prepare_message(struct spi_controller *ctlr,
+ struct spi_message *message)
+{
+ struct rzv2h_rspi_priv *rspi = spi_controller_get_devdata(ctlr);
+ const struct spi_device *spi = message->spi;
+ struct spi_transfer *xfer;
+ u32 speed_hz = U32_MAX;
+ u8 bits_per_word;
+ u32 conf32;
+ u16 conf16;
+
+ /* Make sure SPCR.SPE is 0 before amending the configuration */
+ rzv2h_rspi_spe_disable(rspi);
+
+ /* Configure the device to work in "host" mode */
+ conf32 = RSPI_SPCR_MSTR;
+
+ /* Auto-stop function */
+ conf32 |= RSPI_SPCR_SCKASE;
+
+ /* SPI receive buffer full interrupt enable */
+ conf32 |= RSPI_SPCR_SPRIE;
+
+ writel(conf32, rspi->base + RSPI_SPCR);
+
+ /* Use SPCMD0 only */
+ writeb(0x0, rspi->base + RSPI_SPSCR);
+
+ /* Setup mode */
+ conf32 = FIELD_PREP(RSPI_SPCMD_CPOL, !!(spi->mode & SPI_CPOL));
+ conf32 |= FIELD_PREP(RSPI_SPCMD_CPHA, !!(spi->mode & SPI_CPHA));
+ conf32 |= FIELD_PREP(RSPI_SPCMD_LSBF, !!(spi->mode & SPI_LSB_FIRST));
+ conf32 |= FIELD_PREP(RSPI_SPCMD_SSLKP, 1);
+ conf32 |= FIELD_PREP(RSPI_SPCMD_SSLA, spi_get_chipselect(spi, 0));
+ writel(conf32, rspi->base + RSPI_SPCMD);
+ if (spi->mode & SPI_CS_HIGH)
+ writeb(BIT(spi_get_chipselect(spi, 0)), rspi->base + RSPI_SSLP);
+ else
+ writeb(0, rspi->base + RSPI_SSLP);
+
+ /* Setup FIFO thresholds */
+ conf16 = FIELD_PREP(RSPI_SPDCR2_TTRG, RSPI_FIFO_SIZE - 1);
+ conf16 |= FIELD_PREP(RSPI_SPDCR2_RTRG, 0);
+ writew(conf16, rspi->base + RSPI_SPDCR2);
+
+ rzv2h_rspi_clear_fifos(rspi);
+
+ list_for_each_entry(xfer, &message->transfers, transfer_list) {
+ if (!xfer->speed_hz)
+ continue;
+
+ speed_hz = min(xfer->speed_hz, speed_hz);
+ bits_per_word = xfer->bits_per_word;
+ }
+
+ if (speed_hz == U32_MAX)
+ return -EINVAL;
+
+ rspi->bytes_per_word = roundup_pow_of_two(BITS_TO_BYTES(bits_per_word));
+ rzv2h_rspi_reg_rmw(rspi, RSPI_SPCMD, RSPI_SPCMD_SPB, bits_per_word - 1);
+
+ rspi->freq = rzv2h_rspi_setup_clock(rspi, speed_hz);
+ if (!rspi->freq)
+ return -EINVAL;
+
+ rzv2h_rspi_spe_enable(rspi);
+
+ return 0;
+}
+
+static int rzv2h_rspi_unprepare_message(struct spi_controller *ctlr,
+ struct spi_message *message)
+{
+ struct rzv2h_rspi_priv *rspi = spi_controller_get_devdata(ctlr);
+
+ rzv2h_rspi_spe_disable(rspi);
+
+ return 0;
+}
+
+static int rzv2h_rspi_probe(struct platform_device *pdev)
+{
+ struct spi_controller *controller;
+ struct device *dev = &pdev->dev;
+ struct rzv2h_rspi_priv *rspi;
+ struct clk_bulk_data *clks;
+ unsigned long tclk_rate;
+ int irq_rx, ret, i;
+
+ controller = devm_spi_alloc_host(dev, sizeof(*rspi));
+ if (!controller)
+ return -ENOMEM;
+
+ rspi = spi_controller_get_devdata(controller);
+ platform_set_drvdata(pdev, rspi);
+
+ rspi->controller = controller;
+
+ rspi->base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(rspi->base))
+ return PTR_ERR(rspi->base);
+
+ ret = devm_clk_bulk_get_all_enabled(dev, &clks);
+ if (ret != RSPI_CLK_NUM)
+ return dev_err_probe(dev, ret >= 0 ? -EINVAL : ret,
+ "cannot get clocks\n");
+ for (i = 0; i < RSPI_CLK_NUM; i++) {
+ if (!strcmp(clks[i].id, "tclk")) {
+ rspi->tclk = clks[i].clk;
+ break;
+ }
+ }
+
+ if (!rspi->tclk)
+ return dev_err_probe(dev, -EINVAL, "Failed to get tclk\n");
+
+ tclk_rate = clk_get_rate(rspi->tclk);
+
+ rspi->resets[0].id = "presetn";
+ rspi->resets[1].id = "tresetn";
+ ret = devm_reset_control_bulk_get_exclusive(dev, RSPI_RESET_NUM,
+ rspi->resets);
+ if (ret)
+ return dev_err_probe(dev, ret, "cannot get resets\n");
+
+ irq_rx = platform_get_irq_byname(pdev, "rx");
+ if (irq_rx < 0)
+ return dev_err_probe(dev, irq_rx, "cannot get IRQ 'rx'\n");
+
+ ret = reset_control_bulk_deassert(RSPI_RESET_NUM, rspi->resets);
+ if (ret)
+ return dev_err_probe(dev, ret, "failed to deassert resets\n");
+
+ init_waitqueue_head(&rspi->wait);
+
+ ret = devm_request_irq(dev, irq_rx, rzv2h_rx_irq_handler, 0,
+ dev_name(dev), rspi);
+ if (ret) {
+ dev_err(dev, "cannot request `rx` IRQ\n");
+ goto quit_resets;
+ }
+
+ controller->mode_bits = SPI_CPHA | SPI_CPOL | SPI_CS_HIGH |
+ SPI_LSB_FIRST;
+ controller->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
+ controller->prepare_message = rzv2h_rspi_prepare_message;
+ controller->unprepare_message = rzv2h_rspi_unprepare_message;
+ controller->num_chipselect = 4;
+ controller->transfer_one = rzv2h_rspi_transfer_one;
+ controller->min_speed_hz = rzv2h_rspi_calc_bitrate(tclk_rate,
+ RSPI_SPBR_SPR_MAX,
+ RSPI_SPCMD_BRDV_MAX);
+ controller->max_speed_hz = rzv2h_rspi_calc_bitrate(tclk_rate,
+ RSPI_SPBR_SPR_MIN,
+ RSPI_SPCMD_BRDV_MIN);
+
+ device_set_node(&controller->dev, dev_fwnode(dev));
+
+ ret = spi_register_controller(controller);
+ if (ret) {
+ dev_err(dev, "register controller failed\n");
+ goto quit_resets;
+ }
+
+ return 0;
+
+quit_resets:
+ reset_control_bulk_assert(RSPI_RESET_NUM, rspi->resets);
+
+ return ret;
+}
+
+static int rzv2h_rspi_remove(struct platform_device *pdev)
+{
+ struct rzv2h_rspi_priv *rspi = platform_get_drvdata(pdev);
+
+ spi_unregister_controller(rspi->controller);
+
+ reset_control_bulk_assert(RSPI_RESET_NUM, rspi->resets);
+
+ return 0;
+}
+
+static const struct of_device_id rzv2h_rspi_match[] = {
+ { .compatible = "renesas,r9a09g057-rspi" },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, rzv2h_rspi_match);
+
+static struct platform_driver rzv2h_rspi_drv = {
+ .probe = rzv2h_rspi_probe,
+ .remove = rzv2h_rspi_remove,
+ .driver = {
+ .name = "rzv2h_rspi",
+ .of_match_table = rzv2h_rspi_match,
+ },
+};
+module_platform_driver(rzv2h_rspi_drv);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Fabrizio Castro <fabrizio.castro.jz@renesas.com>");
+MODULE_DESCRIPTION("Renesas RZ/V2H(P) Serial Peripheral Interface Driver");
--
2.34.1
^ permalink raw reply related [flat|nested] 11+ messages in thread* Re: [cip-dev] [PATCH 6.1.y-cip 2/8] spi: Add driver for the RZ/V2H(P) RSPI IP
2026-04-15 13:19 ` [PATCH 6.1.y-cip 2/8] spi: Add driver for the RZ/V2H(P) RSPI IP Ovidiu Panait
@ 2026-04-16 20:51 ` Pavel Machek
0 siblings, 0 replies; 11+ messages in thread
From: Pavel Machek @ 2026-04-16 20:51 UTC (permalink / raw)
To: ovidiu.panait.rb; +Cc: cip-dev, pavel, nobuhiro.iwamatsu.x90
[-- Attachment #1: Type: text/plain, Size: 2040 bytes --]
Hi!
> new file mode 100644
> index 000000000000..cf4272f99378
> --- /dev/null
> +++ b/drivers/spi/spi-rzv2h-rspi.c
> +
> +#define RZV2H_RSPI_TX(func, type) \
> +static inline void rzv2h_rspi_tx_##type(struct rzv2h_rspi_priv *rspi, \
> + const void *txbuf, \
> + unsigned int index) { \
> + type buf = 0; \
> + \
> + if (txbuf) \
> + buf = ((type *)txbuf)[index]; \
> + \
> + func(buf, rspi->base + RSPI_SPDR); \
> +}
> +
> +#define RZV2H_RSPI_RX(func, type) \
> +static inline void rzv2h_rspi_rx_##type(struct rzv2h_rspi_priv *rspi, \
> + void *rxbuf, \
> + unsigned int index) { \
> + type buf = func(rspi->base + RSPI_SPDR); \
> + \
> + if (rxbuf) \
> + ((type *)rxbuf)[index] = buf; \
> +}
> +
> +RZV2H_RSPI_TX(writel, u32)
> +RZV2H_RSPI_TX(writew, u16)
> +RZV2H_RSPI_TX(writeb, u8)
> +RZV2H_RSPI_RX(readl, u32)
> +RZV2H_RSPI_RX(readw, u16)
> +RZV2H_RSPI_RX(readl, u8)
This is quite ... complex system for generating functions that are
then only used once. I suspect that if you just inlined the functions
by hand, code would be easier to read, and not really longer.
Thanks and best regards,
Pavel
> +static void rzv2h_rspi_send(struct rzv2h_rspi_priv *rspi, const void *txbuf,
> + unsigned int index)
> +{
> + switch (rspi->bytes_per_word) {
> + case 4:
> + rzv2h_rspi_tx_u32(rspi, txbuf, index);
> + break;
> + case 2:
> + rzv2h_rspi_tx_u16(rspi, txbuf, index);
> + break;
> + default:
> + rzv2h_rspi_tx_u8(rspi, txbuf, index);
> + }
> +}
> +
> +static int rzv2h_rspi_receive(struct rzv2h_rspi_priv *rspi, void *rxbuf,
> + unsigned int index)
> +{
> + int ret;
> +
> + ret = rzv2h_rspi_wait_for_interrupt(rspi, RSPI_SPSR_SPRF);
> + if (ret)
> + return ret;
> +
> + switch (rspi->bytes_per_word) {
> + case 4:
> + rzv2h_rspi_rx_u32(rspi, rxbuf, index);
> + break;
> + case 2:
> + rzv2h_rspi_rx_u16(rspi, rxbuf, index);
> + break;
> + default:
> + rzv2h_rspi_rx_u8(rspi, rxbuf, index);
> + }
> +
> + return 0;
> +}
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 195 bytes --]
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH 6.1.y-cip 3/8] arm64: defconfig: Enable the RZ/V2H(P) RSPI driver
2026-04-15 13:19 [PATCH 6.1.y-cip 0/8] Add RSPI support for RZ/V2H and RZ/V2N Ovidiu Panait
2026-04-15 13:19 ` [PATCH 6.1.y-cip 1/8] spi: dt-bindings: Document the RZ/V2H(P) RSPI Ovidiu Panait
2026-04-15 13:19 ` [PATCH 6.1.y-cip 2/8] spi: Add driver for the RZ/V2H(P) RSPI IP Ovidiu Panait
@ 2026-04-15 13:19 ` Ovidiu Panait
2026-04-15 13:19 ` [PATCH 6.1.y-cip 4/8] spi: dt-bindings: renesas,rzv2h-rspi: Document RZ/V2N SoC support Ovidiu Panait
` (5 subsequent siblings)
8 siblings, 0 replies; 11+ messages in thread
From: Ovidiu Panait @ 2026-04-15 13:19 UTC (permalink / raw)
To: cip-dev, pavel, nobuhiro.iwamatsu.x90
From: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
commit abd7c0293816a5fa5766710d2e7b576384fdec4d upstream.
Enable the Renesas RZ/V2H(P) RSPI driver for the benefit of
RZ/V2H(P) based platforms.
Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250624192304.338979-6-fabrizio.castro.jz@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
[OP: fixed minor context difference]
Signed-off-by: Ovidiu Panait <ovidiu.panait.rb@renesas.com>
---
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 2d4c693c419b..3f52a05c82d3 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -513,6 +513,7 @@ CONFIG_SPI_PL022=y
CONFIG_SPI_ROCKCHIP=y
CONFIG_SPI_RPCIF=m
CONFIG_SPI_RSPI=m
+CONFIG_SPI_RZV2H_RSPI=m
CONFIG_SPI_QCOM_QSPI=m
CONFIG_SPI_QUP=y
CONFIG_SPI_QCOM_GENI=m
--
2.34.1
^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH 6.1.y-cip 4/8] spi: dt-bindings: renesas,rzv2h-rspi: Document RZ/V2N SoC support
2026-04-15 13:19 [PATCH 6.1.y-cip 0/8] Add RSPI support for RZ/V2H and RZ/V2N Ovidiu Panait
` (2 preceding siblings ...)
2026-04-15 13:19 ` [PATCH 6.1.y-cip 3/8] arm64: defconfig: Enable the RZ/V2H(P) RSPI driver Ovidiu Panait
@ 2026-04-15 13:19 ` Ovidiu Panait
2026-04-15 13:19 ` [PATCH 6.1.y-cip 5/8] clk: renesas: r9a09g056: Add entries for the RSPIs Ovidiu Panait
` (4 subsequent siblings)
8 siblings, 0 replies; 11+ messages in thread
From: Ovidiu Panait @ 2026-04-15 13:19 UTC (permalink / raw)
To: cip-dev, pavel, nobuhiro.iwamatsu.x90
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
commit 043cc033451530f81d7fe791dcc29874f6a147fd upstream.
Document the RSPI controller on the Renesas RZ/V2N SoC. The block is
compatible with the RSPI implementation found on the RZ/V2H(P) family.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20251126131619.136605-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Mark Brown <broonie@kernel.org>
[OP: added oneOf list, as T2H support is not present in 6.1.y-cip]
Signed-off-by: Ovidiu Panait <ovidiu.panait.rb@renesas.com>
---
.../devicetree/bindings/spi/renesas,rzv2h-rspi.yaml | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/spi/renesas,rzv2h-rspi.yaml b/Documentation/devicetree/bindings/spi/renesas,rzv2h-rspi.yaml
index ab27fefc3c3a..394438b3d680 100644
--- a/Documentation/devicetree/bindings/spi/renesas,rzv2h-rspi.yaml
+++ b/Documentation/devicetree/bindings/spi/renesas,rzv2h-rspi.yaml
@@ -14,7 +14,11 @@ allOf:
properties:
compatible:
- const: renesas,r9a09g057-rspi # RZ/V2H(P)
+ oneOf:
+ - const: renesas,r9a09g057-rspi # RZ/V2H(P)
+ - items:
+ - const: renesas,r9a09g056-rspi # RZ/V2N
+ - const: renesas,r9a09g057-rspi
reg:
maxItems: 1
--
2.34.1
^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH 6.1.y-cip 5/8] clk: renesas: r9a09g056: Add entries for the RSPIs
2026-04-15 13:19 [PATCH 6.1.y-cip 0/8] Add RSPI support for RZ/V2H and RZ/V2N Ovidiu Panait
` (3 preceding siblings ...)
2026-04-15 13:19 ` [PATCH 6.1.y-cip 4/8] spi: dt-bindings: renesas,rzv2h-rspi: Document RZ/V2N SoC support Ovidiu Panait
@ 2026-04-15 13:19 ` Ovidiu Panait
2026-04-15 13:19 ` [PATCH 6.1.y-cip 6/8] clk: renesas: r9a09g057: " Ovidiu Panait
` (3 subsequent siblings)
8 siblings, 0 replies; 11+ messages in thread
From: Ovidiu Panait @ 2026-04-15 13:19 UTC (permalink / raw)
To: cip-dev, pavel, nobuhiro.iwamatsu.x90
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
commit d8921e42a1983024227c0e64253ea96b25a1ae9a upstream.
Add clock and reset entries for the RSPI IPs.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20251125221420.288809-4-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
[OP: fixed minor context difference]
Signed-off-by: Ovidiu Panait <ovidiu.panait.rb@renesas.com>
---
drivers/clk/renesas/r9a09g056-cpg.c | 24 ++++++++++++++++++++++++
1 file changed, 24 insertions(+)
diff --git a/drivers/clk/renesas/r9a09g056-cpg.c b/drivers/clk/renesas/r9a09g056-cpg.c
index 1c2b7c3a3821..fc092f57aed0 100644
--- a/drivers/clk/renesas/r9a09g056-cpg.c
+++ b/drivers/clk/renesas/r9a09g056-cpg.c
@@ -266,6 +266,24 @@ static const struct rzv2h_mod_clk r9a09g056_mod_clks[] __initconst = {
BUS_MSTOP(5, BIT(13))),
DEF_MOD("wdt_3_clk_loco", CLK_QEXTAL, 5, 2, 2, 18,
BUS_MSTOP(5, BIT(13))),
+ DEF_MOD("rspi_0_pclk", CLK_PLLCLN_DIV8, 5, 4, 2, 20,
+ BUS_MSTOP(11, BIT(0))),
+ DEF_MOD("rspi_0_pclk_sfr", CLK_PLLCLN_DIV8, 5, 5, 2, 21,
+ BUS_MSTOP(11, BIT(0))),
+ DEF_MOD("rspi_0_tclk", CLK_PLLCLN_DIV8, 5, 6, 2, 22,
+ BUS_MSTOP(11, BIT(0))),
+ DEF_MOD("rspi_1_pclk", CLK_PLLCLN_DIV8, 5, 7, 2, 23,
+ BUS_MSTOP(11, BIT(1))),
+ DEF_MOD("rspi_1_pclk_sfr", CLK_PLLCLN_DIV8, 5, 8, 2, 24,
+ BUS_MSTOP(11, BIT(1))),
+ DEF_MOD("rspi_1_tclk", CLK_PLLCLN_DIV8, 5, 9, 2, 25,
+ BUS_MSTOP(11, BIT(1))),
+ DEF_MOD("rspi_2_pclk", CLK_PLLCLN_DIV8, 5, 10, 2, 26,
+ BUS_MSTOP(11, BIT(2))),
+ DEF_MOD("rspi_2_pclk_sfr", CLK_PLLCLN_DIV8, 5, 11, 2, 27,
+ BUS_MSTOP(11, BIT(2))),
+ DEF_MOD("rspi_2_tclk", CLK_PLLCLN_DIV8, 5, 12, 2, 28,
+ BUS_MSTOP(11, BIT(2))),
DEF_MOD("scif_0_clk_pck", CLK_PLLCM33_DIV16, 8, 15, 4, 15,
BUS_MSTOP(3, BIT(14))),
DEF_MOD("riic_8_ckm", CLK_PLLCM33_DIV16, 9, 3, 4, 19,
@@ -402,6 +420,12 @@ static const struct rzv2h_reset r9a09g056_resets[] __initconst = {
DEF_RST(7, 6, 3, 7), /* WDT_1_RESET */
DEF_RST(7, 7, 3, 8), /* WDT_2_RESET */
DEF_RST(7, 8, 3, 9), /* WDT_3_RESET */
+ DEF_RST(7, 11, 3, 12), /* RSPI_0_PRESETN */
+ DEF_RST(7, 12, 3, 13), /* RSPI_0_TRESETN */
+ DEF_RST(7, 13, 3, 14), /* RSPI_1_PRESETN */
+ DEF_RST(7, 14, 3, 15), /* RSPI_1_TRESETN */
+ DEF_RST(7, 15, 3, 16), /* RSPI_2_PRESETN */
+ DEF_RST(8, 0, 3, 17), /* RSPI_2_TRESETN */
DEF_RST(9, 5, 4, 6), /* SCIF_0_RST_SYSTEM_N */
DEF_RST(9, 8, 4, 9), /* RIIC_0_MRST */
DEF_RST(9, 9, 4, 10), /* RIIC_1_MRST */
--
2.34.1
^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH 6.1.y-cip 6/8] clk: renesas: r9a09g057: Add entries for the RSPIs
2026-04-15 13:19 [PATCH 6.1.y-cip 0/8] Add RSPI support for RZ/V2H and RZ/V2N Ovidiu Panait
` (4 preceding siblings ...)
2026-04-15 13:19 ` [PATCH 6.1.y-cip 5/8] clk: renesas: r9a09g056: Add entries for the RSPIs Ovidiu Panait
@ 2026-04-15 13:19 ` Ovidiu Panait
2026-04-15 13:19 ` [PATCH 6.1.y-cip 7/8] arm64: dts: renesas: r9a09g056: Add RSPI nodes Ovidiu Panait
` (2 subsequent siblings)
8 siblings, 0 replies; 11+ messages in thread
From: Ovidiu Panait @ 2026-04-15 13:19 UTC (permalink / raw)
To: cip-dev, pavel, nobuhiro.iwamatsu.x90
From: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
commit 6132643bfdc928696205207027bce81d23b7ce59 upstream.
Add clock and reset entries for the Renesas RZ/V2H(P) RSPI IPs.
Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250624192304.338979-2-fabrizio.castro.jz@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
[OP: fixed minor context difference]
Signed-off-by: Ovidiu Panait <ovidiu.panait.rb@renesas.com>
---
drivers/clk/renesas/r9a09g057-cpg.c | 24 ++++++++++++++++++++++++
1 file changed, 24 insertions(+)
diff --git a/drivers/clk/renesas/r9a09g057-cpg.c b/drivers/clk/renesas/r9a09g057-cpg.c
index 9f18aef9fd76..f5715947e845 100644
--- a/drivers/clk/renesas/r9a09g057-cpg.c
+++ b/drivers/clk/renesas/r9a09g057-cpg.c
@@ -291,6 +291,24 @@ static const struct rzv2h_mod_clk r9a09g057_mod_clks[] __initconst = {
BUS_MSTOP(5, BIT(13))),
DEF_MOD("rtc_0_clk_rtc", CLK_PLLCM33_DIV16, 5, 3, 2, 19,
BUS_MSTOP(3, BIT(11) | BIT(12))),
+ DEF_MOD("rspi_0_pclk", CLK_PLLCLN_DIV8, 5, 4, 2, 20,
+ BUS_MSTOP(11, BIT(0))),
+ DEF_MOD("rspi_0_pclk_sfr", CLK_PLLCLN_DIV8, 5, 5, 2, 21,
+ BUS_MSTOP(11, BIT(0))),
+ DEF_MOD("rspi_0_tclk", CLK_PLLCLN_DIV8, 5, 6, 2, 22,
+ BUS_MSTOP(11, BIT(0))),
+ DEF_MOD("rspi_1_pclk", CLK_PLLCLN_DIV8, 5, 7, 2, 23,
+ BUS_MSTOP(11, BIT(1))),
+ DEF_MOD("rspi_1_pclk_sfr", CLK_PLLCLN_DIV8, 5, 8, 2, 24,
+ BUS_MSTOP(11, BIT(1))),
+ DEF_MOD("rspi_1_tclk", CLK_PLLCLN_DIV8, 5, 9, 2, 25,
+ BUS_MSTOP(11, BIT(1))),
+ DEF_MOD("rspi_2_pclk", CLK_PLLCLN_DIV8, 5, 10, 2, 26,
+ BUS_MSTOP(11, BIT(2))),
+ DEF_MOD("rspi_2_pclk_sfr", CLK_PLLCLN_DIV8, 5, 11, 2, 27,
+ BUS_MSTOP(11, BIT(2))),
+ DEF_MOD("rspi_2_tclk", CLK_PLLCLN_DIV8, 5, 12, 2, 28,
+ BUS_MSTOP(11, BIT(2))),
DEF_MOD("scif_0_clk_pck", CLK_PLLCM33_DIV16, 8, 15, 4, 15,
BUS_MSTOP(3, BIT(14))),
DEF_MOD("riic_8_ckm", CLK_PLLCM33_DIV16, 9, 3, 4, 19,
@@ -465,6 +483,12 @@ static const struct rzv2h_reset r9a09g057_resets[] __initconst = {
DEF_RST(7, 8, 3, 9), /* WDT_3_RESET */
DEF_RST(7, 9, 3, 10), /* RTC_0_RST_RTC */
DEF_RST(7, 10, 3, 11), /* RTC_0_RST_RTC_V */
+ DEF_RST(7, 11, 3, 12), /* RSPI_0_PRESETN */
+ DEF_RST(7, 12, 3, 13), /* RSPI_0_TRESETN */
+ DEF_RST(7, 13, 3, 14), /* RSPI_1_PRESETN */
+ DEF_RST(7, 14, 3, 15), /* RSPI_1_TRESETN */
+ DEF_RST(7, 15, 3, 16), /* RSPI_2_PRESETN */
+ DEF_RST(8, 0, 3, 17), /* RSPI_2_TRESETN */
DEF_RST(9, 5, 4, 6), /* SCIF_0_RST_SYSTEM_N */
DEF_RST(9, 8, 4, 9), /* RIIC_0_MRST */
DEF_RST(9, 9, 4, 10), /* RIIC_1_MRST */
--
2.34.1
^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH 6.1.y-cip 7/8] arm64: dts: renesas: r9a09g056: Add RSPI nodes
2026-04-15 13:19 [PATCH 6.1.y-cip 0/8] Add RSPI support for RZ/V2H and RZ/V2N Ovidiu Panait
` (5 preceding siblings ...)
2026-04-15 13:19 ` [PATCH 6.1.y-cip 6/8] clk: renesas: r9a09g057: " Ovidiu Panait
@ 2026-04-15 13:19 ` Ovidiu Panait
2026-04-15 13:19 ` [PATCH 6.1.y-cip 8/8] arm64: dts: renesas: r9a09g057: " Ovidiu Panait
2026-04-16 20:52 ` [cip-dev] [PATCH 6.1.y-cip 0/8] Add RSPI support for RZ/V2H and RZ/V2N Pavel Machek
8 siblings, 0 replies; 11+ messages in thread
From: Ovidiu Panait @ 2026-04-15 13:19 UTC (permalink / raw)
To: cip-dev, pavel, nobuhiro.iwamatsu.x90
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
commit 4018dfc222a793f6a4fc5dfb98c883ef3782eb0f upstream.
Add nodes for the RSPI IPs found in the Renesas RZ/V2N SoC.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20251125224533.294235-4-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Ovidiu Panait <ovidiu.panait.rb@renesas.com>
---
arch/arm64/boot/dts/renesas/r9a09g056.dtsi | 63 ++++++++++++++++++++++
1 file changed, 63 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a09g056.dtsi b/arch/arm64/boot/dts/renesas/r9a09g056.dtsi
index d69b3d3d1835..5df4ef4a593b 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g056.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g056.dtsi
@@ -716,6 +716,69 @@ channel5 {
};
};
+ rspi0: spi@12800000 {
+ compatible = "renesas,r9a09g056-rspi", "renesas,r9a09g057-rspi";
+ reg = <0x0 0x12800000 0x0 0x400>;
+ interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 107 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 500 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 501 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "idle", "error", "end", "rx", "tx";
+ clocks = <&cpg CPG_MOD 0x54>,
+ <&cpg CPG_MOD 0x55>,
+ <&cpg CPG_MOD 0x56>;
+ clock-names = "pclk", "pclk_sfr", "tclk";
+ resets = <&cpg 0x7b>, <&cpg 0x7c>;
+ reset-names = "presetn", "tresetn";
+ power-domains = <&cpg>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ rspi1: spi@12800400 {
+ compatible = "renesas,r9a09g056-rspi", "renesas,r9a09g057-rspi";
+ reg = <0x0 0x12800400 0x0 0x400>;
+ interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 110 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 502 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 503 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "idle", "error", "end", "rx", "tx";
+ clocks = <&cpg CPG_MOD 0x57>,
+ <&cpg CPG_MOD 0x58>,
+ <&cpg CPG_MOD 0x59>;
+ clock-names = "pclk", "pclk_sfr", "tclk";
+ resets = <&cpg 0x7d>, <&cpg 0x7e>;
+ reset-names = "presetn", "tresetn";
+ power-domains = <&cpg>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ rspi2: spi@12800800 {
+ compatible = "renesas,r9a09g056-rspi", "renesas,r9a09g057-rspi";
+ reg = <0x0 0x12800800 0x0 0x400>;
+ interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 113 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 504 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 505 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "idle", "error", "end", "rx", "tx";
+ clocks = <&cpg CPG_MOD 0x5a>,
+ <&cpg CPG_MOD 0x5b>,
+ <&cpg CPG_MOD 0x5c>;
+ clock-names = "pclk", "pclk_sfr", "tclk";
+ resets = <&cpg 0x7f>, <&cpg 0x80>;
+ reset-names = "presetn", "tresetn";
+ power-domains = <&cpg>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
i2c0: i2c@14400400 {
compatible = "renesas,riic-r9a09g056", "renesas,riic-r9a09g057";
reg = <0 0x14400400 0 0x400>;
--
2.34.1
^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH 6.1.y-cip 8/8] arm64: dts: renesas: r9a09g057: Add RSPI nodes
2026-04-15 13:19 [PATCH 6.1.y-cip 0/8] Add RSPI support for RZ/V2H and RZ/V2N Ovidiu Panait
` (6 preceding siblings ...)
2026-04-15 13:19 ` [PATCH 6.1.y-cip 7/8] arm64: dts: renesas: r9a09g056: Add RSPI nodes Ovidiu Panait
@ 2026-04-15 13:19 ` Ovidiu Panait
2026-04-16 20:52 ` [cip-dev] [PATCH 6.1.y-cip 0/8] Add RSPI support for RZ/V2H and RZ/V2N Pavel Machek
8 siblings, 0 replies; 11+ messages in thread
From: Ovidiu Panait @ 2026-04-15 13:19 UTC (permalink / raw)
To: cip-dev, pavel, nobuhiro.iwamatsu.x90
From: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
commit c494de2e00fb06d5b62708a91d7dda701abc52f4 upstream.
Add nodes for the RSPI IPs found in the Renesas RZ/V2H(P) SoC.
Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250624192304.338979-7-fabrizio.castro.jz@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Ovidiu Panait <ovidiu.panait.rb@renesas.com>
---
arch/arm64/boot/dts/renesas/r9a09g057.dtsi | 63 ++++++++++++++++++++++
1 file changed, 63 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
index 119bbe8c0f4f..5ab873a4702e 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
@@ -712,6 +712,69 @@ channel5 {
};
};
+ rspi0: spi@12800000 {
+ compatible = "renesas,r9a09g057-rspi";
+ reg = <0x0 0x12800000 0x0 0x400>;
+ interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 107 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 500 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 501 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "idle", "error", "end", "rx", "tx";
+ clocks = <&cpg CPG_MOD 0x54>,
+ <&cpg CPG_MOD 0x55>,
+ <&cpg CPG_MOD 0x56>;
+ clock-names = "pclk", "pclk_sfr", "tclk";
+ resets = <&cpg 0x7b>, <&cpg 0x7c>;
+ reset-names = "presetn", "tresetn";
+ power-domains = <&cpg>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ rspi1: spi@12800400 {
+ compatible = "renesas,r9a09g057-rspi";
+ reg = <0x0 0x12800400 0x0 0x400>;
+ interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 110 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 502 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 503 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "idle", "error", "end", "rx", "tx";
+ clocks = <&cpg CPG_MOD 0x57>,
+ <&cpg CPG_MOD 0x58>,
+ <&cpg CPG_MOD 0x59>;
+ clock-names = "pclk", "pclk_sfr", "tclk";
+ resets = <&cpg 0x7d>, <&cpg 0x7e>;
+ reset-names = "presetn", "tresetn";
+ power-domains = <&cpg>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ rspi2: spi@12800800 {
+ compatible = "renesas,r9a09g057-rspi";
+ reg = <0x0 0x12800800 0x0 0x400>;
+ interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 113 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 504 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 505 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "idle", "error", "end", "rx", "tx";
+ clocks = <&cpg CPG_MOD 0x5a>,
+ <&cpg CPG_MOD 0x5b>,
+ <&cpg CPG_MOD 0x5c>;
+ clock-names = "pclk", "pclk_sfr", "tclk";
+ resets = <&cpg 0x7f>, <&cpg 0x80>;
+ reset-names = "presetn", "tresetn";
+ power-domains = <&cpg>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
i2c0: i2c@14400400 {
compatible = "renesas,riic-r9a09g057";
reg = <0 0x14400400 0 0x400>;
--
2.34.1
^ permalink raw reply related [flat|nested] 11+ messages in thread* Re: [cip-dev] [PATCH 6.1.y-cip 0/8] Add RSPI support for RZ/V2H and RZ/V2N
2026-04-15 13:19 [PATCH 6.1.y-cip 0/8] Add RSPI support for RZ/V2H and RZ/V2N Ovidiu Panait
` (7 preceding siblings ...)
2026-04-15 13:19 ` [PATCH 6.1.y-cip 8/8] arm64: dts: renesas: r9a09g057: " Ovidiu Panait
@ 2026-04-16 20:52 ` Pavel Machek
8 siblings, 0 replies; 11+ messages in thread
From: Pavel Machek @ 2026-04-16 20:52 UTC (permalink / raw)
To: ovidiu.panait.rb; +Cc: cip-dev, pavel, nobuhiro.iwamatsu.x90
[-- Attachment #1: Type: text/plain, Size: 473 bytes --]
Hi!
> This series adds RSPI support for the Renesas RZ/V2H and RZ/V2N SoCs.
>
> Patches were cherry-picked from mainline kernel.
I had some minor comments here, but those should be fixed in mainline,
first, so they should not block the merge.
Reviewed-by: Pavel Machek <pavel@nabladev.com>
I can apply the series if it passes testing and there are no other
comments.
Best regards,
Pavel
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^ permalink raw reply [flat|nested] 11+ messages in thread