Re: [cip-dev] [PATCH 6.1.y-cip 17/32] spi: rzv2h-rspi: add support for RZ/T2H and RZ/N2H

[Pavel Machek <pavel@nabladev.com>]

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HI!

> Compared to the previously supported RZ/V2H, the Renesas RZ/T2H
> (R9A09G077) and RZ/N2H (R9A09G087) SoCs have a smaller FIFO, no resets,
> and only two clocks: PCLKSPIn and PCLK. PCLKSPIn, being the clock from
> which the SPI transfer clock is generated, is the equivalent of the TCLK
> clock from RZ/V2H. They also support generating the SPI transfer clock
> from PCLK.
> 
> PCLKSPIn supports multiple dividers, generating multiple possible
> frequencies from its parent. To handle this, do the following changes.
> 
> Use the minimum frequency of SPI clock to calculate the SPI controller's
> min_speed_hz, and the maximum frequency to calculate max_speed_hz.
> 
> Add a new function, rzv2h_rspi_find_rate_variable(), which is used for
> the .find_tclk_rate() callback, and which supports handling clocks with
> a variable rate, with the following overall logic.
> 
> Iterate through all possible BRDV values.
> 
> For each BRDV, calculate two different SPRs, one for the clock's minimum
> frequency, and one for the maxmimum, and iterate through each SPR
> between them.
> 
> If the minimum SPR is higher than the upper SPR limit, the minimum rate
> is too high to achieve the requested SPI frequency, skip to the next
> BRDV.
> 
> For each SPR, calculate a rate and let the clock framework round it to
> the closest supported rate of the clock.
> 
> The rate and SPR that generate a transfer frequency closest to the
> requested SPI transfer frequency will be picked.
> 
> Signed-off-by: Cosmin Tanislav <cosmin-gabriel.tanislav.xa@renesas.com>
> Link: https://patch.msgid.link/20251119161434.595677-12-cosmin-gabriel.tanislav.xa@renesas.com
> Signed-off-by: Mark Brown <broonie@kernel.org>
> Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
> ---
>  drivers/spi/spi-rzv2h-rspi.c | 108 +++++++++++++++++++++++++++++++++++
>  1 file changed, 108 insertions(+)
> 
> diff --git a/drivers/spi/spi-rzv2h-rspi.c b/drivers/spi/spi-rzv2h-rspi.c
> index 3c1cb76bc7b4..2f4feaedaf97 100644
> --- a/drivers/spi/spi-rzv2h-rspi.c
> +++ b/drivers/spi/spi-rzv2h-rspi.c
> @@ -258,6 +258,105 @@ static inline u32 rzv2h_rspi_calc_bitrate(unsigned long tclk_rate, u8 spr,
>  	return DIV_ROUND_UP(tclk_rate, (2 * (spr + 1) * (1 << brdv)));
>  }
>  
> +static void rzv2h_rspi_find_rate_variable(struct clk *clk, u32 hz,
> +					  u8 spr_min, u8 spr_max,
> +					  struct rzv2h_rspi_best_clock *best)
> +{
> +	long clk_rate, clk_min_rate, clk_max_rate;
> +	int min_rate_spr, max_rate_spr;
> +	unsigned long error;
> +	u32 actual_hz;
> +	u8 brdv;
> +	int spr;
> +
> +	/*
> +	 * On T2H / N2H, the source for the SPI clock is PCLKSPIn, which is a
> +	 * 1/32, 1/30, 1/25 or 1/24 divider of PLL4, which is 2400MHz,
> +	 * resulting in either 75MHz, 80MHz, 96MHz or 100MHz.
> +	 */
> +	clk_min_rate = clk_round_rate(clk, 0);
> +	if (clk_min_rate < 0)
> +		return;

These are clearly failures, yet we are returning void. That is not
usual coding style.

Best regards,
								Pavel

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