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From: Pavel Machek <pavel@nabladev.com>
To: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Cc: cip-dev@lists.cip-project.org,
	Nobuhiro Iwamatsu <nobuhiro.iwamatsu.x90@mail.toshiba>,
	Pavel Machek <pavel@nabladev.com>,
	Biju Das <biju.das.jz@bp.renesas.com>
Subject: Re: [PATCH 6.12.y-cip v2 03/10] pinctrl: renesas: rzt2h: Allow .get_direction() for IRQ function GPIOs
Date: Tue, 7 Jul 2026 22:17:28 +0200	[thread overview]
Message-ID: <ak1e2EgPQdSVIf6A@duo.ucw.cz> (raw)
In-Reply-To: <20260702102349.23431-4-prabhakar.mahadev-lad.rj@bp.renesas.com>

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Hi!

> Hold the spinlock to ensure atomicity between reading the PMC register
> (which determines whether the pin is in GPIO mode or not) and reading
> the function of the pin when it is not in GPIO mode.

Ok, so according to this, two reads need to be protected.

> index 981a34dcc814e..f056e28f6a17e 100644
> --- a/drivers/pinctrl/renesas/pinctrl-rzt2h.c
> +++ b/drivers/pinctrl/renesas/pinctrl-rzt2h.c
> @@ -501,8 +503,25 @@ static int rzt2h_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
>  	if (ret)
>  		return ret;
>  
> -	if (rzt2h_pinctrl_readb(pctrl, port, PMC(port)) & BIT(bit))
> +	guard(spinlock_irqsave)(&pctrl->lock);
> +
> +	if (rzt2h_pinctrl_readb(pctrl, port, PMC(port)) & BIT(bit)) {
> +		/*
> +		 * When a GPIO is being requested as an IRQ, the pinctrl
> +		 * framework expects to be able to read the GPIO's direction.
> +		 * IRQ function is separate from GPIO, and enabling it takes the
> +		 * pin out of GPIO mode.
> +		 * At this point, .child_to_parent_hwirq() has already been
> +		 * called to enable the IRQ function.
> +		 * Default to input direction for IRQ function.
> +		 */
> +		reg64 = rzt2h_pinctrl_readq(pctrl, port, PFC(port));
> +		reg64 = (reg64 >> (bit * 8)) & PFC_MASK;
> +		if (reg64 == PFC_FUNC_INTERRUPT)
> +			return GPIO_LINE_DIRECTION_IN;
> +
>  		return -EINVAL;
> +	}
>  
>  	reg = rzt2h_pinctrl_readw(pctrl, port, PM(port));
>  	reg = (reg >> (bit * 2)) & PM_MASK;

But AFAICT here, whole rest of the function is running with spinlock
held/interrupts disabled. Is that neccessary?

Thanks and best regards,
								Pavel

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  reply	other threads:[~2026-07-07 20:17 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-07-02 10:23 [PATCH 6.12.y-cip v2 00/10] Add pin configuration and GPIO IRQ support to Renesas RZ/T2H SoC Lad Prabhakar
2026-07-02 10:23 ` [PATCH 6.12.y-cip v2 01/10] pinctrl: renesas: Remove unneeded semicolons Lad Prabhakar
2026-07-02 10:23 ` [PATCH 6.12.y-cip v2 02/10] pinctrl: renesas: rzt2h: Move GPIO enable/disable into separate function Lad Prabhakar
2026-07-02 10:23 ` [PATCH 6.12.y-cip v2 03/10] pinctrl: renesas: rzt2h: Allow .get_direction() for IRQ function GPIOs Lad Prabhakar
2026-07-07 20:17   ` Pavel Machek [this message]
2026-07-02 10:23 ` [PATCH 6.12.y-cip v2 04/10] pinctrl: renesas: rzt2h: Add GPIO IRQ chip to handle interrupts Lad Prabhakar
2026-07-02 10:23 ` [PATCH 6.12.y-cip v2 05/10] pinctrl: renesas: rzt2h: Fix device node leak in rzt2h_gpio_register() Lad Prabhakar
2026-07-02 10:23 ` [PATCH 6.12.y-cip v2 06/10] pinctrl: renesas: rzt2h: Fix invalid wait context Lad Prabhakar
2026-07-02 10:23 ` [PATCH 6.12.y-cip v2 07/10] dt-bindings: pinctrl: renesas,r9a09g077: Document pin configuration properties Lad Prabhakar
2026-07-07 20:17   ` Pavel Machek
2026-07-02 10:23 ` [PATCH 6.12.y-cip v2 08/10] pinctrl: renesas: rzt2h: Add pin configuration support Lad Prabhakar
2026-07-02 10:23 ` [PATCH 6.12.y-cip v2 09/10] pinctrl: renesas: rzt2h: Remove unused variable in rzt2h_pinctrl_register() Lad Prabhakar
2026-07-02 10:23 ` [PATCH 6.12.y-cip v2 10/10] pinctrl: renesas: rzt2h: Skip PFC mode configuration if already set Lad Prabhakar
2026-07-07  8:19 ` [PATCH 6.12.y-cip v2 00/10] Add pin configuration and GPIO IRQ support to Renesas RZ/T2H SoC nobuhiro.iwamatsu.x90
2026-07-07 20:17   ` [cip-dev] " Pavel Machek

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