* [PATCH 6.12.y-cip 1/3] arm64: dts: renesas: r9a07g043: Add max-frequency to SDHI nodes
2026-07-14 10:18 [PATCH 6.12.y-cip 0/3] arm64: dts: renesas: Add max-frequency to SDHI nodes Biju
@ 2026-07-14 10:18 ` Biju
2026-07-14 10:18 ` [PATCH 6.12.y-cip 2/3] arm64: dts: renesas: r9a07g044: " Biju
` (3 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: Biju @ 2026-07-14 10:18 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das, Lad Prabhakar
From: Biju Das <biju.das.jz@bp.renesas.com>
[ Upstream commit f82892de7f4878f54a4035be06f3acc6e6449616 ]
Add the max-frequency property set to 133333333 Hz (133.33 MHz) to both
SDHI0 and SDHI1 MMC controller nodes in the RZ/{G2UL,Five} (r9a07g043)
device tree, increasing performance by ca. 33%.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20260520115144.60067-2-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
arch/arm64/boot/dts/renesas/r9a07g043.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi
index 593c66b27ad1..ff5f6b9c1e74 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi
@@ -655,6 +655,7 @@ sdhi0: mmc@11c00000 {
<&cpg CPG_MOD R9A07G043_SDHI0_IMCLK2>,
<&cpg CPG_MOD R9A07G043_SDHI0_ACLK>;
clock-names = "core", "clkh", "cd", "aclk";
+ max-frequency = <133333333>;
resets = <&cpg R9A07G043_SDHI0_IXRST>;
power-domains = <&cpg>;
status = "disabled";
@@ -671,6 +672,7 @@ sdhi1: mmc@11c10000 {
<&cpg CPG_MOD R9A07G043_SDHI1_IMCLK2>,
<&cpg CPG_MOD R9A07G043_SDHI1_ACLK>;
clock-names = "core", "clkh", "cd", "aclk";
+ max-frequency = <133333333>;
resets = <&cpg R9A07G043_SDHI1_IXRST>;
power-domains = <&cpg>;
status = "disabled";
--
2.43.0
^ permalink raw reply related [flat|nested] 6+ messages in thread* [PATCH 6.12.y-cip 2/3] arm64: dts: renesas: r9a07g044: Add max-frequency to SDHI nodes
2026-07-14 10:18 [PATCH 6.12.y-cip 0/3] arm64: dts: renesas: Add max-frequency to SDHI nodes Biju
2026-07-14 10:18 ` [PATCH 6.12.y-cip 1/3] arm64: dts: renesas: r9a07g043: " Biju
@ 2026-07-14 10:18 ` Biju
2026-07-14 10:18 ` [PATCH 6.12.y-cip 3/3] arm64: dts: renesas: r9a07g054: " Biju
` (2 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: Biju @ 2026-07-14 10:18 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das, Lad Prabhakar
From: Biju Das <biju.das.jz@bp.renesas.com>
[ Upstream commit 1b3c392bd655af31a414fc82382cec13e090a997 ]
Add the max-frequency property set to 133333333 Hz (133.33 MHz) to both
SDHI0 and SDHI1 MMC controller nodes in the RZ/{G2L,G2LC} (r9a07g044)
device tree, increasing performance by ca. 33%.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20260520115144.60067-3-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
index 6b1c77cd8261..90f4d9d8c62a 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
@@ -1059,6 +1059,7 @@ sdhi0: mmc@11c00000 {
<&cpg CPG_MOD R9A07G044_SDHI0_IMCLK2>,
<&cpg CPG_MOD R9A07G044_SDHI0_ACLK>;
clock-names = "core", "clkh", "cd", "aclk";
+ max-frequency = <133333333>;
resets = <&cpg R9A07G044_SDHI0_IXRST>;
power-domains = <&cpg>;
status = "disabled";
@@ -1075,6 +1076,7 @@ sdhi1: mmc@11c10000 {
<&cpg CPG_MOD R9A07G044_SDHI1_IMCLK2>,
<&cpg CPG_MOD R9A07G044_SDHI1_ACLK>;
clock-names = "core", "clkh", "cd", "aclk";
+ max-frequency = <133333333>;
resets = <&cpg R9A07G044_SDHI1_IXRST>;
power-domains = <&cpg>;
status = "disabled";
--
2.43.0
^ permalink raw reply related [flat|nested] 6+ messages in thread* [PATCH 6.12.y-cip 3/3] arm64: dts: renesas: r9a07g054: Add max-frequency to SDHI nodes
2026-07-14 10:18 [PATCH 6.12.y-cip 0/3] arm64: dts: renesas: Add max-frequency to SDHI nodes Biju
2026-07-14 10:18 ` [PATCH 6.12.y-cip 1/3] arm64: dts: renesas: r9a07g043: " Biju
2026-07-14 10:18 ` [PATCH 6.12.y-cip 2/3] arm64: dts: renesas: r9a07g044: " Biju
@ 2026-07-14 10:18 ` Biju
2026-07-14 18:30 ` [PATCH 6.12.y-cip 0/3] arm64: dts: renesas: " Pavel Machek
2026-07-15 9:30 ` Pavel Machek
4 siblings, 0 replies; 6+ messages in thread
From: Biju @ 2026-07-14 10:18 UTC (permalink / raw)
To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das, Lad Prabhakar
From: Biju Das <biju.das.jz@bp.renesas.com>
[ Upstream commit dcbbb1266043d1d7ca1f129d2ca58a6ce8e04cbb ]
Add the max-frequency property set to 133333333 Hz (133.33 MHz) to both
SDHI0 and SDHI1 MMC controller nodes in the RZ/V2L (r9a07g054) device
tree, increasing performance by ca. 33%.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20260520115144.60067-4-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
arch/arm64/boot/dts/renesas/r9a07g054.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi
index 01f59914dd09..19b5c083d601 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi
@@ -1067,6 +1067,7 @@ sdhi0: mmc@11c00000 {
<&cpg CPG_MOD R9A07G054_SDHI0_IMCLK2>,
<&cpg CPG_MOD R9A07G054_SDHI0_ACLK>;
clock-names = "core", "clkh", "cd", "aclk";
+ max-frequency = <133333333>;
resets = <&cpg R9A07G054_SDHI0_IXRST>;
power-domains = <&cpg>;
status = "disabled";
@@ -1083,6 +1084,7 @@ sdhi1: mmc@11c10000 {
<&cpg CPG_MOD R9A07G054_SDHI1_IMCLK2>,
<&cpg CPG_MOD R9A07G054_SDHI1_ACLK>;
clock-names = "core", "clkh", "cd", "aclk";
+ max-frequency = <133333333>;
resets = <&cpg R9A07G054_SDHI1_IXRST>;
power-domains = <&cpg>;
status = "disabled";
--
2.43.0
^ permalink raw reply related [flat|nested] 6+ messages in thread* Re: [PATCH 6.12.y-cip 0/3] arm64: dts: renesas: Add max-frequency to SDHI nodes
2026-07-14 10:18 [PATCH 6.12.y-cip 0/3] arm64: dts: renesas: Add max-frequency to SDHI nodes Biju
` (2 preceding siblings ...)
2026-07-14 10:18 ` [PATCH 6.12.y-cip 3/3] arm64: dts: renesas: r9a07g054: " Biju
@ 2026-07-14 18:30 ` Pavel Machek
2026-07-15 9:30 ` Pavel Machek
4 siblings, 0 replies; 6+ messages in thread
From: Pavel Machek @ 2026-07-14 18:30 UTC (permalink / raw)
To: Biju; +Cc: cip-dev, Nobuhiro Iwamatsu, Pavel Machek, Biju Das, Lad Prabhakar
[-- Attachment #1: Type: text/plain, Size: 645 bytes --]
Hi!
> This patch series aims to add the max-frequency property set to
> 133333333 Hz (133.33 MHz) to both SDHI0 and SDHI1 MMC controller nodes in
> the RZ/G2{L,LC,UL}/RZ/V2L device tree.
>
> This change results in approximately 33% performance improvement as
> it sets the SD clk to 100 MHz instead of the max 133 MHz.
>
> All the patches in this series are cherry-picked from mainline.
This looks okay to me.
Reviewed-by: Pavel Machek <pavel@nabladev.com>
I can apply the series if it passes testing and there are no other
comments.
Best regards,
Pavel
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^ permalink raw reply [flat|nested] 6+ messages in thread* Re: [PATCH 6.12.y-cip 0/3] arm64: dts: renesas: Add max-frequency to SDHI nodes
2026-07-14 10:18 [PATCH 6.12.y-cip 0/3] arm64: dts: renesas: Add max-frequency to SDHI nodes Biju
` (3 preceding siblings ...)
2026-07-14 18:30 ` [PATCH 6.12.y-cip 0/3] arm64: dts: renesas: " Pavel Machek
@ 2026-07-15 9:30 ` Pavel Machek
4 siblings, 0 replies; 6+ messages in thread
From: Pavel Machek @ 2026-07-15 9:30 UTC (permalink / raw)
To: Biju; +Cc: cip-dev, Nobuhiro Iwamatsu, Pavel Machek, Biju Das, Lad Prabhakar
[-- Attachment #1: Type: text/plain, Size: 455 bytes --]
Hi!
> This patch series aims to add the max-frequency property set to
> 133333333 Hz (133.33 MHz) to both SDHI0 and SDHI1 MMC controller nodes in
> the RZ/G2{L,LC,UL}/RZ/V2L device tree.
>
> This change results in approximately 33% performance improvement as
> it sets the SD clk to 100 MHz instead of the max 133 MHz.
>
> All the patches in this series are cherry-picked from mainline.
Thank you, applied.
Best regards,
Pavel
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^ permalink raw reply [flat|nested] 6+ messages in thread